ad9081_fmca_ebz:zcu102: initial version
Laszlo Nagy
Laszlo Nagy
parent
f3630dd95b
commit
f3a7fd8b0d
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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PROJECT_NAME := ad9081_fmca_ebz_zcu102
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M_DEPS += timing_constr.xdc
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M_DEPS += ../common/ad9081_fmca_ebz_bd.tcl
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M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
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M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
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M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
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M_DEPS += ../../common/xilinx/adcfifo_bd.tcl
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M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
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M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
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M_DEPS += ../../../library/common/ad_3w_spi.v
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_sysid
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LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
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LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
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LIB_DEPS += jesd204/axi_jesd204_rx
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LIB_DEPS += jesd204/axi_jesd204_tx
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LIB_DEPS += jesd204/jesd204_rx
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LIB_DEPS += jesd204/jesd204_tx
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LIB_DEPS += sysid_rom
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LIB_DEPS += util_adcfifo
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LIB_DEPS += util_dacfifo
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += util_pack/util_upack2
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LIB_DEPS += xilinx/axi_adxcvr
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LIB_DEPS += xilinx/util_adxcvr
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include ../../scripts/project-xilinx.mk
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## ADC FIFO depth in samples per converter
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set adc_fifo_samples_per_converter [expr 64*1024]
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## DAC FIFO depth in samples per converter
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set dac_fifo_samples_per_converter [expr 64*1024]
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source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
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source ../common/ad9081_fmca_ebz_bd.tcl
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#system ID
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ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
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ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
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ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
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set sys_cstring "sys rom custom string placeholder"
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sysid_gen_sys_init_file $sys_cstring
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# Parameters for 15.5Gpbs lane rate
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ad_ip_parameter util_mxfe_xcvr CONFIG.RX_CLK25_DIV 31
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ad_ip_parameter util_mxfe_xcvr CONFIG.TX_CLK25_DIV 31
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ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG0 0x1fa
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ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG1 0x23
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ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG2 0x2
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ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_FBDIV 2
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ad_ip_parameter util_mxfe_xcvr CONFIG.A_TXDIFFCTRL 0xc
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG0 0x3
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG2_GEN2 0x265
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG2_GEN4 0x164
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3 0x1A
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN2 0x1A
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN3 0x1A
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN4 0x12
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ad_ip_parameter util_mxfe_xcvr CONFIG.CH_HSPMUX 0x6868
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ad_ip_parameter util_mxfe_xcvr CONFIG.PREIQ_FREQ_BST 1
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG0 0x4
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG1 0x0
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ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG 0x0
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ad_ip_parameter util_mxfe_xcvr CONFIG.TX_PI_BIASSET 3
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ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_REFCLK_DIV 1
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ad_ip_parameter util_mxfe_xcvr CONFIG.POR_CFG 0x0
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ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG0 0x333c
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ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG4 0x45
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ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_FBDIV 20
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ad_ip_parameter util_mxfe_xcvr CONFIG.PPF0_CFG 0xF00
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ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CP 0xFF
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ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CP_G3 0xF
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ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_LPF 0x2FF
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#
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## mxfe
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#
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set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVCMOS18 } [get_ports agc0[0] ] ; ## FMC0_LA17_CC_P IO_L13P_T2L_N0_GC_QBC_67
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set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVCMOS18 } [get_ports agc0[1] ] ; ## FMC0_LA17_CC_N IO_L13N_T2L_N1_GC_QBC_67
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set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18 } [get_ports agc1[0] ] ; ## FMC0_LA18_CC_P IO_L16P_T2U_N6_QBC_AD3P_67
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set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18 } [get_ports agc1[1] ] ; ## FMC0_LA18_CC_N IO_L16N_T2U_N7_QBC_AD3N_67
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set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS18 } [get_ports agc2[0] ] ; ## FMC0_LA20_P IO_L22P_T3U_N6_DBC_AD0P_67
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set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS18 } [get_ports agc2[1] ] ; ## FMC0_LA20_N IO_L22N_T3U_N7_DBC_AD0N_67
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set_property -dict {PACKAGE_PIN P12 IOSTANDARD LVCMOS18 } [get_ports agc3[0] ] ; ## FMC0_LA21_P IO_L21P_T3L_N4_AD8P_67
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set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS18 } [get_ports agc3[1] ] ; ## FMC0_LA21_N IO_L21N_T3L_N5_AD8N_67
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set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVDS } [get_ports clkin10_n ] ; ## FMC0_CLK2_IO_N IO_L13N_T2L_N1_GC_QBC_66
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set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVDS } [get_ports clkin10_p ] ; ## FMC0_CLK2_IO_P IO_L13P_T2L_N0_GC_QBC_66
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set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVDS } [get_ports clkin6_n ] ; ## FMC0_CLK1_M2C_N IO_L12N_T1U_N11_GC_67
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set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVDS } [get_ports clkin6_p ] ; ## FMC0_CLK1_M2C_P IO_L12P_T1U_N10_GC_67
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set_property -dict {PACKAGE_PIN G7 } [get_ports fpga_refclk_in_n ] ; ## FMC0_GBTCLK0_M2C_N MGTREFCLK0N_229
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set_property -dict {PACKAGE_PIN G8 } [get_ports fpga_refclk_in_p ] ; ## FMC0_GBTCLK0_M2C_P MGTREFCLK0P_229
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set_property -quiet -dict {PACKAGE_PIN F1 } [get_ports rx_data_n[2] ] ; ## FMC0_DP2_M2C_N MGTHRXN3_229 FPGA_SERDIN_0_N
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set_property -quiet -dict {PACKAGE_PIN F2 } [get_ports rx_data_p[2] ] ; ## FMC0_DP2_M2C_P MGTHRXP3_229 FPGA_SERDIN_0_P
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set_property -quiet -dict {PACKAGE_PIN H1 } [get_ports rx_data_n[0] ] ; ## FMC0_DP0_M2C_N MGTHRXN2_229 FPGA_SERDIN_1_N
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set_property -quiet -dict {PACKAGE_PIN H2 } [get_ports rx_data_p[0] ] ; ## FMC0_DP0_M2C_P MGTHRXP2_229 FPGA_SERDIN_1_P
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set_property -quiet -dict {PACKAGE_PIN M1 } [get_ports rx_data_n[7] ] ; ## FMC0_DP7_M2C_N MGTHRXN2_228 FPGA_SERDIN_2_N
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set_property -quiet -dict {PACKAGE_PIN M2 } [get_ports rx_data_p[7] ] ; ## FMC0_DP7_M2C_P MGTHRXP2_228 FPGA_SERDIN_2_P
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set_property -quiet -dict {PACKAGE_PIN T1 } [get_ports rx_data_n[6] ] ; ## FMC0_DP6_M2C_N MGTHRXN0_228 FPGA_SERDIN_3_N
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set_property -quiet -dict {PACKAGE_PIN T2 } [get_ports rx_data_p[6] ] ; ## FMC0_DP6_M2C_P MGTHRXP0_228 FPGA_SERDIN_3_P
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set_property -quiet -dict {PACKAGE_PIN P1 } [get_ports rx_data_n[5] ] ; ## FMC0_DP5_M2C_N MGTHRXN1_228 FPGA_SERDIN_4_N
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set_property -quiet -dict {PACKAGE_PIN P2 } [get_ports rx_data_p[5] ] ; ## FMC0_DP5_M2C_P MGTHRXP1_228 FPGA_SERDIN_4_P
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set_property -quiet -dict {PACKAGE_PIN L3 } [get_ports rx_data_n[4] ] ; ## FMC0_DP4_M2C_N MGTHRXN3_228 FPGA_SERDIN_5_N
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set_property -quiet -dict {PACKAGE_PIN L4 } [get_ports rx_data_p[4] ] ; ## FMC0_DP4_M2C_P MGTHRXP3_228 FPGA_SERDIN_5_P
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set_property -quiet -dict {PACKAGE_PIN K1 } [get_ports rx_data_n[3] ] ; ## FMC0_DP3_M2C_N MGTHRXN0_229 FPGA_SERDIN_6_N
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set_property -quiet -dict {PACKAGE_PIN K2 } [get_ports rx_data_p[3] ] ; ## FMC0_DP3_M2C_P MGTHRXP0_229 FPGA_SERDIN_6_P
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set_property -quiet -dict {PACKAGE_PIN J3 } [get_ports rx_data_n[1] ] ; ## FMC0_DP1_M2C_N MGTHRXN1_229 FPGA_SERDIN_7_N
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set_property -quiet -dict {PACKAGE_PIN J4 } [get_ports rx_data_p[1] ] ; ## FMC0_DP1_M2C_P MGTHRXP1_229 FPGA_SERDIN_7_P
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set_property -quiet -dict {PACKAGE_PIN G3 } [get_ports tx_data_n[0] ] ; ## FMC0_DP0_C2M_N MGTHTXN2_229 FPGA_SERDOUT_0_N
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set_property -quiet -dict {PACKAGE_PIN G4 } [get_ports tx_data_p[0] ] ; ## FMC0_DP0_C2M_P MGTHTXP2_229 FPGA_SERDOUT_0_P
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set_property -quiet -dict {PACKAGE_PIN F5 } [get_ports tx_data_n[2] ] ; ## FMC0_DP2_C2M_N MGTHTXN3_229 FPGA_SERDOUT_1_N
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set_property -quiet -dict {PACKAGE_PIN F6 } [get_ports tx_data_p[2] ] ; ## FMC0_DP2_C2M_P MGTHTXP3_229 FPGA_SERDOUT_1_P
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set_property -quiet -dict {PACKAGE_PIN N3 } [get_ports tx_data_n[7] ] ; ## FMC0_DP7_C2M_N MGTHTXN2_228 FPGA_SERDOUT_2_N
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set_property -quiet -dict {PACKAGE_PIN N4 } [get_ports tx_data_p[7] ] ; ## FMC0_DP7_C2M_P MGTHTXP2_228 FPGA_SERDOUT_2_P
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set_property -quiet -dict {PACKAGE_PIN R3 } [get_ports tx_data_n[6] ] ; ## FMC0_DP6_C2M_N MGTHTXN0_228 FPGA_SERDOUT_3_N
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set_property -quiet -dict {PACKAGE_PIN R4 } [get_ports tx_data_p[6] ] ; ## FMC0_DP6_C2M_P MGTHTXP0_228 FPGA_SERDOUT_3_P
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set_property -quiet -dict {PACKAGE_PIN H5 } [get_ports tx_data_n[1] ] ; ## FMC0_DP1_C2M_N MGTHTXN1_229 FPGA_SERDOUT_4_N
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set_property -quiet -dict {PACKAGE_PIN H6 } [get_ports tx_data_p[1] ] ; ## FMC0_DP1_C2M_P MGTHTXP1_229 FPGA_SERDOUT_4_P
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set_property -quiet -dict {PACKAGE_PIN P5 } [get_ports tx_data_n[5] ] ; ## FMC0_DP5_C2M_N MGTHTXN1_228 FPGA_SERDOUT_5_N
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set_property -quiet -dict {PACKAGE_PIN P6 } [get_ports tx_data_p[5] ] ; ## FMC0_DP5_C2M_P MGTHTXP1_228 FPGA_SERDOUT_5_P
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set_property -quiet -dict {PACKAGE_PIN M5 } [get_ports tx_data_n[4] ] ; ## FMC0_DP4_C2M_N MGTHTXN3_228 FPGA_SERDOUT_6_N
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set_property -quiet -dict {PACKAGE_PIN M6 } [get_ports tx_data_p[4] ] ; ## FMC0_DP4_C2M_P MGTHTXP3_228 FPGA_SERDOUT_6_P
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set_property -quiet -dict {PACKAGE_PIN K5 } [get_ports tx_data_n[3] ] ; ## FMC0_DP3_C2M_N MGTHTXN0_229 FPGA_SERDOUT_7_N
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set_property -quiet -dict {PACKAGE_PIN K6 } [get_ports tx_data_p[3] ] ; ## FMC0_DP3_C2M_P MGTHTXP0_229 FPGA_SERDOUT_7_P
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set_property -quiet -dict {PACKAGE_PIN V1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_syncin_n[0] ] ; ## FMC0_LA02_N IO_L23N_T3U_N9_66
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set_property -quiet -dict {PACKAGE_PIN V2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_syncin_p[0] ] ; ## FMC0_LA02_P IO_L23P_T3U_N8_66
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set_property -quiet -dict {PACKAGE_PIN Y1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_syncin_n[1] ] ; ## FMC0_LA03_N IO_L22N_T3U_N7_DBC_AD0N_66
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set_property -quiet -dict {PACKAGE_PIN Y2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports fpga_syncin_p[1] ] ; ## FMC0_LA03_P IO_L22P_T3U_N6_DBC_AD0P_66
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set_property -quiet -dict {PACKAGE_PIN AC4 IOSTANDARD LVDS } [get_ports fpga_syncout_n[0]] ; ## FMC0_LA01_CC_N IO_L16N_T2U_N7_QBC_AD3N_66
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set_property -quiet -dict {PACKAGE_PIN AB4 IOSTANDARD LVDS } [get_ports fpga_syncout_p[0]] ; ## FMC0_LA01_CC_P IO_L16P_T2U_N6_QBC_AD3P_66
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set_property -quiet -dict {PACKAGE_PIN AC1 IOSTANDARD LVDS } [get_ports fpga_syncout_n[1]] ; ## FMC0_LA06_N IO_L19N_T3L_N1_DBC_AD9N_66
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set_property -quiet -dict {PACKAGE_PIN AC2 IOSTANDARD LVDS } [get_ports fpga_syncout_p[1]] ; ## FMC0_LA06_P IO_L19P_T3L_N0_DBC_AD9P_66
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set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS18 } [get_ports gpio[0] ] ; ## FMC0_LA15_P IO_L6P_T0U_N10_AD6P_66
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set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS18 } [get_ports gpio[1] ] ; ## FMC0_LA15_N IO_L6N_T0U_N11_AD6N_66
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set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18 } [get_ports gpio[2] ] ; ## FMC0_LA19_P IO_L23P_T3U_N8_67
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set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18 } [get_ports gpio[3] ] ; ## FMC0_LA19_N IO_L23N_T3U_N9_67
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set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVCMOS18 } [get_ports gpio[4] ] ; ## FMC0_LA13_P IO_L8P_T1L_N2_AD5P_66
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set_property -dict {PACKAGE_PIN AC8 IOSTANDARD LVCMOS18 } [get_ports gpio[5] ] ; ## FMC0_LA13_N IO_L8N_T1L_N3_AD5N_66
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set_property -dict {PACKAGE_PIN AC7 IOSTANDARD LVCMOS18 } [get_ports gpio[6] ] ; ## FMC0_LA14_P IO_L7P_T1L_N0_QBC_AD13P_66
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set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVCMOS18 } [get_ports gpio[7] ] ; ## FMC0_LA14_N IO_L7N_T1L_N1_QBC_AD13N_66
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set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS18 } [get_ports gpio[8] ] ; ## FMC0_LA16_P IO_L5P_T0U_N8_AD14P_66
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set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS18 } [get_ports gpio[9] ] ; ## FMC0_LA16_N IO_L5N_T0U_N9_AD14N_66
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set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS18 } [get_ports gpio[10] ] ; ## FMC0_LA22_N IO_L20N_T3L_N3_AD1N_67
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set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS18 } [get_ports hmc_gpio1 ] ; ## FMC0_LA11_N IO_L10N_T1U_N7_QBC_AD4N_66
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set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS18 } [get_ports hmc_sync ] ; ## FMC0_LA07_N IO_L18N_T2U_N11_AD2N_66
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set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS18 } [get_ports irqb[0] ] ; ## FMC0_LA08_P IO_L17P_T2U_N8_AD10P_66
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set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVCMOS18 } [get_ports irqb[1] ] ; ## FMC0_LA08_N IO_L17N_T2U_N9_AD10N_66
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set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS18 } [get_ports rstb ] ; ## FMC0_LA07_P IO_L18P_T2U_N10_AD2P_66
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set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS18 } [get_ports rxen[0] ] ; ## FMC0_LA10_P IO_L15P_T2L_N4_AD11P_66
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set_property -dict {PACKAGE_PIN W4 IOSTANDARD LVCMOS18 } [get_ports rxen[1] ] ; ## FMC0_LA10_N IO_L15N_T2L_N5_AD11N_66
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set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS18 } [get_ports spi0_csb ] ; ## FMC0_LA05_P IO_L20P_T3L_N2_AD1P_66
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set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVCMOS18 } [get_ports spi0_miso ] ; ## FMC0_LA05_N IO_L20N_T3L_N3_AD1N_66
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||||||
|
set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVCMOS18 } [get_ports spi0_mosi ] ; ## FMC0_LA04_P IO_L21P_T3L_N4_AD8P_66
|
||||||
|
set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVCMOS18 } [get_ports spi0_sclk ] ; ## FMC0_LA04_N IO_L21N_T3L_N5_AD8N_66
|
||||||
|
set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS18 } [get_ports spi1_csb ] ; ## FMC0_LA12_P IO_L9P_T1L_N4_AD12P_66
|
||||||
|
set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS18 } [get_ports spi1_sclk ] ; ## FMC0_LA11_P IO_L10P_T1U_N6_QBC_AD4P_66
|
||||||
|
set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS18 } [get_ports spi1_sdio ] ; ## FMC0_LA12_N IO_L9N_T1L_N5_AD12N_66
|
||||||
|
set_property -dict {PACKAGE_PIN AA6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref2_n ] ; ## FMC0_CLK0_M2C_N IO_L12N_T1U_N11_GC_66
|
||||||
|
set_property -dict {PACKAGE_PIN AA7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref2_p ] ; ## FMC0_CLK0_M2C_P IO_L12P_T1U_N10_GC_66
|
||||||
|
set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVCMOS18 } [get_ports txen[0] ] ; ## FMC0_LA09_P IO_L24P_T3U_N10_66
|
||||||
|
set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS18 } [get_ports txen[1] ] ; ## FMC0_LA09_N IO_L24N_T3U_N11_66
|
||||||
|
|
||||||
|
|
@ -0,0 +1,30 @@
|
||||||
|
|
||||||
|
source ../../scripts/adi_env.tcl
|
||||||
|
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
|
||||||
|
source $ad_hdl_dir/projects/scripts/adi_board.tcl
|
||||||
|
|
||||||
|
adi_project ad9081_fmca_ebz_zcu102 0 [list \
|
||||||
|
JESD_MODE 8B10B \
|
||||||
|
RX_JESD_M 8 \
|
||||||
|
RX_JESD_L 4 \
|
||||||
|
RX_JESD_S 1 \
|
||||||
|
RX_JESD_NP 16 \
|
||||||
|
RX_NUM_LINKS 1 \
|
||||||
|
TX_JESD_M 8 \
|
||||||
|
TX_JESD_L 4 \
|
||||||
|
TX_JESD_S 1 \
|
||||||
|
TX_JESD_NP 16 \
|
||||||
|
TX_NUM_LINKS 1 \
|
||||||
|
]
|
||||||
|
|
||||||
|
adi_project_files ad9081_fmca_ebz_zcu102 [list \
|
||||||
|
"system_top.v" \
|
||||||
|
"system_constr.xdc"\
|
||||||
|
"timing_constr.xdc"\
|
||||||
|
"../../../library/common/ad_3w_spi.v"\
|
||||||
|
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
|
||||||
|
"$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
|
||||||
|
|
||||||
|
|
||||||
|
adi_project_run ad9081_fmca_ebz_zcu102
|
||||||
|
|
||||||
|
|
@ -0,0 +1,283 @@
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
// developed independently, and may be accompanied by separate and unique license
|
||||||
|
// terms.
|
||||||
|
//
|
||||||
|
// The user should read each of these license terms, and understand the
|
||||||
|
// freedoms and responsibilities that he or she has by using this source/core.
|
||||||
|
//
|
||||||
|
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||||
|
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||||
|
// A PARTICULAR PURPOSE.
|
||||||
|
//
|
||||||
|
// Redistribution and use of source or resulting binaries, with or without modification
|
||||||
|
// of this file, are permitted under one of the following two license terms:
|
||||||
|
//
|
||||||
|
// 1. The GNU General Public License version 2 as published by the
|
||||||
|
// Free Software Foundation, which can be found in the top level directory
|
||||||
|
// of this repository (LICENSE_GPL2), and also online at:
|
||||||
|
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||||
|
//
|
||||||
|
// OR
|
||||||
|
//
|
||||||
|
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||||
|
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||||
|
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||||
|
// This will allow to generate bit files and not release the source code,
|
||||||
|
// as long as it attaches to an ADI device.
|
||||||
|
//
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
|
|
||||||
|
module system_top #(
|
||||||
|
parameter TX_JESD_L = 8,
|
||||||
|
parameter TX_NUM_LINKS = 1,
|
||||||
|
parameter RX_JESD_L = 8,
|
||||||
|
parameter RX_NUM_LINKS = 1
|
||||||
|
) (
|
||||||
|
|
||||||
|
input [12:0] gpio_bd_i,
|
||||||
|
output [ 7:0] gpio_bd_o,
|
||||||
|
|
||||||
|
|
||||||
|
// FMC HPC IOs
|
||||||
|
input [1:0] agc0,
|
||||||
|
input [1:0] agc1,
|
||||||
|
input [1:0] agc2,
|
||||||
|
input [1:0] agc3,
|
||||||
|
input clkin6_n,
|
||||||
|
input clkin6_p,
|
||||||
|
input clkin10_n,
|
||||||
|
input clkin10_p,
|
||||||
|
input fpga_refclk_in_n,
|
||||||
|
input fpga_refclk_in_p,
|
||||||
|
input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_n,
|
||||||
|
input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_p,
|
||||||
|
output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_n,
|
||||||
|
output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_p,
|
||||||
|
input [TX_NUM_LINKS-1:0] fpga_syncin_n,
|
||||||
|
input [TX_NUM_LINKS-1:0] fpga_syncin_p,
|
||||||
|
output [RX_NUM_LINKS-1:0] fpga_syncout_n,
|
||||||
|
output [RX_NUM_LINKS-1:0] fpga_syncout_p,
|
||||||
|
inout [10:0] gpio,
|
||||||
|
inout hmc_gpio1,
|
||||||
|
output hmc_sync,
|
||||||
|
input [1:0] irqb,
|
||||||
|
output rstb,
|
||||||
|
output [1:0] rxen,
|
||||||
|
output spi0_csb,
|
||||||
|
input spi0_miso,
|
||||||
|
output spi0_mosi,
|
||||||
|
output spi0_sclk,
|
||||||
|
output spi1_csb,
|
||||||
|
output spi1_sclk,
|
||||||
|
inout spi1_sdio,
|
||||||
|
input sysref2_n,
|
||||||
|
input sysref2_p,
|
||||||
|
output [1:0] txen
|
||||||
|
|
||||||
|
);
|
||||||
|
|
||||||
|
// internal signals
|
||||||
|
|
||||||
|
wire [94:0] gpio_i;
|
||||||
|
wire [94:0] gpio_o;
|
||||||
|
wire [94:0] gpio_t;
|
||||||
|
wire [ 2:0] spi0_csn;
|
||||||
|
|
||||||
|
wire [ 2:0] spi1_csn;
|
||||||
|
wire spi1_mosi;
|
||||||
|
wire spi1_miso;
|
||||||
|
|
||||||
|
wire ref_clk;
|
||||||
|
wire sysref;
|
||||||
|
wire [TX_NUM_LINKS-1:0] tx_syncin;
|
||||||
|
wire [RX_NUM_LINKS-1:0] rx_syncout;
|
||||||
|
|
||||||
|
wire [7:0] rx_data_p_loc;
|
||||||
|
wire [7:0] rx_data_n_loc;
|
||||||
|
wire [7:0] tx_data_p_loc;
|
||||||
|
wire [7:0] tx_data_n_loc;
|
||||||
|
|
||||||
|
wire clkin6;
|
||||||
|
wire clkin10;
|
||||||
|
wire tx_device_clk;
|
||||||
|
wire rx_device_clk;
|
||||||
|
|
||||||
|
assign iic_rstn = 1'b1;
|
||||||
|
|
||||||
|
// instantiations
|
||||||
|
|
||||||
|
IBUFDS_GTE4 i_ibufds_ref_clk (
|
||||||
|
.CEB (1'd0),
|
||||||
|
.I (fpga_refclk_in_p),
|
||||||
|
.IB (fpga_refclk_in_n),
|
||||||
|
.O (ref_clk),
|
||||||
|
.ODIV2 ());
|
||||||
|
|
||||||
|
IBUFDS i_ibufds_sysref (
|
||||||
|
.I (sysref2_p),
|
||||||
|
.IB (sysref2_n),
|
||||||
|
.O (sysref));
|
||||||
|
|
||||||
|
IBUFDS i_ibufds_tx_device_clk (
|
||||||
|
.I (clkin6_p),
|
||||||
|
.IB (clkin6_n),
|
||||||
|
.O (clkin6));
|
||||||
|
|
||||||
|
IBUFDS i_ibufds_rx_device_clk (
|
||||||
|
.I (clkin10_p),
|
||||||
|
.IB (clkin10_n),
|
||||||
|
.O (clkin10));
|
||||||
|
|
||||||
|
genvar i;
|
||||||
|
generate
|
||||||
|
for(i=0;i<TX_NUM_LINKS;i=i+1) begin : g_tx_buffers
|
||||||
|
IBUFDS i_ibufds_syncin (
|
||||||
|
.I (fpga_syncin_p[i]),
|
||||||
|
.IB (fpga_syncin_n[i]),
|
||||||
|
.O (tx_syncin[i]));
|
||||||
|
end
|
||||||
|
|
||||||
|
for(i=0;i<RX_NUM_LINKS;i=i+1) begin : g_rx_buffers
|
||||||
|
OBUFDS i_obufds_syncout (
|
||||||
|
.I (rx_syncout[i]),
|
||||||
|
.O (fpga_syncout_p[i]),
|
||||||
|
.OB (fpga_syncout_n[i]));
|
||||||
|
end
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
BUFG i_tx_device_clk (
|
||||||
|
.I (clkin6),
|
||||||
|
.O (tx_device_clk)
|
||||||
|
);
|
||||||
|
|
||||||
|
BUFG i_rx_device_clk (
|
||||||
|
.I (clkin10),
|
||||||
|
.O (rx_device_clk)
|
||||||
|
);
|
||||||
|
// spi
|
||||||
|
|
||||||
|
assign spi0_csb = spi0_csn[0];
|
||||||
|
assign spi1_csb = spi1_csn[0];
|
||||||
|
|
||||||
|
|
||||||
|
ad_3w_spi #(.NUM_OF_SLAVES(1)) i_spi (
|
||||||
|
.spi_csn (spi1_csn[0]),
|
||||||
|
.spi_clk (spi1_sclk),
|
||||||
|
.spi_mosi (spi1_mosi),
|
||||||
|
.spi_miso (spi1_miso),
|
||||||
|
.spi_sdio (spi1_sdio),
|
||||||
|
.spi_dir ());
|
||||||
|
|
||||||
|
// gpios
|
||||||
|
|
||||||
|
ad_iobuf #(.DATA_WIDTH(12)) i_iobuf (
|
||||||
|
.dio_t (gpio_t[43:32]),
|
||||||
|
.dio_i (gpio_o[43:32]),
|
||||||
|
.dio_o (gpio_i[43:32]),
|
||||||
|
.dio_p ({hmc_gpio1, // 43
|
||||||
|
gpio[10:0]})); // 42-32
|
||||||
|
|
||||||
|
assign gpio_i[44] = agc0[0];
|
||||||
|
assign gpio_i[45] = agc0[1];
|
||||||
|
assign gpio_i[46] = agc1[0];
|
||||||
|
assign gpio_i[47] = agc1[1];
|
||||||
|
assign gpio_i[48] = agc2[0];
|
||||||
|
assign gpio_i[49] = agc2[1];
|
||||||
|
assign gpio_i[50] = agc3[0];
|
||||||
|
assign gpio_i[51] = agc3[1];
|
||||||
|
assign gpio_i[52] = irqb[0];
|
||||||
|
assign gpio_i[53] = irqb[1];
|
||||||
|
|
||||||
|
assign hmc_sync = gpio_o[54];
|
||||||
|
assign rstb = gpio_o[55];
|
||||||
|
assign rxen[0] = gpio_o[56];
|
||||||
|
assign rxen[1] = gpio_o[57];
|
||||||
|
assign txen[0] = gpio_o[58];
|
||||||
|
assign txen[1] = gpio_o[59];
|
||||||
|
assign dac_fifo_bypass = gpio_o[60];
|
||||||
|
|
||||||
|
/* Board GPIOS. Buttons, LEDs, etc... */
|
||||||
|
assign gpio_i[20: 8] = gpio_bd_i;
|
||||||
|
assign gpio_bd_o = gpio_o[7:0];
|
||||||
|
|
||||||
|
// Unused GPIOs
|
||||||
|
assign gpio_i[94:54] = gpio_o[94:54];
|
||||||
|
assign gpio_i[31:21] = gpio_o[31:21];
|
||||||
|
assign gpio_i[7:0] = gpio_o[7:0];
|
||||||
|
|
||||||
|
system_wrapper i_system_wrapper (
|
||||||
|
.gpio_i (gpio_i),
|
||||||
|
.gpio_o (gpio_o),
|
||||||
|
.gpio_t (gpio_t),
|
||||||
|
.spi0_csn (spi0_csn),
|
||||||
|
.spi0_miso (spi0_miso),
|
||||||
|
.spi0_mosi (spi0_mosi),
|
||||||
|
.spi0_sclk (spi0_sclk),
|
||||||
|
.spi1_csn (spi1_csn),
|
||||||
|
.spi1_miso (spi1_miso),
|
||||||
|
.spi1_mosi (spi1_mosi),
|
||||||
|
.spi1_sclk (spi1_sclk),
|
||||||
|
// FMC HPC
|
||||||
|
.rx_data_0_n (rx_data_n_loc[0]),
|
||||||
|
.rx_data_0_p (rx_data_p_loc[0]),
|
||||||
|
.rx_data_1_n (rx_data_n_loc[1]),
|
||||||
|
.rx_data_1_p (rx_data_p_loc[1]),
|
||||||
|
.rx_data_2_n (rx_data_n_loc[2]),
|
||||||
|
.rx_data_2_p (rx_data_p_loc[2]),
|
||||||
|
.rx_data_3_n (rx_data_n_loc[3]),
|
||||||
|
.rx_data_3_p (rx_data_p_loc[3]),
|
||||||
|
.rx_data_4_n (rx_data_n_loc[4]),
|
||||||
|
.rx_data_4_p (rx_data_p_loc[4]),
|
||||||
|
.rx_data_5_n (rx_data_n_loc[5]),
|
||||||
|
.rx_data_5_p (rx_data_p_loc[5]),
|
||||||
|
.rx_data_6_n (rx_data_n_loc[6]),
|
||||||
|
.rx_data_6_p (rx_data_p_loc[6]),
|
||||||
|
.rx_data_7_n (rx_data_n_loc[7]),
|
||||||
|
.rx_data_7_p (rx_data_p_loc[7]),
|
||||||
|
.tx_data_0_n (tx_data_n_loc[0]),
|
||||||
|
.tx_data_0_p (tx_data_p_loc[0]),
|
||||||
|
.tx_data_1_n (tx_data_n_loc[1]),
|
||||||
|
.tx_data_1_p (tx_data_p_loc[1]),
|
||||||
|
.tx_data_2_n (tx_data_n_loc[2]),
|
||||||
|
.tx_data_2_p (tx_data_p_loc[2]),
|
||||||
|
.tx_data_3_n (tx_data_n_loc[3]),
|
||||||
|
.tx_data_3_p (tx_data_p_loc[3]),
|
||||||
|
.tx_data_4_n (tx_data_n_loc[4]),
|
||||||
|
.tx_data_4_p (tx_data_p_loc[4]),
|
||||||
|
.tx_data_5_n (tx_data_n_loc[5]),
|
||||||
|
.tx_data_5_p (tx_data_p_loc[5]),
|
||||||
|
.tx_data_6_n (tx_data_n_loc[6]),
|
||||||
|
.tx_data_6_p (tx_data_p_loc[6]),
|
||||||
|
.tx_data_7_n (tx_data_n_loc[7]),
|
||||||
|
.tx_data_7_p (tx_data_p_loc[7]),
|
||||||
|
.ref_clk_q0 (ref_clk),
|
||||||
|
.ref_clk_q1 (ref_clk),
|
||||||
|
.rx_device_clk (rx_device_clk),
|
||||||
|
.tx_device_clk (tx_device_clk),
|
||||||
|
.rx_sync_0 (rx_syncout),
|
||||||
|
.tx_sync_0 (tx_syncin),
|
||||||
|
.rx_sysref_0 (sysref),
|
||||||
|
.tx_sysref_0 (sysref),
|
||||||
|
.dac_fifo_bypass (dac_fifo_bypass)
|
||||||
|
);
|
||||||
|
|
||||||
|
assign rx_data_p_loc[TX_JESD_L*TX_NUM_LINKS-1:0] = rx_data_p[TX_JESD_L*TX_NUM_LINKS-1:0];
|
||||||
|
assign rx_data_n_loc[TX_JESD_L*TX_NUM_LINKS-1:0] = rx_data_n[TX_JESD_L*TX_NUM_LINKS-1:0];
|
||||||
|
|
||||||
|
assign tx_data_p[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_p_loc[TX_JESD_L*TX_NUM_LINKS-1:0];
|
||||||
|
assign tx_data_n[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_n_loc[TX_JESD_L*TX_NUM_LINKS-1:0];
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
|
@ -0,0 +1,15 @@
|
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# Primary clock definitions
|
||||||
|
create_clock -name refclk -period 1.29 [get_ports fpga_refclk_in_p]
|
||||||
|
|
||||||
|
# device clock
|
||||||
|
create_clock -name tx_device_clk -period 2.58 [get_ports clkin6_p]
|
||||||
|
create_clock -name rx_device_clk -period 2.58 [get_ports clkin10_p]
|
||||||
|
|
||||||
|
|
||||||
|
# Constraint SYSREFs
|
||||||
|
# Assumption is that REFCLK and SYSREF have similar propagation delay,
|
||||||
|
# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK
|
||||||
|
set_input_delay -clock [get_clocks tx_device_clk] \
|
||||||
|
[get_property PERIOD [get_clocks tx_device_clk]] \
|
||||||
|
[get_ports {sysref2_*}]
|
||||||
|
|
||||||
Loading…
Reference in New Issue