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altera/common: Add SERDES related modules

main
Istvan Csomortani 2016-09-09 18:04:41 +03:00
parent a183e51a12
commit f4be0524b4
4 changed files with 640 additions and 0 deletions
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229
library/altera/alt_serdes/alt_serdes_hw.tcl Normal file
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package require -exact qsys 13.0
source ../../scripts/adi_env.tcl
source ../../scripts/adi_ip_alt.tcl
set_module_property NAME util_serdes_clk
set_module_property DESCRIPTION "A simple Altera IOPLL macro instance"
set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME util_serdes_clk
set_module_property ELABORATION_CALLBACK p_util_serdes_clk
add_fileset quartus_synth QUARTUS_SYNTH "" ""
set_fileset_property quartus_synth TOP_LEVEL ad_serdes_clk
add_fileset_file ad_serdes_clk.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_clk.v TOP_LEVEL_FILE
add_parameter DEVICE_FAMILY STRING
set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
set_parameter_property DEVICE_FAMILY ENABLED false
add_parameter MODE STRING 0
set_parameter_property MODE DEFAULT_VALUE "TX"
set_parameter_property MODE DISPLAY_NAME MODE
set_parameter_property MODE TYPE STRING
set_parameter_property MODE UNITS None
set_parameter_property MODE HDL_PARAMETER true
add_hdl_instance alt_clk altera_iopll
set_instance_parameter_value alt_clk {gui_reference_clock_frequency} {500.0}
set_instance_parameter_value alt_clk {gui_use_locked} {1}
set_instance_parameter_value alt_clk {gui_operation_mode} {lvds}
set_instance_parameter_value alt_clk {gui_en_lvds_ports} {true}
set_instance_parameter_value alt_clk {gui_number_of_clocks} {4}
set_instance_parameter_value alt_clk {gui_output_clock_frequency0} {1200.0}
set_instance_parameter_value alt_clk {gui_ps_units0} {degrees}
set_instance_parameter_value alt_clk {gui_phase_shift_deg0} {180.0}
set_instance_parameter_value alt_clk {gui_duty_cycle0} {50.0}
set_instance_parameter_value alt_clk {gui_output_clock_frequency1} {150.0}
set_instance_parameter_value alt_clk {gui_ps_units1} {degrees}
set_instance_parameter_value alt_clk {gui_phase_shift_deg1} {315.0}
set_instance_parameter_value alt_clk {gui_duty_cycle1} {12.5}
set_instance_parameter_value alt_clk {gui_output_clock_frequency2} {150.0}
set_instance_parameter_value alt_clk {gui_ps_units2} {degrees}
set_instance_parameter_value alt_clk {gui_phase_shift_deg2} {22.5}
set_instance_parameter_value alt_clk {gui_duty_cycle2} {50.0}
set_instance_parameter_value alt_clk {gui_output_clock_frequency3} {600.0}
set_instance_parameter_value alt_clk {gui_ps_units3} {degrees}
set_instance_parameter_value alt_clk {gui_phase_shift_deg3} {90}
set_instance_parameter_value alt_clk {gui_duty_cycle3} {50.0}
set_instance_parameter_value alt_clk {system_info_device_family} DEVICE_FAMILY
set_instance_parameter_value alt_clk {gui_en_reconf} {true}
# input clock and reset
ad_alt_intf clock clk Output 1
ad_alt_intf clock div_clk Output 1
ad_alt_intf clock loaden Output 1
add_interface serdes_clk clock end
add_interface_port serdes_clk clk_in_p clk Input 1
add_interface serdes_rst reset end
set_interface_property serdes_rst associatedClock serdes_clk
add_interface_port serdes_rst mmcm_rst reset Input 1
# updates
proc p_util_serdes_clk {} {
set serdes_clk_mode [get_parameter_value MODE]
if {$serdes_clk_mode eq "TX"} {
set_instance_parameter_value alt_clk {gui_en_phout_ports} {false}
} elseif {$serdes_clk_mode eq "RX"} {
set_instance_parameter_value alt_clk {gui_en_phout_ports} {true}
ad_alt_intf signal phase Output 8
} else {
set_instance_parameter_value alt_clk {gui_en_phout_ports} {false}
}
}
package require -exact qsys 13.0
source ../../scripts/adi_env.tcl
source ../../scripts/adi_ip_alt.tcl
set_module_property NAME util_serdes_in
set_module_property DESCRIPTION "A simple Altera LVDS Serdes macro instance in rx mode"
set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME util_serdes_in
add_fileset quartus_synth QUARTUS_SYNTH "" ""
set_fileset_property quartus_synth TOP_LEVEL ad_serdes_in
add_fileset_file ad_serdes_in.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_in.v TOP_LEVEL_FILE
add_parameter DEVICE_FAMILY STRING
set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
set_parameter_property DEVICE_FAMILY ENABLED false
add_parameter DATA_WIDTH STRING
set_parameter_property DATA_WIDTH DEFAULT_VALUE 16
set_parameter_property DATA_WIDTH DISPLAY_NAME DATA_WIDTH
set_parameter_property DATA_WIDTH TYPE INTEGER
set_parameter_property DATA_WIDTH UNITS None
set_parameter_property DATA_WIDTH HDL_PARAMETER true
add_hdl_instance alt_serdes_in altera_lvds
set_instance_parameter_value alt_serdes_in {DATA_RATE} {600.0}
set_instance_parameter_value alt_serdes_in {MODE} {dpa_mode_fifo}
set_instance_parameter_value alt_serdes_in {NUM_CHANNELS} {1}
set_instance_parameter_value alt_serdes_in {J_FACTOR} {8}
set_instance_parameter_value alt_serdes_in {INCLOCK_FREQUENCY} {100}
set_instance_parameter_value alt_serdes_in {PLL_USE_RESET} {false}
set_instance_parameter_value alt_serdes_in {TX_EXPORT_CORECLOCK} {false}
set_instance_parameter_value alt_serdes_in {TX_USE_OUTCLOCK} {false}
set_instance_parameter_value alt_serdes_in {USE_EXTERNAL_PLL} {true}
set_instance_parameter_value alt_serdes_in {SYS_INFO_DEVICE_FAMILY} DEVICE_FAMILY
# input clock and reset
add_interface fast_clk clock end
add_interface_port fast_clk clk clk Input 1
set_interface_property fast_clk associatedReset serdes_rst
add_interface serdes_rst reset end
add_interface_port serdes_rst rst reset Input 1
set_interface_property serdes_rst associatedClock fast_clk
add_interface div_clk clock end
add_interface_port div_clk div_clk clk Input 1
set_interface_property div_clk associatedReset none
add_interface loaden clock end
add_interface_port loaden loaden clk Input 1
set_interface_property loaden associatedReset none
add_interface parallel_data conduit end
add_interface_port parallel_data data_s0 data0 output DATA_WIDTH
add_interface_port parallel_data data_s1 data1 output DATA_WIDTH
add_interface_port parallel_data data_s2 data2 output DATA_WIDTH
add_interface_port parallel_data data_s3 data3 output DATA_WIDTH
add_interface_port parallel_data data_s4 data4 output DATA_WIDTH
add_interface_port parallel_data data_s5 data5 output DATA_WIDTH
add_interface_port parallel_data data_s6 data6 output DATA_WIDTH
add_interface_port parallel_data data_s7 data7 output DATA_WIDTH
set_interface_property parallel_data associatedClock div_clk
set_interface_property parallel_data associatedReset none
add_interface serial_data conduit end
add_interface_port serial_data data_out_p data_p output 1
add_interface_port serial_data data_out_n data_n output 1
package require -exact qsys 13.0
source ../../scripts/adi_env.tcl
source ../../scripts/adi_ip_alt.tcl
set_module_property NAME util_serdes_out
set_module_property DESCRIPTION "A simple Altera LVDS Serdes macro instance in tx mode"
set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME util_serdes_out
add_fileset quartus_synth QUARTUS_SYNTH "" ""
set_fileset_property quartus_synth TOP_LEVEL ad_serdes_out
add_fileset_file ad_serdes_out.v VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_out.v TOP_LEVEL_FILE
add_parameter DEVICE_FAMILY STRING
set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true
set_parameter_property DEVICE_FAMILY HDL_PARAMETER false
set_parameter_property DEVICE_FAMILY ENABLED false
add_parameter DATA_WIDTH STRING
set_parameter_property DATA_WIDTH DEFAULT_VALUE 16
set_parameter_property DATA_WIDTH DISPLAY_NAME DATA_WIDTH
set_parameter_property DATA_WIDTH TYPE INTEGER
set_parameter_property DATA_WIDTH UNITS None
set_parameter_property DATA_WIDTH HDL_PARAMETER true
add_parameter DEVICE_TYPE STRING
set_parameter_property DEVICE_TYPE DEFAULT_VALUE 0
set_parameter_property DEVICE_TYPE DISPLAY_NAME DEVICE_TYPE
set_parameter_property DEVICE_TYPE TYPE INTEGER
set_parameter_property DEVICE_TYPE UNITS None
set_parameter_property DEVICE_TYPE HDL_PARAMETER true
add_hdl_instance alt_serdes_out altera_lvds
set_instance_parameter_value alt_serdes_out {DATA_RATE} {600.0}
set_instance_parameter_value alt_serdes_out {MODE} {TX}
set_instance_parameter_value alt_serdes_out {NUM_CHANNELS} {1}
set_instance_parameter_value alt_serdes_out {J_FACTOR} {8}
set_instance_parameter_value alt_serdes_out {INCLOCK_FREQUENCY} {100}
set_instance_parameter_value alt_serdes_out {PLL_USE_RESET} {false}
set_instance_parameter_value alt_serdes_out {TX_EXPORT_CORECLOCK} {false}
set_instance_parameter_value alt_serdes_out {TX_USE_OUTCLOCK} {false}
set_instance_parameter_value alt_serdes_out {USE_EXTERNAL_PLL} {true}
set_instance_parameter_value alt_serdes_out {SYS_INFO_DEVICE_FAMILY} DEVICE_FAMILY
# input clock and reset
ad_alt_intf clock clk Input 1
ad_alt_intf clock div_clk Input 1
ad_alt_intf clock loaden Input 1
ad_alt_intf reset rst Input 1
add_interface parallel_data conduit end
add_interface_port parallel_data data_s0 data0 input DATA_WIDTH
add_interface_port parallel_data data_s1 data1 input DATA_WIDTH
add_interface_port parallel_data data_s2 data2 input DATA_WIDTH
add_interface_port parallel_data data_s3 data3 input DATA_WIDTH
add_interface_port parallel_data data_s4 data4 input DATA_WIDTH
add_interface_port parallel_data data_s5 data5 input DATA_WIDTH
add_interface_port parallel_data data_s6 data6 input DATA_WIDTH
add_interface_port parallel_data data_s7 data7 input DATA_WIDTH
set_interface_property parallel_data associatedClock div_clk
set_interface_property parallel_data associatedReset none
add_interface serial_data conduit end
add_interface_port serial_data data_out_p data_p output 1
add_interface_port serial_data data_out_n data_n output 1

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library/altera/common/ad_serdes_clk.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// serial data output interface: serdes(x8)
`timescale 1ps/1ps
module ad_serdes_clk (
// clock and divided clock
mmcm_rst,
clk_in_p,
clk_in_n,
clk,
div_clk,
out_clk,
loaden,
phase,
// drp interface
up_clk,
up_rstn,
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked);
// parameters
parameter MODE = "TX";
// clock and divided clock
input mmcm_rst;
input clk_in_p;
input clk_in_n;
output clk;
output div_clk;
output out_clk;
output loaden;
output [ 7:0] phase;
// drp interface
input up_clk;
input up_rstn;
input up_drp_sel;
input up_drp_wr;
input [11:0] up_drp_addr;
input [15:0] up_drp_wdata;
output [15:0] up_drp_rdata;
output up_drp_ready;
output up_drp_locked;
wire locked;
// ground the unused outputs
assign up_drp_rdata = 15'b0;
assign up_drp_ready = 1'b0;
assign up_drp_locked = locked;
generate if (MODE == "TX") begin
assign phase = 8'h0;
alt_clk i_alt_clk (
.locked (locked), // locked.export
.outclk_0 (clk), // outclk0.clk
.outclk_1 (loaden), // outclk1.clk
.outclk_2 (div_clk), // outclk2.clk
.outclk_3 (out_clk), // outclk3.clk
.reconfig_from_pll (), // reconfig_from_pll.reconfig_from_pll
.reconfig_to_pll (), // reconfig_to_pll.reconfig_to_pll
.refclk (clk_in_p), // refclk.clk
.rst (mmcm_rst) // reset.reset
);
// TODO: Add Altera PLL Reconfig IP
end else begin
alt_clk i_alt_clk (
.locked (locked), // locked.export
.outclk_0 (clk), // outclk0.clk
.outclk_1 (loaden), // outclk1.clk
.outclk_2 (div_clk), // outclk2.clk
.outclk_3 (out_clk), // outclk3.clk
.reconfig_from_pll (), // reconfig_from_pll.reconfig_from_pll
.reconfig_to_pll (), // reconfig_to_pll.reconfig_to_pll
.phout (phase),
.refclk (clk_in_p), // refclk.clk
.rst (mmcm_rst) // reset.reset
);
end
endgenerate
endmodule

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library/altera/common/ad_serdes_in.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ps/1ps
module ad_serdes_in (
// reset and clocks
rst,
clk,
div_clk,
loaden,
clk_phase,
// data interface
data_s0,
data_s1,
data_s2,
data_s3,
data_s4,
data_s5,
data_s6,
data_s7,
data_in_p,
data_in_n,
// delay-data interface
up_clk,
up_dld,
up_dwdata,
up_drdata,
// delay-control interface
delay_clk,
delay_rst,
delay_locked);
// parameters
parameter DEVICE_TYPE = 0;
// reset and clocks
input rst;
input clk;
input div_clk;
input loaden;
input clk_phase;
// data interface
output data_s0;
output data_s1;
output data_s2;
output data_s3;
output data_s4;
output data_s5;
output data_s6;
output data_s7;
input data_in_p;
input data_in_n;
// delay-data interface
input up_clk;
input up_dld;
input [ 4:0] up_dwdata;
output [ 4:0] up_drdata;
// delay-control interface
input delay_clk;
input delay_rst;
output delay_locked;
// internal signals
wire [ 7:0] data_out_s;
assign data_s0 = data_out_s[0];
assign data_s1 = data_out_s[1];
assign data_s2 = data_out_s[2];
assign data_s2 = data_out_s[2];
assign data_s3 = data_out_s[3];
assign data_s4 = data_out_s[4];
assign data_s5 = data_out_s[5];
assign data_s6 = data_out_s[6];
assign data_s7 = data_out_s[7];
altera_lvds_in i_altera_lvds_in (
.ext_coreclock (div_clk), // ext_coreclock.export
.ext_fclk (clk), // ext_fclk.export
.ext_loaden (loaden), // ext_loaden.export
.ext_pll_locked (), // ext_pll_locked.export
.ext_vcoph (clk_phase), // ext_vcoph.export
.rx_dpa_locked (delay_locked), // rx_dpa_locked.export
.rx_in (data_in_p), // rx_in.export
.rx_out (data_out_s) // rx_out.export
);
endmodule

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library/altera/common/ad_serdes_out.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// serial data output interface: serdes(x8)
`timescale 1ps/1ps
module ad_serdes_out (
// reset and clocks
rst,
clk,
div_clk,
loaden,
// data interface
data_s0,
data_s1,
data_s2,
data_s3,
data_s4,
data_s5,
data_s6,
data_s7,
data_out_p,
data_out_n);
// parameters
parameter DEVICE_TYPE = 0;
parameter DATA_WIDTH = 16;
localparam DW = DATA_WIDTH - 1;
// reset and clocks
input rst;
input clk;
input div_clk;
input loaden;
// data interface
input [DW:0] data_s0;
input [DW:0] data_s1;
input [DW:0] data_s2;
input [DW:0] data_s3;
input [DW:0] data_s4;
input [DW:0] data_s5;
input [DW:0] data_s6;
input [DW:0] data_s7;
output [DW:0] data_out_p;
output [DW:0] data_out_n;
// internal signals
wire [DW:0] data_out_s;
wire [ 7:0] data_in_s[DW:0];
// instantiations
assign data_out_p = data_out_s;
assign data_out_n = 0; // differential pair will be defined by the Pin Planner
genvar l_inst;
generate
for (l_inst = 0; l_inst <= DW; l_inst = l_inst + 1) begin: g_data
assign data_in_s[l_inst] = {data_s7[l_inst],
data_s6[l_inst],
data_s5[l_inst],
data_s4[l_inst],
data_s3[l_inst],
data_s2[l_inst],
data_s1[l_inst],
data_s0[l_inst]};
alt_serdes_out i_alt_serdes_out (
.ext_coreclock (div_clk), // ext_coreclock.export
.ext_fclk (clk), // ext_fclk.export
.ext_loaden (loaden), // ext_loaden.export
.tx_in (data_in_s[l_inst]), // tx_in.export
.tx_out (data_out_s[l_inst]) // tx_out.export
);
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************