spi_engine_execution: Add an additional register stage for the physical SPI
The main reason is to improve timing when the SPI clock is more than 50 MHz. (the SPI Engine's spi_clk is more than 100MHz)main
parent
cf9d0814d5
commit
f4de1fecdc
|
@ -68,7 +68,7 @@ module spi_engine_execution #(
|
||||||
output [7:0] sync,
|
output [7:0] sync,
|
||||||
|
|
||||||
output reg sclk,
|
output reg sclk,
|
||||||
output sdo,
|
output reg sdo,
|
||||||
output reg sdo_t,
|
output reg sdo_t,
|
||||||
input sdi,
|
input sdi,
|
||||||
input sdi_1,
|
input sdi_1,
|
||||||
|
@ -97,6 +97,10 @@ localparam REG_WORD_LENGTH = 2'b10;
|
||||||
localparam BIT_COUNTER_WIDTH = DATA_WIDTH > 16 ? 5 :
|
localparam BIT_COUNTER_WIDTH = DATA_WIDTH > 16 ? 5 :
|
||||||
DATA_WIDTH > 8 ? 4 : 3;
|
DATA_WIDTH > 8 ? 4 : 3;
|
||||||
|
|
||||||
|
reg sclk_int = 1'b0;
|
||||||
|
wire sdo_int_s;
|
||||||
|
reg sdo_t_int = 1'b0;
|
||||||
|
|
||||||
reg idle;
|
reg idle;
|
||||||
|
|
||||||
reg [7:0] clk_div_counter = 'h00;
|
reg [7:0] clk_div_counter = 'h00;
|
||||||
|
@ -352,9 +356,9 @@ end
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
if (transfer_active == 1'b1 || wait_for_io == 1'b1)
|
if (transfer_active == 1'b1 || wait_for_io == 1'b1)
|
||||||
begin
|
begin
|
||||||
sdo_t <= ~sdo_enabled;
|
sdo_t_int <= ~sdo_enabled;
|
||||||
end else begin
|
end else begin
|
||||||
sdo_t <= 1'b1;
|
sdo_t_int <= 1'b1;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
@ -371,7 +375,7 @@ always @(posedge clk) begin
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
assign sdo = data_sdo_shift[DATA_WIDTH-1];
|
assign sdo_int_s = data_sdo_shift[DATA_WIDTH-1];
|
||||||
|
|
||||||
// In case of an interface with high clock rate (SCLK > 50MHz), one of the
|
// In case of an interface with high clock rate (SCLK > 50MHz), one of the
|
||||||
// next SCLK edge must be used to flop the SDI line, to compensate the overall
|
// next SCLK edge must be used to flop the SDI line, to compensate the overall
|
||||||
|
@ -448,10 +452,17 @@ end
|
||||||
|
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
if (transfer_active == 1'b1) begin
|
if (transfer_active == 1'b1) begin
|
||||||
sclk <= cpol ^ cpha ^ ntx_rx;
|
sclk_int <= cpol ^ cpha ^ ntx_rx;
|
||||||
end else begin
|
end else begin
|
||||||
sclk <= cpol;
|
sclk_int <= cpol;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
// Additional register stage to imrpove timing
|
||||||
|
always @(posedge clk) begin
|
||||||
|
sclk <= sclk_int;
|
||||||
|
sdo <= sdo_int_s;
|
||||||
|
sdo_t <= sdo_t_int;
|
||||||
|
end
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
Loading…
Reference in New Issue