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cn0506_rgmii: Add support for zc706

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AndreiGrozav 2019-09-13 17:27:10 +01:00 committed by AndreiGrozav
parent 98fba87d8f
commit f4f547715e
6 changed files with 379 additions and 0 deletions
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20
projects/cn0506_rgmii/zc706/Makefile Normal file
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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := cn0506_zc706
M_DEPS += ../common/cn0506_bd.tcl
M_DEPS += ../../common/zc706/zc706_system_constr.xdc
M_DEPS += ../../common/zc706/zc706_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_spdif_tx
LIB_DEPS += axi_sysid
LIB_DEPS += sysid_rom
include ../../scripts/project-xilinx.mk

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projects/cn0506_rgmii/zc706/README.rst Normal file
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- Connect to FMC LPC
- VADJ = 2.5V
- RGMII mode, using a GMII-to-RGMII converter. Connected to PS7's Ethernet 0(PHY 0) and Ethernet 1(PHY 0)

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projects/cn0506_rgmii/zc706/system_bd.tcl Normal file
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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source ../common/cn0506_bd.tcl
ad_ip_parameter clk_wiz CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 200
ad_ip_parameter clk_wiz CONFIG.MMCM_CLKIN2_PERIOD 10.0
ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_ENET0_IO EMIO
ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_GRP_MDIO_IO EMIO
ad_ip_parameter sys_ps7 CONFIG.PCW_ENET1_PERIPHERAL_ENABLE 1
ad_ip_parameter sys_ps7 CONFIG.PCW_ENET1_GRP_MDIO_ENABLE 1
ad_connect sys_ps7/GMII_ETHERNET_0 gmii_to_rgmii_0/GMII
ad_connect sys_ps7/MDIO_ETHERNET_0 gmii_to_rgmii_0/MDIO_GEM
ad_connect sys_ps7/GMII_ETHERNET_1 gmii_to_rgmii_1/GMII
ad_connect sys_ps7/MDIO_ETHERNET_1 gmii_to_rgmii_1/MDIO_GEM
# Remove the unused 200MHz reset generator added in the base design.
delete_bd_objs [get_bd_nets sys_ps7_FCLK_RESET1_N] \
[get_bd_nets sys_200m_reset] \
[get_bd_nets sys_200m_resetn] \
[get_bd_cells sys_200m_rstgen]

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projects/cn0506_rgmii/zc706/system_constr.xdc Normal file
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set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVDS_25} [get_ports ref_clk_125_p] ; ## H04 FMC_LPC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVDS_25} [get_ports ref_clk_125_n] ; ## H05 FMC_LPC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports rgmii_rxc_a] ; ## G06 FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS25} [get_ports rgmii_rx_ctl_a] ; ## H14 FMC_LPC_LA07_N
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS25} [get_ports {rgmii_rxd_a[0]}] ; ## H07 FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports {rgmii_rxd_a[1]}] ; ## H08 FMC_LPC_LA02_N
set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVCMOS25} [get_ports {rgmii_rxd_a[2]}] ; ## G09 FMC_LPC_LA03_P
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS25} [get_ports {rgmii_rxd_a[3]}] ; ## G10 FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN Ak15 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports rgmii_txc_a] ; ## H11 FMC_LPC_LA04_N
set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports rgmii_tx_ctl_a] ; ## H13 FMC_LPC_LA07_P
set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {rgmii_txd_a[0]}] ; ## D14 FMC_LPC_LA09_P
set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {rgmii_txd_a[1]}] ; ## D15 FMC_LPC_LA09_N
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {rgmii_txd_a[2]}] ; ## C10 FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {rgmii_txd_a[3]}] ; ## C11 FMC_LPC_LA06_N
set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVCMOS25 PULLUP true} [get_ports mdio_fmc_a] ; ## H16 FMC_LPC_LA11_P
set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVCMOS25} [get_ports mdc_fmc_a] ; ## H17 FMC_LPC_LA11_N
set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS25} [get_ports reset_a] ; ## H19 FMC_LPC_LA15_P
set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVCMOS25} [get_ports link_st_a] ; ## H10 FMC_LPC_LA04_P
set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS25} [get_ports int_n_a] ; ## G13 FMC_LPC_LA08_N
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS25} [get_ports led_0_a] ; ## G12 FMC_LPC_LA08_P
set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVCMOS25} [get_ports led_ar_c_c2m] ; ## G15 FMC_HPC1_LA12_P
set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVCMOS25} [get_ports led_ar_a_c2m] ; ## G16 FMC_HPC1_LA12_N
set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVCMOS25} [get_ports led_al_c_c2m] ; ## D17 FMC_LPC_LA13_P
set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVCMOS25} [get_ports led_al_a_c2m] ; ## D18 FMC_LPC_LA13_N
set_property -dict {PACKAGE_PIN AE27 IOSTANDARD LVCMOS25} [get_ports rgmii_rxc_b] ; ## C22 FMC_LPC_LA18_CC_P
set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVCMOS25} [get_ports rgmii_rx_ctl_b] ; ## H29 FMC_LPC_LA24_N
set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVCMOS25} [get_ports {rgmii_rxd_b[0]}] ; ## H22 FMC_LPC_LA19_P
set_property -dict {PACKAGE_PIN AH27 IOSTANDARD LVCMOS25} [get_ports {rgmii_rxd_b[1]}] ; ## H23 FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVCMOS25} [get_ports {rgmii_rxd_b[2]}] ; ## G21 FMC_LPC_LA20_P
set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVCMOS25} [get_ports {rgmii_rxd_b[3]}] ; ## G22 FMC_LPC_LA20_N
set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports rgmii_txc_b] ; ## G28 FMC_LPC_LA25_N
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports rgmii_tx_ctl_b] ; ## H28 FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {rgmii_txd_b[0]}] ; ## H25 FMC_LPC_LA21_P
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {rgmii_txd_b[1]}] ; ## H26 FMC_LPC_LA21_N
set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {rgmii_txd_b[2]}] ; ## G24 FMC_LPC_LA22_P
set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {rgmii_txd_b[3]}] ; ## G25 FMC_LPC_LA22_N
set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS25 PULLUP true} [get_ports mdio_fmc_b] ; ## H31 FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS25} [get_ports mdc_fmc_b] ; ## H32 FMC_LPC_LA28_N
set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVCMOS25} [get_ports reset_b] ; ## H20 FMC_LPC_LA15_N
set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVCMOS25} [get_ports link_st_b] ; ## G27 FMC_LPC_LA25_P
set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVCMOS25} [get_ports int_n_b] ; ## D24 FMC_LPC_LA23_N
set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVCMOS25} [get_ports led_0_b] ; ## D23 FMC_LPC_LA23_P
set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS25} [get_ports led_bl_c_c2m] ; ## D26 FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports led_bl_a_c2m] ; ## D27 FMC_LPC_LA26_N
set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports led_br_c_c2m] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports led_br_a_c2m] ; ## G19 FMC_LPC_LA16_N
create_clock -name rx_clk_1 -period 8.0 [get_ports rgmii_rxc_a]
create_clock -name rx_clk_2 -period 8.0 [get_ports rgmii_rxc_b]
create_clock -name ref_clk_125 -period 8.0 [get_ports ref_clk_125_p]

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projects/cn0506_rgmii/zc706/system_project.tcl Normal file
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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project cn0506_zc706
adi_project_files cn0506_zc706 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"]
adi_project_run cn0506_zc706

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projects/cn0506_rgmii/zc706/system_top.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [14:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [23:0] hdmi_data,
output spdif,
input sys_rst,
input sys_clk_p,
input sys_clk_n,
inout iic_scl,
inout iic_sda,
input ref_clk_125_p,
input ref_clk_125_n,
// RGMII interface
output reset_a,
output mdc_fmc_a,
inout mdio_fmc_a,
input [ 3:0] rgmii_rxd_a,
input rgmii_rx_ctl_a,
input rgmii_rxc_a,
output [ 3:0] rgmii_txd_a,
output rgmii_tx_ctl_a,
output rgmii_txc_a,
input link_st_a,
input int_n_a,
input led_0_a,
output reset_b,
output mdc_fmc_b,
inout mdio_fmc_b,
input [ 3:0] rgmii_rxd_b,
input rgmii_rx_ctl_b,
input rgmii_rxc_b,
output [ 3:0] rgmii_txd_b,
output rgmii_tx_ctl_b,
output rgmii_txc_b,
input link_st_b,
input int_n_b,
input led_0_b,
// LEDs
output led_ar_c_c2m,
output led_ar_a_c2m,
output led_al_c_c2m,
output led_al_a_c2m,
output led_br_c_c2m,
output led_br_a_c2m,
output led_bl_c_c2m,
output led_bl_a_c2m
);
// internal signals
wire reset;
wire [ 1:0] speed_mode_a_s;
wire [ 1:0] speed_mode_b_s;
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
assign reset_a = reset;
assign reset_b = reset;
// port a - right led (activity/status) yellow only
assign led_ar_c_c2m = led_0_a;
assign led_ar_a_c2m = 1'b0;
// port a - left led (speed mode): 10M=off, 100M=yellow, 1G=green
assign led_al_c_c2m = speed_mode_a_s[0];
assign led_al_a_c2m = speed_mode_a_s[1];
// port b - right led (activity/status) yellow only
assign led_br_c_c2m = led_0_b;
assign led_br_a_c2m = 1'b0;
// port b - left led (speed mode): 10M=off, 100M=yellow, 1G=green
assign led_bl_c_c2m = speed_mode_b_s[0];
assign led_bl_a_c2m = speed_mode_b_s[1];
assign gpio_i[63:36] = gpio_o[63:36];
assign gpio_i[35] = link_st_a;
assign gpio_i[34] = link_st_b;
assign gpio_i[33] = int_n_a;
assign gpio_i[32] = int_n_b;
assign gpio_i[31:15] = gpio_o[31:15];
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
.dio_t (gpio_t[14:0]),
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
.dio_p (gpio_bd));
IBUFDS i_ibufds_clk_125 (
.I (ref_clk_125_p),
.IB (ref_clk_125_n),
.O (ref_clk_125));
// instantiations
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.spdif (spdif),
.spi0_clk_i (1'b0),
.spi0_clk_o (),
.spi0_csn_0_o (),
.spi0_csn_1_o (),
.spi0_csn_2_o (),
.spi0_csn_i (1'b1),
.spi0_sdi_i (1'b0),
.spi0_sdo_i (1'b0),
.spi0_sdo_o (),
.spi1_clk_i (1'b0),
.spi1_clk_o (),
.spi1_csn_0_o (),
.spi1_csn_1_o (),
.spi1_csn_2_o (),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b0),
.spi1_sdo_i (1'b0),
.spi1_sdo_o(),
.reset (reset),
.clock_speed_0(),
.MDIO_PHY_0_mdc (mdc_fmc_a),
.MDIO_PHY_0_mdio_io (mdio_fmc_a),
.RGMII_0_rd (rgmii_rxd_a),
.RGMII_0_rx_ctl (rgmii_rx_ctl_a),
.RGMII_0_rxc (rgmii_rxc_a),
.RGMII_0_td (rgmii_txd_a),
.RGMII_0_tx_ctl (rgmii_tx_ctl_a),
.RGMII_0_txc (rgmii_txc_a),
.ref_clk_125 (ref_clk_125),
.speed_mode_a (speed_mode_a_s),
.MDIO_PHY_1_mdc (mdc_fmc_b),
.MDIO_PHY_1_mdio_io (mdio_fmc_b),
.RGMII_1_rd (rgmii_rxd_b),
.RGMII_1_rx_ctl (rgmii_rx_ctl_b),
.RGMII_1_rxc (rgmii_rxc_b),
.RGMII_1_td (rgmii_txd_b),
.RGMII_1_tx_ctl (rgmii_tx_ctl_b),
.RGMII_1_txc (rgmii_txc_b),
.speed_mode_b (speed_mode_b_s)
);
endmodule
// ***************************************************************************
// ***************************************************************************