diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl index 9bdb1e07b..70a97841d 100644 --- a/projects/fmcomms2/common/fmcomms2_bd.tcl +++ b/projects/fmcomms2/common/fmcomms2_bd.tcl @@ -31,6 +31,17 @@ if {$sys_zynq == 0} { set gpio_fmcomms2_t [create_bd_port -dir O -from 16 -to 0 gpio_fmcomms2_t] } +if {$sys_zynq == 1} { + set spi_udc_clk_i [create_bd_port -dir I spi_udc_clk_i] + set spi_udc_clk_o [create_bd_port -dir O spi_udc_clk_o] + set spi_udc_csn_i [create_bd_port -dir I spi_udc_csn_i] + set spi_udc_csn_tx_o [create_bd_port -dir O spi_udc_csn_tx_o] + set spi_udc_csn_rx_o [create_bd_port -dir O spi_udc_csn_rx_o] + set spi_udc_mosi_i [create_bd_port -dir I spi_udc_mosi_i] + set spi_udc_mosi_o [create_bd_port -dir O spi_udc_mosi_o] + set spi_udc_miso_i [create_bd_port -dir I spi_udc_miso_i] +} + # ad9361 core set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361] @@ -129,6 +140,13 @@ if {$sys_zynq == 1} { set_property LEFT 48 [get_bd_ports GPIO_T] } + # additional spi for up/down converter + +if {$sys_zynq == 1} { + set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7 +} + # connections (spi) if {$sys_zynq == 0} { @@ -158,6 +176,19 @@ if {$sys_zynq == 0} { connect_bd_net -net gpio_fmcomms2_t [get_bd_ports gpio_fmcomms2_t] [get_bd_pins axi_fmcomms2_gpio/gpio_io_t] connect_bd_net -net axi_fmcomms2_gpio_irq [get_bd_pins axi_fmcomms2_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In8] } + + # connections (up/down converter spi) + +if {$sys_zynq == 1} { + connect_bd_net -net spi_udc_csn_i [get_bd_ports spi_udc_csn_i] [get_bd_pins sys_ps7/SPI1_SS_I] + connect_bd_net -net spi_udc_csn_tx_o [get_bd_ports spi_udc_csn_tx_o] [get_bd_pins sys_ps7/SPI1_SS_O] + connect_bd_net -net spi_udc_csn_rx_o [get_bd_ports spi_udc_csn_rx_o] [get_bd_pins sys_ps7/SPI1_SS1_O] + connect_bd_net -net spi_udc_clk_i [get_bd_ports spi_udc_clk_i] [get_bd_pins sys_ps7/SPI1_SCLK_I] + connect_bd_net -net spi_udc_clk_o [get_bd_ports spi_udc_clk_o] [get_bd_pins sys_ps7/SPI1_SCLK_O] + connect_bd_net -net spi_udc_mosi_i [get_bd_ports spi_udc_mosi_i] [get_bd_pins sys_ps7/SPI1_MOSI_I] + connect_bd_net -net spi_udc_mosi_o [get_bd_ports spi_udc_mosi_o] [get_bd_pins sys_ps7/SPI1_MOSI_O] + connect_bd_net -net spi_udc_miso_i [get_bd_ports spi_udc_miso_i] [get_bd_pins sys_ps7/SPI1_MISO_I] +} # connections (ad9361) connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9361/delay_clk] @@ -263,7 +294,6 @@ if {$sys_zynq == 1} { connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source } - # interconnect (mem/dac) if {$sys_zynq == 0} { diff --git a/projects/fmcomms2/zc702/system_top.v b/projects/fmcomms2/zc702/system_top.v index ad8776bad..596ce359e 100644 --- a/projects/fmcomms2/zc702/system_top.v +++ b/projects/fmcomms2/zc702/system_top.v @@ -250,7 +250,15 @@ module system_top ( .tx_data_out_n (tx_data_out_n), .tx_data_out_p (tx_data_out_p), .tx_frame_out_n (tx_frame_out_n), - .tx_frame_out_p (tx_frame_out_p)); + .tx_frame_out_p (tx_frame_out_p), + .spi_udc_clk_i (1'b0), + .spi_udc_clk_o (spi_udc_sclk), + .spi_udc_csn_i (1'b1), + .spi_udc_csn_tx_o (spi_udc_csn_tx), + .spi_udc_csn_rx_o (spi_udc_csn_rx), + .spi_udc_mosi_i (spi_udc_data), + .spi_udc_mosi_o (spi_udc_data), + .spi_udc_miso_i (1'b0)); endmodule diff --git a/projects/fmcomms2/zc706/system_constr.xdc b/projects/fmcomms2/zc706/system_constr.xdc index 83e5fdcf3..62e133203 100644 --- a/projects/fmcomms2/zc706/system_constr.xdc +++ b/projects/fmcomms2/zc706/system_constr.xdc @@ -58,6 +58,13 @@ set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports spi_clk] set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## C26 FMC_LPC_LA27_P set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## C27 FMC_LPC_LA27_N +# spi pmod J58 + +set_property -dict {PACKAGE_PIN AJ21 IOSTANDARD LVCMOS25} [get_ports spi_udc_csn_tx] ; ## PMOD1_0_LS +set_property -dict {PACKAGE_PIN AK21 IOSTANDARD LVCMOS25} [get_ports spi_udc_csn_rx] ; ## PMOD1_1_LS +set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS25} [get_ports spi_udc_sclk] ; ## PMOD1_3_LS +set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS25} [get_ports spi_udc_data] ; ## PMOD1_2_LS + # clocks create_clock -name rx_clk -period 4.00 [get_ports rx_clk_in_p] diff --git a/projects/fmcomms2/zc706/system_top.v b/projects/fmcomms2/zc706/system_top.v index 3ed444e1a..d2ee4a70d 100644 --- a/projects/fmcomms2/zc706/system_top.v +++ b/projects/fmcomms2/zc706/system_top.v @@ -101,7 +101,12 @@ module system_top ( spi_csn, spi_clk, spi_mosi, - spi_miso); + spi_miso, + + spi_udc_csn_tx, + spi_udc_csn_rx, + spi_udc_sclk, + spi_udc_data); inout [14:0] DDR_addr; inout [ 2:0] DDR_ba; @@ -165,6 +170,11 @@ module system_top ( output spi_mosi; input spi_miso; + output spi_udc_csn_tx; + output spi_udc_csn_rx; + output spi_udc_sclk; + output spi_udc_data; + // internal signals wire [48:0] gpio_i; @@ -237,7 +247,15 @@ module system_top ( .tx_data_out_n (tx_data_out_n), .tx_data_out_p (tx_data_out_p), .tx_frame_out_n (tx_frame_out_n), - .tx_frame_out_p (tx_frame_out_p)); + .tx_frame_out_p (tx_frame_out_p), + .spi_udc_clk_i (1'b0), + .spi_udc_clk_o (spi_udc_sclk), + .spi_udc_csn_i (1'b1), + .spi_udc_csn_tx_o (spi_udc_csn_tx), + .spi_udc_csn_rx_o (spi_udc_csn_rx), + .spi_udc_mosi_i (spi_udc_data), + .spi_udc_mosi_o (spi_udc_data), + .spi_udc_miso_i (1'b0)); endmodule diff --git a/projects/fmcomms2/zed/system_constr.xdc b/projects/fmcomms2/zed/system_constr.xdc index eb149178a..bc569a939 100644 --- a/projects/fmcomms2/zed/system_constr.xdc +++ b/projects/fmcomms2/zed/system_constr.xdc @@ -58,6 +58,13 @@ set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports spi_clk] set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## C26 FMC_LPC_LA27_P set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## C27 FMC_LPC_LA27_N +# spi pmod JA1 + +set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports spi_udc_csn_tx] ; ## JA1 +set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS33} [get_ports spi_udc_csn_rx] ; ## JA2 +set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVCMOS33} [get_ports spi_udc_sclk] ; ## JA4 +set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS33} [get_ports spi_udc_data] ; ## JA3 + # clocks create_clock -name rx_clk -period 4 [get_ports rx_clk_in_p] diff --git a/projects/fmcomms2/zed/system_top.v b/projects/fmcomms2/zed/system_top.v index 146c0914d..270d3835a 100644 --- a/projects/fmcomms2/zed/system_top.v +++ b/projects/fmcomms2/zed/system_top.v @@ -111,7 +111,12 @@ module system_top ( spi_csn, spi_clk, spi_mosi, - spi_miso); + spi_miso, + + spi_udc_csn_tx, + spi_udc_csn_rx, + spi_udc_sclk, + spi_udc_data); inout [14:0] DDR_addr; inout [ 2:0] DDR_ba; @@ -185,6 +190,11 @@ module system_top ( output spi_mosi; input spi_miso; + output spi_udc_csn_tx; + output spi_udc_csn_rx; + output spi_udc_sclk; + output spi_udc_data; + // internal signals wire [48:0] gpio_i; @@ -287,7 +297,15 @@ module system_top ( .tx_data_out_n (tx_data_out_n), .tx_data_out_p (tx_data_out_p), .tx_frame_out_n (tx_frame_out_n), - .tx_frame_out_p (tx_frame_out_p)); + .tx_frame_out_p (tx_frame_out_p), + .spi_udc_clk_i (1'b0), + .spi_udc_clk_o (spi_udc_sclk), + .spi_udc_csn_i (1'b1), + .spi_udc_csn_tx_o (spi_udc_csn_tx), + .spi_udc_csn_rx_o (spi_udc_csn_rx), + .spi_udc_mosi_i (spi_udc_data), + .spi_udc_mosi_o (spi_udc_data), + .spi_udc_miso_i (1'b0)); endmodule