diff --git a/library/axi_ad9467/axi_ad9467.v b/library/axi_ad9467/axi_ad9467.v index 1a0957737..15ac2f5f5 100644 --- a/library/axi_ad9467/axi_ad9467.v +++ b/library/axi_ad9467/axi_ad9467.v @@ -147,28 +147,25 @@ module axi_ad9467( wire adc_rst; wire up_clk; wire up_rstn; + wire delay_rst; // internal signals wire [15:0] adc_data_s; wire adc_or_s; wire adc_ddr_edgesel_s; - wire delay_rst_s; - wire delay_sel_s; - wire delay_rwn_s; - wire [ 7:0] delay_addr_s; - wire [ 4:0] delay_wdata_s; - wire [ 4:0] delay_rdata_s; - wire delay_ack_t_s; + wire [ 8:0] up_dld_s; + wire [44:0] up_dwdata_s; + wire [44:0] up_drdata_s; wire delay_locked_s; wire up_status_pn_err_s; wire up_status_pn_oos_s; wire up_status_or_s; wire up_rreq_s; wire [13:0] up_raddr_s; - wire [31:0] up_rdata_s[0:1]; - wire up_rack_s[0:1]; - wire up_wack_s[0:1]; + wire [31:0] up_rdata_s[0:2]; + wire up_rack_s[0:2]; + wire up_wack_s[0:2]; wire up_wreq_s; wire [13:0] up_waddr_s; wire [31:0] up_wdata_s; @@ -187,9 +184,9 @@ module axi_ad9467( up_rack <= 1'd0; up_wack <= 1'd0; end else begin - up_rdata <= up_rdata_s[0] | up_rdata_s[1]; - up_rack <= up_rack_s[0] | up_rack_s[1]; - up_wack <= up_wack_s[0] | up_wack_s[1]; + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2]; + up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2]; + up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2]; end end @@ -209,14 +206,12 @@ module axi_ad9467( .adc_data (adc_data_s), .adc_or (adc_or_s), .adc_ddr_edgesel (adc_ddr_edgesel_s), + .up_clk (up_clk), + .up_dld (up_dld_s), + .up_dwdata (up_dwdata_s), + .up_drdata (up_drdata_s), .delay_clk (delay_clk), - .delay_rst (delay_rst_s), - .delay_sel (delay_sel_s), - .delay_rwn (delay_rwn_s), - .delay_addr (delay_addr_s), - .delay_wdata (delay_wdata_s), - .delay_rdata (delay_rdata_s), - .delay_ack_t (delay_ack_t_s), + .delay_rst (delay_rst), .delay_locked (delay_locked_s)); // channel @@ -242,6 +237,26 @@ module axi_ad9467( .up_rdata (up_rdata_s[0]), .up_rack (up_rack_s[0])); + // adc delay control + + up_delay_cntrl #(.IO_WIDTH(9), .IO_BASEADDR(6'h02)) i_delay_cntrl ( + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s), + .up_dld (up_dld_s), + .up_dwdata (up_dwdata_s), + .up_drdata (up_drdata_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + // common processor control up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common ( @@ -252,21 +267,15 @@ module axi_ad9467( .adc_ddr_edgesel (adc_ddr_edgesel_s), .adc_pin_mode (), .adc_status (1'b1), + .adc_sync_status (1'd0), .adc_status_ovf (adc_dovf), .adc_status_unf (adc_dunf), .adc_clk_ratio (32'b1), + .adc_start_code (), + .adc_sync (), .up_status_pn_err (up_status_pn_err_s), .up_status_pn_oos (up_status_pn_oos_s), .up_status_or (up_status_or_s), - .delay_clk (delay_clk), - .delay_rst (delay_rst_s), - .delay_sel (delay_sel_s), - .delay_rwn (delay_rwn_s), - .delay_addr (delay_addr_s), - .delay_wdata (delay_wdata_s), - .delay_rdata (delay_rdata_s), - .delay_ack_t (delay_ack_t_s), - .delay_locked (delay_locked_s), .drp_clk (1'b0), .drp_rst (), .drp_sel (), diff --git a/library/axi_ad9467/axi_ad9467_if.v b/library/axi_ad9467/axi_ad9467_if.v index 4c429ee3d..f7c9a7b56 100644 --- a/library/axi_ad9467/axi_ad9467_if.v +++ b/library/axi_ad9467/axi_ad9467_if.v @@ -64,14 +64,12 @@ module axi_ad9467_if ( // delay control signals + up_clk, + up_dld, + up_dwdata, + up_drdata, delay_clk, delay_rst, - delay_sel, - delay_rwn, - delay_addr, - delay_wdata, - delay_rdata, - delay_ack_t, delay_locked); // buffer type based on the target device. @@ -100,14 +98,12 @@ module axi_ad9467_if ( // delay control signals + input up_clk; + input [ 8:0] up_dld; + input [44:0] up_dwdata; + output [44:0] up_drdata; input delay_clk; input delay_rst; - input delay_sel; - input delay_rwn; - input [ 7:0] delay_addr; - input [ 4:0] delay_wdata; - output [ 4:0] delay_rdata; - output delay_ack_t; output delay_locked; // internal registers @@ -121,13 +117,9 @@ module axi_ad9467_if ( reg adc_or_p = 'd0; reg adc_or_n = 'd0; reg adc_or = 'd0; - reg [ 8:0] delay_ld = 'd0; - reg delay_ack_t = 'd0; - reg [ 4:0] delay_rdata = 'd0; // internal signals - wire [ 4:0] delay_rdata_s[8:0]; wire [ 7:0] adc_data_p_s; wire [ 7:0] adc_data_n_s; wire adc_or_p_s; @@ -168,49 +160,6 @@ module axi_ad9467_if ( end end - // delay write interface, each delay element can be individually - // addressed, and a delay value can be directly loaded (no inc/dec stuff) - - always @(posedge delay_clk) begin - if ((delay_sel == 1'b1) && (delay_rwn == 1'b0)) begin - case (delay_addr) - 8'd8 : delay_ld <= 9'h100; - 8'd7 : delay_ld <= 9'h080; - 8'd6 : delay_ld <= 9'h040; - 8'd5 : delay_ld <= 9'h020; - 8'd4 : delay_ld <= 9'h010; - 8'd3 : delay_ld <= 9'h008; - 8'd2 : delay_ld <= 9'h004; - 8'd1 : delay_ld <= 9'h002; - 8'd0 : delay_ld <= 9'h001; - default: delay_ld <= 9'h000; - endcase - end else begin - delay_ld <= 9'h000; - end - end - - // delay read interface, a delay ack toggle is used to transfer data to the - // processor side- delay locked is independently transferred - - always @(posedge delay_clk) begin - case (delay_addr) - 8'd8 : delay_rdata <= delay_rdata_s[8]; - 8'd7 : delay_rdata <= delay_rdata_s[7]; - 8'd6 : delay_rdata <= delay_rdata_s[6]; - 8'd5 : delay_rdata <= delay_rdata_s[5]; - 8'd4 : delay_rdata <= delay_rdata_s[4]; - 8'd3 : delay_rdata <= delay_rdata_s[3]; - 8'd2 : delay_rdata <= delay_rdata_s[2]; - 8'd1 : delay_rdata <= delay_rdata_s[1]; - 8'd0 : delay_rdata <= delay_rdata_s[0]; - default: delay_rdata <= 5'd0; - endcase - if (delay_sel == 1'b1) begin - delay_ack_t <= ~delay_ack_t; - end - end - // data interface generate @@ -225,11 +174,12 @@ module axi_ad9467_if ( .rx_data_in_n (adc_data_in_n[l_inst]), .rx_data_p (adc_data_p_s[l_inst]), .rx_data_n (adc_data_n_s[l_inst]), + .up_clk (up_clk), + .up_dld (up_dld[l_inst]), + .up_dwdata (up_dwdata[((l_inst*5)+4):(l_inst*5)]), + .up_drdata (up_drdata[((l_inst*5)+4):(l_inst*5)]), .delay_clk (delay_clk), .delay_rst (delay_rst), - .delay_ld (delay_ld[l_inst]), - .delay_wdata (delay_wdata), - .delay_rdata (delay_rdata_s[l_inst]), .delay_locked ()); end endgenerate @@ -246,11 +196,12 @@ module axi_ad9467_if ( .rx_data_in_n (adc_or_in_n), .rx_data_p (adc_or_p_s), .rx_data_n (adc_or_n_s), + .up_clk (up_clk), + .up_dld (up_dld[8]), + .up_dwdata (up_dwdata[44:40]), + .up_drdata (up_drdata[44:40]), .delay_clk (delay_clk), .delay_rst (delay_rst), - .delay_ld (delay_ld[8]), - .delay_wdata (delay_wdata), - .delay_rdata (delay_rdata_s[8]), .delay_locked (delay_locked)); // clock