docs/projects/ad9783 & images: Add ad9783_ebz project doc
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>main
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@ -21,6 +21,7 @@ HDL Reference Designs
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:hidden:
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projects/ad9081_fmca_ebz/index
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projects/ad9783_ebz/index
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.. role:: red
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.. role:: green
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.. _ad9783_ebz_hdl:
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AD9783-EBZ HDL project
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===============================================================================
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Overview
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-------------------------------------------------------------------------------
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The :part:`AD9783` includes pin-compatible, high dynamic range, dual
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digital-to-analog converters (DACs) with 16-bit resolution, and sample rates of
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up to 500 MSPS.
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The device includes specific features for direct conversion transmit
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applications, including gain and offset compensation, interfacing seamlessly
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with analog quadrature modulators.
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The :part:`EVAL-AD9783` board is connected to the FPGA carrier through
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:part:`AD-DAC-FMC`-ADP interposer board.
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Supported boards
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-------------------------------------------------------------------------------
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- :part:`EVAL-AD9783`
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Supported devices
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-------------------------------------------------------------------------------
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- :part:`AD9780`
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- :part:`AD9781`
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- :part:`AD9783`
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Supported carriers
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-------------------------------------------------------------------------------
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- :xilinx:`ZCU102` on FMC HPC0 slot
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Block design
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-------------------------------------------------------------------------------
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Block diagram
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The data path and clock domains are depicted in the below diagram:
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.. image:: ../images/ad9783_ebz/ad9783_zcu102_block_diagram.svg
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:width: 800
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:align: center
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:alt: AD9783-EBZ/ZCU102 block diagram
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Clock scheme
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- External clock source connected to J1 (CLOCK IN)
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- For maximum performance, give a 500 MHz clock
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To make the connection between the :part:`EVAL-AD9783` evaluation board and
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the carrier using SPI, some hardware changes must be done to the evaluation
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board. These are presented in detail in the **Connections and hardware changes**
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section.
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CPU/Memory interconnects addresses
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The addresses are dependent on the architecture of the FPGA, having an offset
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added to the base address from HDL (see more at :ref:`architecture`).
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============== =============== ===========
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Instance Zynq/Microblaze ZynqMP
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============== =============== ===========
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axi_ad9783 0x7420_0000 0x9420_0000
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axi_ad9783_dma 0x7C42_0000 0x9C42_0000
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============== =============== ===========
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SPI connections
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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For the evaluation board to communicate through SPI with the carrier, some
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hardware changes must be done, which are explained in the system level
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documentation.
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.. list-table::
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:widths: 25 25 25 25
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:header-rows: 1
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* - SPI type
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- SPI manager instance
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- SPI subordinate
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- CS nb
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* - PS
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- SPI 0
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- AD9783
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- 0
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Interrupts
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Below are the Programmable Logic interrupts used in this project.
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============== === ============ =============
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Instance name HDL Linux ZynqMP Actual ZynqMP
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============== === ============ =============
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axi_ad9783_dma 12 108 140
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============== === ============ =============
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Building the HDL project
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-------------------------------------------------------------------------------
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The design is built upon ADI's generic HDL reference design framework.
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ADI does not distribute the bit/elf files of these projects so they
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must be built from the sources available :git-hdl:`here <master:/>`. To get
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the source you must
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`clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__
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the HDL repository, and then build the project as follows:
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**Linux/Cygwin/WSL**
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.. code-block::
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user@analog:~$ cd hdl/projects/ad9783_ebz/zcu102
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user@analog:~/hdl/projects/ad9783_ebz/zcu102$ make
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A more comprehensive build guide can be found in the :ref:`build_hdl` user guide.
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Software considerations
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-------------------------------------------------------------------------------
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The SPI communication is changed because of hardware modifications, so the
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connection looks like this:
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|ad9783_zcu102_spi_pmod.svg|
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Resources
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-------------------------------------------------------------------------------
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Systems related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Here you can find the quick start guides available for these evaluation boards:
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.. list-table::
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:widths: 20 10 20 20 20 10
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:header-rows: 1
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* - Evaluation board
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- Zynq-7000
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- Zynq UltraScale+ MP
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- Microblaze
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- Versal
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- Arria 10
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* - AD9783-EBZ
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- ---
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- :dokuwiki:`[Wiki] ZCU102 <resources/fpga/xilinx/interposer/ad9783>`
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- ---
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- ---
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- ---
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Hardware related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- Product datasheets:
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- :part:`AD9780`
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- :part:`AD9781`
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- :part:`AD9783`
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- :part:`EVAL-AD9783`
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- :part:`AD-DAC-FMC`-ADP
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HDL related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- :git-hdl:`AD9783_EBZ HDL project source code <master:projects/ad9783_ebz>`
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.. list-table::
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:widths: 30 35 35
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:header-rows: 1
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* - IP name
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- Source code link
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- Documentation link
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* - AXI_AD9783
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- :git-hdl:`library/axi_ad9783 <master:library/axi_ad9783>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_ad9783>`
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* - AXI_DMAC
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- :git-hdl:`library/axi_dmac <master:library/axi_dmac>`
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- :ref:`here <axi_dmac>`
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* - AXI_SYSID
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- :git-hdl:`library/axi_sysid <master:library/axi_sysid>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_sysid>`
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* - SYSID_ROM
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- :git-hdl:`library/sysid_rom <master:library/sysid_rom>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_sysid>`
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* - UTIL_UPACK2
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- :git-hdl:`library/util_pack/util_upack2 <master:library/util_pack/util_upack2>`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/util_upack>`
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Software related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- :git-linux:`Linux device tree zynqmp-zcu102-rev10-ad9783.dts <master:arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9783.dts>`
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- :git-linux:`Linux driver ad9783.c <master:drivers/iio/frequency>`
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.. include:: ../common/more_information.rst
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.. include:: ../common/support.rst
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.. |ad9783_zcu102_spi_pmod.svg| image:: ../images/ad9783_ebz/ad9783_zcu102_spi_pmod.svg
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:width: 600
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:align: top
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:alt: AD9783-EBZ/ZCU102 SPI Pmod connection
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After Width: | Height: | Size: 36 KiB |
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Reference in New Issue