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axi_logic_analyzer: equalize delay paths 

- Add parameter for input data delay time to easily match the one of the
adc_trigger.
- Change the trigger delay path to match between the internal and
external(adc_trigger delays).
main
AndreiGrozav 2019-09-06 15:37:59 +03:00 committed by AndreiGrozav
parent 5e08e2d548
commit f5ac0f7019
2 changed files with 57 additions and 40 deletions
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63
library/axi_logic_analyzer/axi_logic_analyzer.v
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@ -35,7 +35,13 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module axi_logic_analyzer ( module axi_logic_analyzer #(
// add sample delays on LA to compensate for adc path delay
parameter ADC_PATH_DELAY = 19) (
// interface
input clk, input clk,
output clk_out, output clk_out,
@ -45,7 +51,7 @@ module axi_logic_analyzer (
output [15:0] data_t, output [15:0] data_t,
input [ 1:0] trigger_i, input [ 1:0] trigger_i,
output reg adc_valid, output adc_valid,
output [15:0] adc_data, output [15:0] adc_data,
input [15:0] dac_data, input [15:0] dac_data,
@ -83,7 +89,6 @@ module axi_logic_analyzer (
// internal registers // internal registers
reg [15:0] data_m1 = 'd0;
reg [15:0] data_r = 'd0; reg [15:0] data_r = 'd0;
reg [ 1:0] trigger_m1 = 'd0; reg [ 1:0] trigger_m1 = 'd0;
reg [31:0] downsampler_counter_la = 'd0; reg [31:0] downsampler_counter_la = 'd0;
@ -107,7 +112,7 @@ module axi_logic_analyzer (
reg streaming_on; reg streaming_on;
reg [15:0] adc_data_m2 = 'd0; reg [15:0] adc_data_mn = 'd0;
// internal signals // internal signals
@ -156,7 +161,7 @@ module axi_logic_analyzer (
assign trigger_out = trigger_delay == 32'h0 ? trigger_out_s | streaming_on : trigger_out_delayed | streaming_on; assign trigger_out = trigger_delay == 32'h0 ? trigger_out_s | streaming_on : trigger_out_delayed | streaming_on;
assign trigger_out_delayed = delay_counter == 32'h0 ? 1 : 0; assign trigger_out_delayed = delay_counter == 32'h0 ? 1 : 0;
assign adc_data = adc_data_m2; assign adc_data = adc_data_mn;
always @(posedge clk_out) begin always @(posedge clk_out) begin
if (trigger_delay == 0) begin if (trigger_delay == 0) begin
@ -218,26 +223,38 @@ module axi_logic_analyzer (
.I1 (data_i[0]), .I1 (data_i[0]),
.S (clock_select)); .S (clock_select));
// synchronization // - synchronization
// - compensate for m2k adc path delay
// - transfer data at clock frequency if capture is enabled
always @(posedge clk_out) begin genvar j;
if (sample_valid_la == 1'b1) begin
data_m1 <= data_i; generate
trigger_m1 <= trigger_i;
reg [15:0] data_m[ADC_PATH_DELAY-2:0];
always @(posedge clk_out) begin
if (sample_valid_la == 1'b1) begin
data_m[0] <= data_i;
end
end end
end
// transfer data at clock frequency for (j = 0; j < ADC_PATH_DELAY - 2; j = j + 1) begin
// if capture is enabled always @(posedge clk_out) begin
if (sample_valid_la == 1'b1) begin
always @(posedge clk_out) begin data_m[j+1] <= data_m[j];
if (sample_valid_la == 1'b1) begin end
adc_data_m2 <= data_m1; end
adc_valid <= 1'b1;
end else begin
adc_valid <= 1'b0;
end end
end
always @(posedge clk_out) begin
if (sample_valid_la == 1'b1) begin
adc_data_mn <= data_m[ADC_PATH_DELAY-2];
end
end
endgenerate
assign adc_valid = sample_valid_la;
// downsampler logic analyzer // downsampler logic analyzer
@ -295,7 +312,7 @@ module axi_logic_analyzer (
.clk (clk_out), .clk (clk_out),
.reset (reset), .reset (reset),
.data (adc_data_m2), .data (adc_data_mn),
.data_valid(sample_valid_la), .data_valid(sample_valid_la),
.trigger_i (trigger_m1), .trigger_i (trigger_m1),
.trigger_in (trigger_in), .trigger_in (trigger_in),
@ -329,7 +346,7 @@ module axi_logic_analyzer (
.clock_select (clock_select), .clock_select (clock_select),
.overwrite_enable (overwrite_enable), .overwrite_enable (overwrite_enable),
.overwrite_data (overwrite_data), .overwrite_data (overwrite_data),
.input_data (adc_data_m2), .input_data (adc_data_mn),
.od_pp_n (od_pp_n), .od_pp_n (od_pp_n),
.triggered (up_triggered), .triggered (up_triggered),

34
library/axi_logic_analyzer/axi_logic_analyzer_trigger.v
View File

@ -66,13 +66,11 @@ module axi_logic_analyzer_trigger (
reg trigger_active; reg trigger_active;
reg trigger_active_mux; reg trigger_active_mux;
reg trigger_active_d1; reg trigger_active_d1;
reg trigger_active_d2;
always @(posedge clk) begin always @(posedge clk) begin
if (data_valid == 1'b1) begin if (data_valid == 1'b1) begin
trigger_active_d1 <= trigger_active_mux; trigger_active_d1 <= trigger_active_mux;
trigger_active_d2 <= trigger_active_d1; trigger_out <= trigger_active_d1;
trigger_out <= trigger_active_d2;
trigger_out_adc <= trigger_active_mux; trigger_out_adc <= trigger_active_mux;
end end
end end
@ -82,20 +80,22 @@ module axi_logic_analyzer_trigger (
// 0 OR // 0 OR
// 1 AND // 1 AND
always @(*) begin always @(posedge clk) begin
case (trigger_logic[0]) if (data_valid == 1'b1) begin
0: trigger_active = |((edge_detect & edge_detect_enable) | case (trigger_logic[0])
(rise_edge & rise_edge_enable) | 0: trigger_active <= |((edge_detect & edge_detect_enable) |
(fall_edge & fall_edge_enable) | (rise_edge & rise_edge_enable) |
(low_level & low_level_enable) | (fall_edge & fall_edge_enable) |
(high_level & high_level_enable)); (low_level & low_level_enable) |
1: trigger_active = &((edge_detect | ~edge_detect_enable) & (high_level & high_level_enable));
(rise_edge | ~rise_edge_enable) & 1: trigger_active <= &((edge_detect | ~edge_detect_enable) &
(fall_edge | ~fall_edge_enable) & (rise_edge | ~rise_edge_enable) &
(low_level | ~low_level_enable) & (fall_edge | ~fall_edge_enable) &
(high_level | ~high_level_enable)); (low_level | ~low_level_enable) &
default: trigger_active = 1'b1; (high_level | ~high_level_enable));
endcase default: trigger_active = 1'b1;
endcase
end
end end
always @(*) begin always @(*) begin