util_extract: Compensate 4 word latency
parent
54e96c49ae
commit
f6288dc0a3
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@ -47,6 +47,7 @@ module util_extract #(
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input data_valid,
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output [DATA_WIDTH-1:0] data_out,
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output reg valid_out,
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output reg trigger_out
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);
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@ -55,6 +56,9 @@ module util_extract #(
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genvar n;
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reg trigger_d1;
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reg trigger_d2;
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reg trigger_d3;
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reg trigger_d4;
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wire [15:0] trigger; // 16 maximum channels
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@ -70,9 +74,12 @@ module util_extract #(
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// compensate delay in the FIFO
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always @(posedge clk) begin
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valid_out <= data_valid;
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if (data_valid == 1'b1) begin
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trigger_d1 <= |trigger;
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trigger_out <= trigger_d1;
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trigger_d2 <= trigger_d1;
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trigger_d3 <= trigger_d2;
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trigger_out <= trigger_d3;
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end
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end
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