diff --git a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl new file mode 100644 index 000000000..f876a8034 --- /dev/null +++ b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl @@ -0,0 +1,275 @@ + + # motor control + + # position detection interface + + set position_i [ create_bd_port -dir I -from 2 -to 0 position_i ] + + # current monitor 1 interface + + set adc_clk_o [ create_bd_port -dir O adc_clk_o ] + + set adc_m1_ia_dat_i [ create_bd_port -dir I adc_m1_ia_dat_i ] + set adc_m1_ib_dat_i [ create_bd_port -dir I adc_m1_ib_dat_i ] + set adc_m1_vbus_dat_i [ create_bd_port -dir I adc_m1_vbus_dat_i ] + + # current monitor 2 interface + + set adc_m2_ia_dat_i [ create_bd_port -dir I adc_m2_ia_dat_i ] + set adc_m2_ib_dat_i [ create_bd_port -dir I adc_m2_ib_dat_i ] + set adc_m2_vbus_dat_i [ create_bd_port -dir I adc_m2_vbus_dat_i ] + + # motor control interface + + set fmc_m1_en_o [ create_bd_port -dir O fmc_m1_en_o ] + set fmc_m2_en_o [ create_bd_port -dir O fmc_m2_en_o ] + + # gpo interface + + set gpo_o [ create_bd_port -dir O -from 3 -to 0 gpo_o ] + + # interrupts + + set motcon2_c_m_1_irq [create_bd_port -dir O motcon2_c_m_1_irq] + set motcon2_c_m_2_irq [create_bd_port -dir O motcon2_c_m_2_irq] + set motcon2_s_d_irq [create_bd_port -dir O motcon2_s_d_irq] + + # Ethernet + + set eth2_mdio [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 eth2_mdio ] + set eth2_rgmii [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rgmii_rtl:1.0 eth2_rgmii ] + + set eth2_phy_rst_n [ create_bd_port -dir O eth2_phy_rst_n ] + + # xadc interface + + create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0 + create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8 + create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn + + # additions to default configuration + + set_property -dict [list CONFIG.NUM_MI {14}] $axi_cpu_interconnect + + + set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1} ] $sys_ps7 + set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1} ] $sys_ps7 + set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1} ] $sys_ps7 + set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1} ] $sys_ps7 + set_property -dict [list CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {1} ] $sys_ps7 + + # current monitor 1 peripherals + + set axi_mc_current_monitor_1 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_current_monitor:1.0 axi_mc_current_monitor_1 ] + + set axi_current_monitor_1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_current_monitor_1_dma] + set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_current_monitor_1_dma + set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_current_monitor_1_dma + set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_current_monitor_1_dma + set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_current_monitor_1_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_current_monitor_1_dma + set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_current_monitor_1_dma + set_property -dict [list CONFIG.C_DMA_AXI_PROTOCOL_DEST {1}] $axi_current_monitor_1_dma + + # current monitor 2 peripherals + + set axi_mc_current_monitor_2 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_current_monitor:1.0 axi_mc_current_monitor_2 ] + + set axi_current_monitor_2_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_current_monitor_2_dma] + set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_current_monitor_2_dma + set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_current_monitor_2_dma + set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_current_monitor_2_dma + set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_current_monitor_2_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_current_monitor_2_dma + set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_current_monitor_2_dma + set_property -dict [list CONFIG.C_DMA_AXI_PROTOCOL_DEST {1}] $axi_current_monitor_2_dma + + # speed detector + +# set axi_mc_speed_1 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_speed:1.0 axi_mc_speed_1 ] + +# set axi_speed_detector_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_speed_detector_dma] +# set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_speed_detector_dma +# set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_speed_detector_dma +# set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_speed_detector_dma +# set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_speed_detector_dma +# set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_speed_detector_dma +# set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {32}] $axi_speed_detector_dma +# set_property -dict [list CONFIG.C_DMA_AXI_PROTOCOL_DEST {1}] $axi_speed_detector_dma + + # xadc + + set xadc_wiz_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.0 xadc_wiz_1 ] + set_property -dict [ list CONFIG.CHANNEL_ENABLE_VAUXP0_VAUXN0 {true} ] $xadc_wiz_1 + set_property -dict [ list CONFIG.ENABLE_EXTERNAL_MUX {false} ] $xadc_wiz_1 + set_property -dict [ list CONFIG.OT_ALARM {false} ] $xadc_wiz_1 + set_property -dict [ list CONFIG.USER_TEMP_ALARM {false} ] $xadc_wiz_1 + set_property -dict [ list CONFIG.VCCAUX_ALARM {false} ] $xadc_wiz_1 + set_property -dict [ list CONFIG.VCCINT_ALARM {false} ] $xadc_wiz_1 + set_property -dict [ list CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} ] $xadc_wiz_1 + + #ethernet + + set gmii_to_rgmii_eth2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:gmii_to_rgmii:3.0 gmii_to_rgmii_eth2 ] + set_property -dict [ list CONFIG.C_PHYADDR {1} CONFIG.SupportLevel {Include_Shared_Logic_in_Core} ] $gmii_to_rgmii_eth2 + + # connections + + # position + +# connect_bd_net -net position_i_1 [get_bd_ports position_i] [get_bd_pins axi_mc_speed_1/position_i] +# connect_bd_net -net position_i_1 [get_bd_pins axi_mc_speed_1/bemf_i] + + # current monitor 1 + + connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_current_monitor_1/ref_clk] $sys_100m_clk_source + + connect_bd_net -net adc_m1_ia_dat_i_1 [get_bd_ports adc_m1_ia_dat_i] [get_bd_pins axi_mc_current_monitor_1/adc_ia_dat_i] + connect_bd_net -net adc_m1_ib_dat_i_1 [get_bd_ports adc_m1_ib_dat_i] [get_bd_pins axi_mc_current_monitor_1/adc_ib_dat_i] + connect_bd_net -net adc_m1_vbus_dat_i_1 [get_bd_ports adc_m1_vbus_dat_i] [get_bd_pins axi_mc_current_monitor_1/adc_vbus_dat_i] + + connect_bd_net -net axi_mc_current_monitor_1_adc_ia_clk_o [get_bd_ports adc_clk_o] [get_bd_pins axi_mc_current_monitor_1/adc_ia_clk_o] + + connect_bd_net -net axi_mc_current_monitor_1_adc_clk [get_bd_pins axi_mc_current_monitor_1/adc_clk_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_clk] + connect_bd_net -net axi_mc_current_monitor_1_adc_dwr [get_bd_pins axi_mc_current_monitor_1/adc_dwr_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_en] + connect_bd_net -net axi_mc_current_monitor_1_adc_ddata [get_bd_pins axi_mc_current_monitor_1/adc_ddata_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_din] + connect_bd_net -net axi_mc_current_monitor_1_adc_dsync [get_bd_pins axi_mc_current_monitor_1/adc_dsync_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_sync] + connect_bd_net -net axi_mc_current_monitor_1_adc_dovf [get_bd_pins axi_mc_current_monitor_1/adc_dovf_i] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_overflow] + + # interrupt + + connect_bd_net -net axi_current_monitor_1_dma_irq [get_bd_pins axi_current_monitor_1_dma/irq] [get_bd_ports motcon2_c_m_1_irq] + + # current monitor 2 + + connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_current_monitor_2/ref_clk] $sys_100m_clk_source + + connect_bd_net -net adc_m2_ia_dat_i [get_bd_ports adc_m2_ia_dat_i] [get_bd_pins axi_mc_current_monitor_2/adc_ia_dat_i] + connect_bd_net -net adc_m2_ib_dat_i [get_bd_ports adc_m2_ib_dat_i] [get_bd_pins axi_mc_current_monitor_2/adc_ib_dat_i] + connect_bd_net -net adc_m2_vbus_dat_i_1 [get_bd_ports adc_m2_vbus_dat_i] [get_bd_pins axi_mc_current_monitor_2/adc_vbus_dat_i] + + connect_bd_net -net axi_mc_current_monitor_2_adc_clk [get_bd_pins axi_mc_current_monitor_2/adc_clk_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_clk] + connect_bd_net -net axi_mc_current_monitor_2_adc_dwr [get_bd_pins axi_mc_current_monitor_2/adc_dwr_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_en] + connect_bd_net -net axi_mc_current_monitor_2_adc_ddata [get_bd_pins axi_mc_current_monitor_2/adc_ddata_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_din] + connect_bd_net -net axi_mc_current_monitor_2_adc_dsync [get_bd_pins axi_mc_current_monitor_2/adc_dsync_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_sync] + connect_bd_net -net axi_mc_current_monitor_2_adc_dovf [get_bd_pins axi_mc_current_monitor_2/adc_dovf_i] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_overflow] + + #interrupt + + connect_bd_net -net axi_current_monitor_2_dma_irq [get_bd_pins axi_current_monitor_2_dma/irq] [get_bd_ports motcon2_c_m_2_irq] + + # speed detector + +# connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_speed_1/ref_clk] $sys_100m_clk_source + + +# connect_bd_net -net speed_detector_adc_clk [get_bd_pins axi_mc_speed_1/adc_clk_o] [get_bd_pins axi_speed_detector_dma/fifo_wr_clk] +# connect_bd_net -net speed_detector_adc_dwr [get_bd_pins axi_mc_speed_1/adc_dwr_o] [get_bd_pins axi_speed_detector_dma/fifo_wr_en] +# connect_bd_net -net speed_detector_adc_ddata [get_bd_pins axi_mc_speed_1/adc_ddata_o] [get_bd_pins axi_speed_detector_dma/fifo_wr_din] +# connect_bd_net -net speed_detector_adc_dovf [get_bd_pins axi_mc_speed_1/adc_dovf_i] [get_bd_pins axi_speed_detector_dma/fifo_wr_overflow] + + # interrupt + +# connect_bd_net -net axi_speed_detector_dma_irq [get_bd_pins axi_speed_detector_dma/irq] [get_bd_ports motcon2_s_d_irq] + + # xadc + + connect_bd_net -net sys_100m_clk [get_bd_pins xadc_wiz_1/s_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_resetn [get_bd_pins xadc_wiz_1/s_axi_aresetn] $sys_100m_resetn_source + + connect_bd_intf_net -intf_net Vp_Vn_1 [get_bd_intf_pins xadc_wiz_1/Vp_Vn] [get_bd_intf_ports Vp_Vn] + connect_bd_intf_net -intf_net Vaux0_1 [get_bd_intf_pins xadc_wiz_1/Vaux0] [get_bd_intf_ports Vaux0] + connect_bd_intf_net -intf_net Vaux8_1 [get_bd_intf_pins xadc_wiz_1/Vaux8] [get_bd_intf_ports Vaux8] + + #ethernet + + connect_bd_intf_net -intf_net gmii_to_rgmii_eth2_eth2_mdio [get_bd_intf_ports eth2_mdio] [get_bd_intf_pins gmii_to_rgmii_eth2/MDIO_PHY] + connect_bd_intf_net -intf_net gmii_to_rgmii_eth2_eth2_rgmii [get_bd_intf_ports eth2_rgmii] [get_bd_intf_pins gmii_to_rgmii_eth2/RGMII] + connect_bd_intf_net -intf_net sys_ps7_GMII_ETHERNET_1 [get_bd_intf_pins gmii_to_rgmii_eth2/GMII] [get_bd_intf_pins sys_ps7/GMII_ETHERNET_1] + connect_bd_intf_net -intf_net sys_ps7_MDIO_ETHERNET_1 [get_bd_intf_pins gmii_to_rgmii_eth2/MDIO_GEM] [get_bd_intf_pins sys_ps7/MDIO_ETHERNET_1] + + connect_bd_net -net sys_200m_clk [get_bd_pins gmii_to_rgmii_eth2/clkin] $sys_200m_clk_source + connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_pins gmii_to_rgmii_eth2/rx_reset] [get_bd_pins gmii_to_rgmii_eth2/tx_reset] [get_bd_pins sys_rstgen/peripheral_reset] + connect_bd_net -net [get_bd_nets sys_100m_resetn] [get_bd_ports eth2_phy_rst_n] [get_bd_pins sys_rstgen/peripheral_aresetn] + + # interconnect (cpu) + + connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_mc_current_monitor_1/s_axi] +# connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_mc_speed_1/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_current_monitor_2_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_mc_current_monitor_2/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_current_monitor_1_dma/s_axi] +# connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_speed_detector_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins xadc_wiz_1/s_axi_lite] + + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source + + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source + + #inteconnects (current monitor 1) + + connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_current_monitor_1/s_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mc_current_monitor_1/s_axi_aresetn] $sys_100m_resetn_source + + connect_bd_net -net sys_100m_clk [get_bd_pins axi_current_monitor_1_dma/s_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_current_monitor_1_dma/s_axi_aresetn] $sys_100m_resetn_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_current_monitor_1_dma/m_dest_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_current_monitor_1_dma/m_dest_axi_aresetn] $sys_100m_resetn_source + + connect_bd_intf_net -intf_net axi_current_monitor_1_dma [get_bd_intf_pins axi_current_monitor_1_dma/m_dest_axi] [get_bd_intf_pins sys_ps7/S_AXI_HP1] + + #interconnect (current monitor 2) + + connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_current_monitor_2/s_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mc_current_monitor_2/s_axi_aresetn] $sys_100m_resetn_source + + connect_bd_net -net sys_100m_clk [get_bd_pins axi_current_monitor_2_dma/s_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_current_monitor_2_dma/s_axi_aresetn] $sys_100m_resetn_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_current_monitor_2_dma/m_dest_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_current_monitor_2_dma/m_dest_axi_aresetn] $sys_100m_resetn_source + + connect_bd_intf_net -intf_net axi_current_monitor_2_dma [get_bd_intf_pins axi_current_monitor_2_dma/m_dest_axi] [get_bd_intf_pins sys_ps7/S_AXI_HP2] + + # interconnect (speed detector) + +# connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_speed_1/s_axi_aclk] $sys_100m_clk_source +# connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mc_speed_1/s_axi_aresetn] $sys_100m_resetn_source + +# connect_bd_net -net sys_100m_clk [get_bd_pins axi_speed_detector_dma/m_dest_axi_aclk] $sys_100m_clk_source +# connect_bd_net -net sys_100m_resetn [get_bd_pins axi_speed_detector_dma/s_axi_aresetn] $sys_100m_resetn_source +# connect_bd_net -net sys_100m_clk [get_bd_pins axi_speed_detector_dma/s_axi_aclk] $sys_100m_clk_source +# connect_bd_net -net sys_100m_resetn [get_bd_pins axi_speed_detector_dma/m_dest_axi_aresetn] $sys_100m_resetn_source + +# connect_bd_intf_net -intf_net axi_speed_detector_dma [get_bd_intf_pins axi_speed_detector_dma/m_dest_axi] [get_bd_intf_pins sys_ps7/S_AXI_HP3] + + # interconnect (dmas) + + connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK] $sys_100m_clk_source + + # address map + + create_bd_addr_seg -range 0x10000 -offset 0x40400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_current_monitor_1_dma/s_axi/axi_lite] SEG_data_c_m_1_dma +# create_bd_addr_seg -range 0x10000 -offset 0x40410000 $sys_addr_cntrl_space [get_bd_addr_segs axi_speed_detector_dma/s_axi/axi_lite] SEG_data_s_d_dma + create_bd_addr_seg -range 0x10000 -offset 0x40430000 $sys_addr_cntrl_space [get_bd_addr_segs axi_current_monitor_2_dma/s_axi/axi_lite] SEG_data_c_m_2_dma + create_bd_addr_seg -range 0x10000 -offset 0x40500000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_current_monitor_1/s_axi/axi_lite] SEG_data_c_m_1 +# create_bd_addr_seg -range 0x10000 -offset 0x40510000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_speed_1/s_axi/axi_lite] SEG_data_s_d + create_bd_addr_seg -range 0x10000 -offset 0x40530000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_current_monitor_2/s_axi/axi_lite] SEG_data_c_m_2 + create_bd_addr_seg -range 0x10000 -offset 0x43200000 $sys_addr_cntrl_space [get_bd_addr_segs xadc_wiz_1/s_axi_lite/Reg] SEG_data_xadc + + create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_current_monitor_1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm + create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_current_monitor_2_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm +# create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_speed_detector_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm diff --git a/projects/motcon2_fmc/zed/system_bd.tcl b/projects/motcon2_fmc/zed/system_bd.tcl new file mode 100644 index 000000000..139113832 --- /dev/null +++ b/projects/motcon2_fmc/zed/system_bd.tcl @@ -0,0 +1,4 @@ + + source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl + source ../common/motcon2_fmc_bd.tcl + diff --git a/projects/motcon2_fmc/zed/system_constr.xdc b/projects/motcon2_fmc/zed/system_constr.xdc new file mode 100644 index 000000000..06fda41cc --- /dev/null +++ b/projects/motcon2_fmc/zed/system_constr.xdc @@ -0,0 +1,92 @@ +# Motor Control + +#set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports gpio_bd[27]] ; ## XADC-GIO0 +#set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[28]] ; ## XADC-GIO1 +#set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[29]] ; ## XADC-GIO2 +#set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS33} [get_ports gpio_bd[30]] ; ## XADC-GIO3 + +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS25} [get_ports {position_i[0]}] +set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS25} [get_ports {position_i[1]}] +set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS25} [get_ports {position_i[2]}] + +#set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS25} [get_ports {position_m2_i[0]}] ;#M2_SENSOR_A +#set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS25} [get_ports {position_m2_i[1]}] ;#M2_SENSOR_B +#set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS25} [get_ports {position_m2_i[2]}] ;#M2_SENSOR_C + +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports fmc_m1_en_o] +#set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports pwm_m1_ah_o] +#set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS25} [get_ports pwm_m1_al_o] +#set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports pwm_m1_bh_o] +#set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports pwm_m1_bl_o] +#set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports pwm_m1_ch_o] +#set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports pwm_m1_cl_o] +#set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports pwm_m1_dh_o] +#set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports pwm_m1_dl_o] + +set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports fmc_m2_en_o] +#set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS25} [get_ports pwm_m2_ah_o] +#set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS25} [get_ports pwm_m2_al_o] +#set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS25} [get_ports pwm_m2_bh_o] +#set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS25} [get_ports pwm_m2_bl_o] +#set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports pwm_m2_ch_o] +#set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports pwm_m2_cl_o] +#set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25} [get_ports pwm_m2_dh_o] +#set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS25} [get_ports pwm_m2_dl_o] + +set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports adc_clk_o] +set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports adc_m1_vbus_dat_i] +set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25} [get_ports adc_m2_vbus_dat_i] +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports adc_m1_ia_dat_i] +set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports adc_m1_ib_dat_i] +set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS25} [get_ports adc_m2_ia_dat_i] +set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS25} [get_ports adc_m2_ib_dat_i] + +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25} [get_ports {gpo_o[0]}] +set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS25} [get_ports {gpo_o[1]}] +set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS25} [get_ports {gpo_o[2]}] +set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS25} [get_ports {gpo_o[3]}] + +#set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS25} [get_ports {gpi_i[0]}] +#set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS25} [get_ports {gpi_i[1]}] + +#set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[0]}] +#set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[1]}] +#set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[2]}] +#set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[3]}] + +set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS25} [get_ports vauxn0] +set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS25} [get_ports vauxn8] +set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS25} [get_ports vauxp0] +set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS25} [get_ports vauxp8] +set_property -dict {PACKAGE_PIN M12 IOSTANDARD LVCMOS25} [get_ports vn_in] +set_property -dict {PACKAGE_PIN L11 IOSTANDARD LVCMOS25} [get_ports vp_in] + +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25} [get_ports eth2_mdio_mdc] +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports eth2_mdio_io] +set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS25} [get_ports eth2_phy_rst_n] +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_rxc] +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_rx_ctl] +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[0]}] +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[1]}] +set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[2]}] +set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[3]}] +set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_txc] +set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_tx_ctl] +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[0]}] +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[1]}] +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[2]}] +set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[3]}] + +#set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_rxc] +#set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_rx_ctl] +#set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[0]}] +#set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[1]}] +#set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[2]}] +#set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[3]}] + +#set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_txc] +#set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_tx_ctl] +#set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[0]}] +#set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[1]}] +#set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[2]}] +#set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[3]}] diff --git a/projects/motcon2_fmc/zed/system_project.tcl b/projects/motcon2_fmc/zed/system_project.tcl new file mode 100644 index 000000000..4eaaf96de --- /dev/null +++ b/projects/motcon2_fmc/zed/system_project.tcl @@ -0,0 +1,12 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl + +adi_project_create motcon2_fmc_zed +adi_project_files motcon2_fmc_zed [list \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ] + +adi_project_run motcon2_fmc_zed diff --git a/projects/motcon2_fmc/zed/system_top.v b/projects/motcon2_fmc/zed/system_top.v new file mode 100644 index 000000000..ab337a8c5 --- /dev/null +++ b/projects/motcon2_fmc/zed/system_top.v @@ -0,0 +1,347 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2015(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + DDR_addr, + DDR_ba, + DDR_cas_n, + DDR_ck_n, + DDR_ck_p, + DDR_cke, + DDR_cs_n, + DDR_dm, + DDR_dq, + DDR_dqs_n, + DDR_dqs_p, + DDR_odt, + DDR_ras_n, + DDR_reset_n, + DDR_we_n, + + eth2_rgmii_rd, + eth2_rgmii_rx_ctl, + eth2_rgmii_rxc, + eth2_rgmii_td, + eth2_rgmii_tx_ctl, + eth2_rgmii_txc, + eth2_mdio_io, + eth2_mdio_mdc, + eth2_phy_rst_n, + + FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp, + FIXED_IO_mio, + FIXED_IO_ps_clk, + FIXED_IO_ps_porb, + FIXED_IO_ps_srstb, + + gpio_bd, + + hdmi_out_clk, + hdmi_vsync, + hdmi_hsync, + hdmi_data_e, + hdmi_data, + + adc_clk_o, + adc_m1_ia_dat_i, + adc_m1_ib_dat_i, + adc_m1_vbus_dat_i, + fmc_m1_en_o, + fmc_m2_en_o, + adc_m2_ia_dat_i, + adc_m2_ib_dat_i, + adc_m2_vbus_dat_i, + gpo_o, + position_i, + /*pwm_ah_o, + pwm_al_o, + pwm_bh_o, + pwm_bl_o, + pwm_ch_o, + pwm_cl_o,*/ + + vauxn0, + vauxn8, + vauxp0, + vauxp8, + vn_in, + vp_in, + //muxaddr_out, + + i2s_mclk, + i2s_bclk, + i2s_lrclk, + i2s_sdata_out, + i2s_sdata_in, + + spdif, + + iic_scl, + iic_sda, + iic_mux_scl, + iic_mux_sda, + + otg_vbusoc); + + inout [14:0] DDR_addr; + inout [ 2:0] DDR_ba; + inout DDR_cas_n; + inout DDR_ck_n; + inout DDR_ck_p; + inout DDR_cke; + inout DDR_cs_n; + inout [ 3:0] DDR_dm; + inout [31:0] DDR_dq; + inout [ 3:0] DDR_dqs_n; + inout [ 3:0] DDR_dqs_p; + inout DDR_odt; + inout DDR_ras_n; + inout DDR_reset_n; + inout DDR_we_n; + + input [3:0] eth2_rgmii_rd; + input eth2_rgmii_rx_ctl; + input eth2_rgmii_rxc; + output [3:0] eth2_rgmii_td; + output eth2_rgmii_tx_ctl; + output eth2_rgmii_txc; + inout eth2_mdio_io; + output eth2_mdio_mdc; + output eth2_phy_rst_n; + + inout FIXED_IO_ddr_vrn; + inout FIXED_IO_ddr_vrp; + inout [53:0] FIXED_IO_mio; + inout FIXED_IO_ps_clk; + inout FIXED_IO_ps_porb; + inout FIXED_IO_ps_srstb; + + inout [31:0] gpio_bd; + + output hdmi_out_clk; + output hdmi_vsync; + output hdmi_hsync; + output hdmi_data_e; + output [15:0] hdmi_data; + + output adc_clk_o; + output fmc_m1_en_o; + input adc_m1_ia_dat_i; + input adc_m1_ib_dat_i; + input adc_m1_vbus_dat_i; + output fmc_m2_en_o; + input adc_m2_ia_dat_i; + input adc_m2_ib_dat_i; + input adc_m2_vbus_dat_i; + output [3:0] gpo_o; + input [2:0] position_i; + /* output pwm_ah_o; + output pwm_al_o; + output pwm_bh_o; + output pwm_bl_o; + output pwm_ch_o; + output pwm_cl_o;*/ + + input vauxn0; + input vauxn8; + input vauxp0; + input vauxp8; + input vn_in; + input vp_in; + //output [3:0] muxaddr_out; + + output spdif; + + output i2s_mclk; + output i2s_bclk; + output i2s_lrclk; + output i2s_sdata_out; + input i2s_sdata_in; + + + inout iic_scl; + inout iic_sda; + inout [ 1:0] iic_mux_scl; + inout [ 1:0] iic_mux_sda; + + input otg_vbusoc; + + // internal signals + + wire [31:0] gpio_i; + wire [31:0] gpio_o; + wire [31:0] gpio_t; + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; + wire [15:0] ps_intrs; + + // instantiations + + ad_iobuf #( + .DATA_WIDTH(32)) + i_gpio_bd ( + .dt(gpio_t), + .di(gpio_o), + .do(gpio_i), + .dio(gpio_bd)); + + ad_iobuf #( + .DATA_WIDTH(2)) + i_iic_mux_scl ( + .dt({iic_mux_scl_t_s, iic_mux_scl_t_s}), + .di(iic_mux_scl_o_s), + .do(iic_mux_scl_i_s), + .dio(iic_mux_scl)); + + ad_iobuf #( + .DATA_WIDTH(2)) + i_iic_mux_sda ( + .dt({iic_mux_sda_t_s, iic_mux_sda_t_s}), + .di(iic_mux_sda_o_s), + .do(iic_mux_sda_i_s), + .dio(iic_mux_sda)); + + system_wrapper i_system_wrapper ( + .DDR_addr (DDR_addr), + .DDR_ba (DDR_ba), + .DDR_cas_n (DDR_cas_n), + .DDR_ck_n (DDR_ck_n), + .DDR_ck_p (DDR_ck_p), + .DDR_cke (DDR_cke), + .DDR_cs_n (DDR_cs_n), + .DDR_dm (DDR_dm), + .DDR_dq (DDR_dq), + .DDR_dqs_n (DDR_dqs_n), + .DDR_dqs_p (DDR_dqs_p), + .DDR_odt (DDR_odt), + .DDR_ras_n (DDR_ras_n), + .DDR_reset_n (DDR_reset_n), + .DDR_we_n (DDR_we_n), + .FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn), + .FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp), + .FIXED_IO_mio (FIXED_IO_mio), + .FIXED_IO_ps_clk (FIXED_IO_ps_clk), + .FIXED_IO_ps_porb (FIXED_IO_ps_porb), + .FIXED_IO_ps_srstb (FIXED_IO_ps_srstb), + .GPIO_I (gpio_i), + .GPIO_O (gpio_o), + .GPIO_T (gpio_t), + + .eth2_rgmii_rd(eth2_rgmii_rd), + .eth2_rgmii_rx_ctl(eth2_rgmii_rx_ctl), + .eth2_rgmii_rxc(eth2_rgmii_rxc), + .eth2_rgmii_td(eth2_rgmii_td), + .eth2_rgmii_tx_ctl(eth2_rgmii_tx_ctl), + .eth2_rgmii_txc(eth2_rgmii_txc), + .eth2_phy_rst_n(eth2_phy_rst_n), + .eth2_mdio_mdio_io(eth2_mdio_io), + .eth2_mdio_mdc(eth2_mdio_mdc), + + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .adc_clk_o(adc_clk_o), + .fmc_m1_en_o(fmc_m1_en_o), + .adc_m1_ia_dat_i(adc_m1_ia_dat_i), + .adc_m1_ib_dat_i(adc_m1_ib_dat_i), + .adc_m1_vbus_dat_i(adc_m1_vbus_dat_i), + .fmc_m2_en_o(fmc_m2_en_o), + .adc_m2_ia_dat_i(adc_m2_ia_dat_i), + .adc_m2_ib_dat_i(adc_m2_ib_dat_i), + .adc_m2_vbus_dat_i(adc_m2_vbus_dat_i), + .gpo_o(gpo_o), + .position_i(position_i), + //.pwm_ah_o(pwm_ah_o), + //.pwm_al_o(pwm_al_o), + //.pwm_bh_o(pwm_bh_o), + //.pwm_bl_o(pwm_bl_o), + //.pwm_ch_o(pwm_ch_o), + //.pwm_cl_o(pwm_cl_o), + .Vaux0_v_n(vauxn0), + .Vaux0_v_p(vauxp0), + .Vaux8_v_n(vauxn8), + .Vaux8_v_p(vauxp8), + .Vp_Vn_v_n(vn_in), + .Vp_Vn_v_p(vp_in), + //.muxaddr_out(muxaddr_out), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_I (iic_mux_scl_i_s), + .iic_mux_scl_O (iic_mux_scl_o_s), + .iic_mux_scl_T (iic_mux_scl_t_s), + .iic_mux_sda_I (iic_mux_sda_i_s), + .iic_mux_sda_O (iic_mux_sda_o_s), + .iic_mux_sda_T (iic_mux_sda_t_s), + .ps_intr_10 (ps_intrs[10]), + .ps_intr_11 (ps_intrs[11]), + .ps_intr_12 (ps_intrs[12]), + .ps_intr_13 (ps_intrs[13]), + .ps_intr_4 (ps_intrs[4]), + .ps_intr_5 (ps_intrs[5]), + .ps_intr_6 (ps_intrs[6]), + .ps_intr_7 (ps_intrs[7]), + .ps_intr_8 (ps_intrs[8]), + .ps_intr_9 (ps_intrs[9]), + .iic_fmc_intr(ps_intrs[11]), + .motcon2_c_m_1_irq(ps_intrs[13]), + .motcon2_c_m_2_irq(ps_intrs[9]), + .motcon2_s_d_irq(ps_intrs[12]), + //.motcon2_ctrl_irq(ps_intrs[10]), + .otg_vbusoc (otg_vbusoc), + .spdif (spdif)); + +endmodule + +// *************************************************************************** +// ***************************************************************************