From f6f7cff8a0bd11c19cd101cf2f66c09b5a1c40ea Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 12 Jul 2017 12:12:30 +0300
Subject: [PATCH] util_clkdiv: Added altera version

---
 library/util_clkdiv/util_clkdiv_alt.v  | 82 ++++++++++++++++++++++++++
 library/util_clkdiv/util_clkdiv_hw.tcl | 25 ++++++++
 2 files changed, 107 insertions(+)
 create mode 100644 library/util_clkdiv/util_clkdiv_alt.v
 create mode 100644 library/util_clkdiv/util_clkdiv_hw.tcl

diff --git a/library/util_clkdiv/util_clkdiv_alt.v b/library/util_clkdiv/util_clkdiv_alt.v
new file mode 100644
index 000000000..3c79f1fce
--- /dev/null
+++ b/library/util_clkdiv/util_clkdiv_alt.v
@@ -0,0 +1,82 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2014(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+// Divides the input clock to SEL_0_DIV if clk_sel is 0 or SEL_1_DIV if
+// clk_sel is 1. Provides a glitch free output clock
+// IP uses BUFR/BUFGCE_DIV and BUFGMUX_CTRL primitives
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module util_clkdiv_alt #(
+  parameter SIM_DEVICE = "CYCLONE5",
+  parameter CLOCK_TYPE = "Global Clock") (
+
+  input   clk,
+  input   reset,
+  output  clk_out,
+  output  reset_out
+ );
+
+reg enable;
+reg reset_d1;
+
+assign reset_out = reset | reset_d1;
+
+always @(posedge clk) begin
+  reset_d1 <= reset;
+end
+
+always @(posedge clk) begin
+  enable <= ~enable;
+end
+  
+generate if (SIM_DEVICE == "CYCLONE5") begin
+	cyclonev_clkena #(
+		.clock_type ("Global Clock"),
+		.ena_register_mode ("falling edge"),
+		.lpm_type ("cyclonev_clkena")
+  ) clock_divider_by_2 ( 
+	.ena(enable),
+	.enaout(),
+	.inclk(clk),
+//	.clkselect (2'b0),
+	.outclk(clk_out));
+
+end endgenerate
+
+endmodule  // util_clkdiv_alt
diff --git a/library/util_clkdiv/util_clkdiv_hw.tcl b/library/util_clkdiv/util_clkdiv_hw.tcl
new file mode 100644
index 000000000..310801727
--- /dev/null
+++ b/library/util_clkdiv/util_clkdiv_hw.tcl
@@ -0,0 +1,25 @@
+
+package require -exact qsys 13.0
+source ../scripts/adi_env.tcl
+source ../scripts/adi_ip_alt.tcl
+
+
+set_module_property NAME util_clkdiv
+set_module_property DESCRIPTION "Clock Division Utility"
+set_module_property VERSION 1.0
+set_module_property GROUP "Analog Devices"
+set_module_property DISPLAY_NAME util_clkdiv
+
+# files
+
+add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
+set_fileset_property quartus_synth TOP_LEVEL util_clkdiv_alt
+add_fileset_file util_clkdiv_alt.v       VERILOG PATH util_clkdiv_alt.v TOP_LEVEL_FILE
+
+# defaults
+
+ad_alt_intf clock   clk             input   1
+ad_alt_intf reset   reset           input 1 if_clk
+ad_alt_intf clock   clk_out         output  1
+ad_alt_intf reset   reset_out       output 1 if_clk_out
+