From f73ed741c94d72c584807401f48f79d3500ac7c4 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Thu, 17 Dec 2020 09:48:21 +0000 Subject: [PATCH] fmcadc5: Connect link clock to second JESD link layer --- projects/fmcadc5/common/fmcadc5_bd.tcl | 1 + 1 file changed, 1 insertion(+) diff --git a/projects/fmcadc5/common/fmcadc5_bd.tcl b/projects/fmcadc5/common/fmcadc5_bd.tcl index 875592a1f..af39ad805 100644 --- a/projects/fmcadc5/common/fmcadc5_bd.tcl +++ b/projects/fmcadc5/common/fmcadc5_bd.tcl @@ -104,6 +104,7 @@ delete_bd_objs [get_bd_cells axi_ad9625_1_jesd_rstgen] ad_xcvrpll util_fmcadc5_0_xcvr/rx_out_clk_0 util_fmcadc5_1_xcvr/rx_clk_* ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 axi_ad9625_1_jesd/device_clk +ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 axi_ad9625_1_jesd/link_clk ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 axi_ad9625_0_core/rx_clk ad_connect axi_ad9625_0_jesd/rx_sof axi_ad9625_0_core/rx_sof ad_connect axi_ad9625_0_jesd/rx_data_tdata axi_ad9625_0_core/rx_data