From f752f0c9d7dc5a6bc5332c0f5a014a404f261084 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Wed, 26 Oct 2016 13:13:49 -0400 Subject: [PATCH] a10soc- xcvr updates --- projects/adrv9371x/a10soc/system_top.v | 178 +- projects/adrv9371x/common/adrv9371x_qsys.tcl | 1119 ++++--------- projects/common/a10soc/a10soc_system_qsys.tcl | 1491 +++-------------- 3 files changed, 635 insertions(+), 2153 deletions(-) diff --git a/projects/adrv9371x/a10soc/system_top.v b/projects/adrv9371x/a10soc/system_top.v index 1a350c207..c56298487 100644 --- a/projects/adrv9371x/a10soc/system_top.v +++ b/projects/adrv9371x/a10soc/system_top.v @@ -140,6 +140,9 @@ module system_top ( // internal signals + wire sys_hps_resetn; + wire sys_resetn_s; + wire [ 7:0] spi_csn; wire [ 31:0] gpio_i; wire [ 31:0] gpio_o; @@ -160,95 +163,112 @@ module system_top ( // gpio (max-v-u21) - assign gpio_i[15:8] = gpio_o[15:8]; - assign gpio_i[ 7:0] = gpio_bd_i; + assign gpio_i[15:12] = gpio_o[15:12]; + assign gpio_i[11: 4] = gpio_bd_i; + assign gpio_i[ 3: 0] = gpio_o[3:0]; assign gpio_bd_o = gpio_o[3:0]; + // spi + + assign spi_csn_ad9528 = spi_csn[1]; + assign spi_csn_ad9371 = spi_csn[0]; + assign sys_resetn_s = sys_resetn & sys_hps_resetn; + // instantiations system_bd i_system_bd ( - .ad9371_gpio_export (ad9371_gpio), - .hps_ddr_mem_ck (hps_ddr_clk_p), - .hps_ddr_mem_ck_n (hps_ddr_clk_n), - .hps_ddr_mem_a (hsp_ddr_a), - .hps_ddr_mem_act_n (hps_ddr_act_n), - .hps_ddr_mem_ba (hps_ddr_ba), - .hps_ddr_mem_bg (hps_ddr_bg), - .hps_ddr_mem_cke (hps_ddr_cke), - .hps_ddr_mem_cs_n (hps_ddr_cs_n), - .hps_ddr_mem_odt (hps_ddr_odt), - .hps_ddr_mem_reset_n (hps_ddr_reset_n), - .hps_ddr_mem_par (hps_ddr_par), - .hps_ddr_mem_alert_n (hps_ddr_alert_n), - .hps_ddr_mem_dqs (hps_ddr_dqs_p), - .hps_ddr_mem_dqs_n (hps_ddr_dqs_n), - .hps_ddr_mem_dq (hps_ddr_dq), - .hps_ddr_mem_dbi_n (hps_ddr_dbi_n), - .hps_ddr_oct_oct_rzqin (hps_ddr_rzq), - .hps_ddr_ref_clk_clk (hps_ddr_ref_clk), - .hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk), - .hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]), - .hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]), - .hps_io_hps_io_phery_emac0_TXD2 (hps_eth_txd[2]), - .hps_io_hps_io_phery_emac0_TXD3 (hps_eth_txd[3]), - .hps_io_hps_io_phery_emac0_RX_CTL (hps_eth_rxctl), - .hps_io_hps_io_phery_emac0_TX_CTL (hps_eth_txctl), - .hps_io_hps_io_phery_emac0_RX_CLK (hps_eth_rxclk), - .hps_io_hps_io_phery_emac0_RXD0 (hps_eth_rxd[0]), - .hps_io_hps_io_phery_emac0_RXD1 (hps_eth_rxd[1]), - .hps_io_hps_io_phery_emac0_RXD2 (hps_eth_rxd[2]), - .hps_io_hps_io_phery_emac0_RXD3 (hps_eth_rxd[3]), - .hps_io_hps_io_phery_emac0_MDIO (hps_eth_mdio), - .hps_io_hps_io_phery_emac0_MDC (hps_eth_mdc), - .hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_cmd), - .hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_d[0]), - .hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_d[1]), - .hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_d[2]), - .hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_d[3]), - .hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_d[4]), - .hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_d[5]), - .hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_d[6]), - .hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_d[7]), - .hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_clk), - .hps_io_hps_io_phery_usb0_DATA0 (hps_usb_d[0]), - .hps_io_hps_io_phery_usb0_DATA1 (hps_usb_d[1]), - .hps_io_hps_io_phery_usb0_DATA2 (hps_usb_d[2]), - .hps_io_hps_io_phery_usb0_DATA3 (hps_usb_d[3]), - .hps_io_hps_io_phery_usb0_DATA4 (hps_usb_d[4]), - .hps_io_hps_io_phery_usb0_DATA5 (hps_usb_d[5]), - .hps_io_hps_io_phery_usb0_DATA6 (hps_usb_d[6]), - .hps_io_hps_io_phery_usb0_DATA7 (hps_usb_d[7]), - .hps_io_hps_io_phery_usb0_CLK (hps_usb_clk), - .hps_io_hps_io_phery_usb0_STP (hps_usb_stp), - .hps_io_hps_io_phery_usb0_DIR (hps_usb_dir), - .hps_io_hps_io_phery_usb0_NXT (hps_usb_nxt), - .hps_io_hps_io_phery_uart1_RX (hps_uart_rx), - .hps_io_hps_io_phery_uart1_TX (hps_uart_tx), - .hps_io_hps_io_phery_i2c1_SDA (hps_i2c_sda), - .hps_io_hps_io_phery_i2c1_SCL (hps_i2c_scl), - .hps_io_hps_io_gpio_gpio1_io5 (hps_gpio[0]), - .hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]), - .hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]), - .hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]), - .xcvr_ref_clk_clk (ref_clk1), - .rx_data_rx_serial_data (rx_data[1:0]), - .rx_os_data_rx_serial_data (rx_data[3:2]), - .rx_os_sync_rx_sync (rx_os_sync), - .rx_os_sysref_rx_ext_sysref_in (sysref), - .rx_sync_rx_sync (rx_sync), - .rx_sysref_rx_ext_sysref_in (sysref), + .avl_ad9371_gpio_export (ad9371_gpio), + .rx_data_0_rx_serial_data (rx_data[0]), + .rx_data_1_rx_serial_data (rx_data[1]), + .rx_data_2_rx_serial_data (rx_data[2]), + .rx_data_3_rx_serial_data (rx_data[3]), + .rx_os_ref_clk_clk (ref_clk1), + .rx_os_sync_export (rx_os_sync), + .rx_os_sysref_export (sysref), + .rx_ref_clk_clk (ref_clk1), + .rx_sync_export (rx_sync), + .rx_sysref_export (sysref), .sys_clk_clk (sys_clk), - .sys_rst_reset_n (sys_resetn), - .tx_data_tx_serial_data ({tx_data[0],tx_data[3],tx_data[2],tx_data[1]}), - .tx_sync_tx_sync (tx_sync), - .tx_sysref_tx_ext_sysref_in (sysref), - .gpio_i_export (gpio_i), - .gpio_o_export (gpio_o), + .sys_gpio_in_export (gpio_i), + .sys_gpio_out_export (gpio_o), + .sys_hps_ddr_mem_ck (hps_ddr_clk_p), + .sys_hps_ddr_mem_ck_n (hps_ddr_clk_n), + .sys_hps_ddr_mem_a (hsp_ddr_a), + .sys_hps_ddr_mem_act_n (hps_ddr_act_n), + .sys_hps_ddr_mem_ba (hps_ddr_ba), + .sys_hps_ddr_mem_bg (hps_ddr_bg), + .sys_hps_ddr_mem_cke (hps_ddr_cke), + .sys_hps_ddr_mem_cs_n (hps_ddr_cs_n), + .sys_hps_ddr_mem_odt (hps_ddr_odt), + .sys_hps_ddr_mem_reset_n (hps_ddr_reset_n), + .sys_hps_ddr_mem_par (hps_ddr_par), + .sys_hps_ddr_mem_alert_n (hps_ddr_alert_n), + .sys_hps_ddr_mem_dqs (hps_ddr_dqs_p), + .sys_hps_ddr_mem_dqs_n (hps_ddr_dqs_n), + .sys_hps_ddr_mem_dq (hps_ddr_dq), + .sys_hps_ddr_mem_dbi_n (hps_ddr_dbi_n), + .sys_hps_ddr_oct_oct_rzqin (hps_ddr_rzq), + .sys_hps_ddr_ref_clk_clk (hps_ddr_ref_clk), + .sys_hps_ddr_rstn_reset_n (sys_resetn), + .sys_hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk), + .sys_hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]), + .sys_hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]), + .sys_hps_io_hps_io_phery_emac0_TXD2 (hps_eth_txd[2]), + .sys_hps_io_hps_io_phery_emac0_TXD3 (hps_eth_txd[3]), + .sys_hps_io_hps_io_phery_emac0_RX_CTL (hps_eth_rxctl), + .sys_hps_io_hps_io_phery_emac0_TX_CTL (hps_eth_txctl), + .sys_hps_io_hps_io_phery_emac0_RX_CLK (hps_eth_rxclk), + .sys_hps_io_hps_io_phery_emac0_RXD0 (hps_eth_rxd[0]), + .sys_hps_io_hps_io_phery_emac0_RXD1 (hps_eth_rxd[1]), + .sys_hps_io_hps_io_phery_emac0_RXD2 (hps_eth_rxd[2]), + .sys_hps_io_hps_io_phery_emac0_RXD3 (hps_eth_rxd[3]), + .sys_hps_io_hps_io_phery_emac0_MDIO (hps_eth_mdio), + .sys_hps_io_hps_io_phery_emac0_MDC (hps_eth_mdc), + .sys_hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_cmd), + .sys_hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_d[0]), + .sys_hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_d[1]), + .sys_hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_d[2]), + .sys_hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_d[3]), + .sys_hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_d[4]), + .sys_hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_d[5]), + .sys_hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_d[6]), + .sys_hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_d[7]), + .sys_hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_clk), + .sys_hps_io_hps_io_phery_usb0_DATA0 (hps_usb_d[0]), + .sys_hps_io_hps_io_phery_usb0_DATA1 (hps_usb_d[1]), + .sys_hps_io_hps_io_phery_usb0_DATA2 (hps_usb_d[2]), + .sys_hps_io_hps_io_phery_usb0_DATA3 (hps_usb_d[3]), + .sys_hps_io_hps_io_phery_usb0_DATA4 (hps_usb_d[4]), + .sys_hps_io_hps_io_phery_usb0_DATA5 (hps_usb_d[5]), + .sys_hps_io_hps_io_phery_usb0_DATA6 (hps_usb_d[6]), + .sys_hps_io_hps_io_phery_usb0_DATA7 (hps_usb_d[7]), + .sys_hps_io_hps_io_phery_usb0_CLK (hps_usb_clk), + .sys_hps_io_hps_io_phery_usb0_STP (hps_usb_stp), + .sys_hps_io_hps_io_phery_usb0_DIR (hps_usb_dir), + .sys_hps_io_hps_io_phery_usb0_NXT (hps_usb_nxt), + .sys_hps_io_hps_io_phery_uart1_RX (hps_uart_rx), + .sys_hps_io_hps_io_phery_uart1_TX (hps_uart_tx), + .sys_hps_io_hps_io_phery_i2c1_SDA (hps_i2c_sda), + .sys_hps_io_hps_io_phery_i2c1_SCL (hps_i2c_scl), + .sys_hps_io_hps_io_gpio_gpio1_io5 (hps_gpio[0]), + .sys_hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]), + .sys_hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]), + .sys_hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]), + .sys_hps_out_rstn_reset_n (sys_hps_resetn), + .sys_hps_rstn_reset_n (sys_resetn), + .sys_rstn_reset_n (sys_resetn_s), .sys_spi_MISO (spi_miso), .sys_spi_MOSI (spi_mosi), .sys_spi_SCLK (spi_clk), - .sys_spi_SS_n ({spi_csn_ad9528, spi_csn_ad9371})); + .sys_spi_SS_n (spi_csn), + .tx_data_0_tx_serial_data (tx_data[0]), + .tx_data_1_tx_serial_data (tx_data[1]), + .tx_data_2_tx_serial_data (tx_data[2]), + .tx_data_3_tx_serial_data (tx_data[3]), + .tx_ref_clk_clk (ref_clk1), + .tx_sync_export (tx_sync), + .tx_sysref_export (sysref)); endmodule diff --git a/projects/adrv9371x/common/adrv9371x_qsys.tcl b/projects/adrv9371x/common/adrv9371x_qsys.tcl index 2913a0b8b..01df30849 100644 --- a/projects/adrv9371x/common/adrv9371x_qsys.tcl +++ b/projects/adrv9371x/common/adrv9371x_qsys.tcl @@ -1,848 +1,361 @@ -# overwrite default settings -set_instance_parameter_value sys_spi {clockPhase} {1} -set_instance_parameter_value sys_spi {clockPolarity} {1} -set_instance_parameter_value sys_spi {targetClockRate} {5000000.0} +# ad9371_tx-xcvr -# Add adrv9371x +add_instance avl_ad9371_tx_xcvr avl_adxcvr 1.0 +set_instance_parameter_value avl_ad9371_tx_xcvr {ID} {0} +set_instance_parameter_value avl_ad9371_tx_xcvr {TX_OR_RX_N} {1} +set_instance_parameter_value avl_ad9371_tx_xcvr {PCS_CONFIG} {JESD_PCS_CFG2} +set_instance_parameter_value avl_ad9371_tx_xcvr {LANE_RATE} {4915.2} +set_instance_parameter_value avl_ad9371_tx_xcvr {PLLCLK_FREQUENCY} {2457.6} +set_instance_parameter_value avl_ad9371_tx_xcvr {REFCLK_FREQUENCY} {122.88} +set_instance_parameter_value avl_ad9371_tx_xcvr {CORECLK_FREQUENCY} {122.88} +set_instance_parameter_value avl_ad9371_tx_xcvr {NUM_OF_LANES} {4} +set_instance_parameter_value avl_ad9371_tx_xcvr {NUM_OF_CONVS} {4} +set_instance_parameter_value avl_ad9371_tx_xcvr {FRM_BCNT} {2} +set_instance_parameter_value avl_ad9371_tx_xcvr {FRM_SCNT} {1} +set_instance_parameter_value avl_ad9371_tx_xcvr {MF_FCNT} {32} +set_instance_parameter_value avl_ad9371_tx_xcvr {HD} {1} +add_connection sys_clk.clk avl_ad9371_tx_xcvr.sys_clk +add_connection sys_clk.clk_reset avl_ad9371_tx_xcvr.sys_resetn +add_interface tx_ref_clk clock sink +set_interface_property tx_ref_clk EXPORT_OF avl_ad9371_tx_xcvr.ref_clk +add_interface tx_data_0 conduit end +set_interface_property tx_data_0 EXPORT_OF avl_ad9371_tx_xcvr.tx_data_0 +add_interface tx_data_1 conduit end +set_interface_property tx_data_1 EXPORT_OF avl_ad9371_tx_xcvr.tx_data_1 +add_interface tx_data_2 conduit end +set_interface_property tx_data_2 EXPORT_OF avl_ad9371_tx_xcvr.tx_data_2 +add_interface tx_data_3 conduit end +set_interface_property tx_data_3 EXPORT_OF avl_ad9371_tx_xcvr.tx_data_3 +add_interface tx_sysref conduit end +set_interface_property tx_sysref EXPORT_OF avl_ad9371_tx_xcvr.sysref +add_interface tx_sync conduit end +set_interface_property tx_sync EXPORT_OF avl_ad9371_tx_xcvr.sync +add_connection avl_ad9371_tx_xcvr.tx_phy_s_0 avl_ad9371_tx_xcvr.tx_ip_s_3 +add_connection avl_ad9371_tx_xcvr.tx_phy_s_1 avl_ad9371_tx_xcvr.tx_ip_s_0 +add_connection avl_ad9371_tx_xcvr.tx_phy_s_2 avl_ad9371_tx_xcvr.tx_ip_s_1 +add_connection avl_ad9371_tx_xcvr.tx_phy_s_3 avl_ad9371_tx_xcvr.tx_ip_s_2 +add_connection avl_ad9371_tx_xcvr.tx_ip_d_3 avl_ad9371_tx_xcvr.tx_phy_d_0 +add_connection avl_ad9371_tx_xcvr.tx_ip_d_0 avl_ad9371_tx_xcvr.tx_phy_d_1 +add_connection avl_ad9371_tx_xcvr.tx_ip_d_1 avl_ad9371_tx_xcvr.tx_phy_d_2 +add_connection avl_ad9371_tx_xcvr.tx_ip_d_2 avl_ad9371_tx_xcvr.tx_phy_d_3 -add_instance xcvr_ref_clk altera_clock_bridge 16.0 -set_instance_parameter_value xcvr_ref_clk {EXPLICIT_CLOCK_RATE} {122880000.0} -set_instance_parameter_value xcvr_ref_clk {NUM_CLOCK_OUTPUTS} {1} +# ad9371_tx-xcvr -add_instance xcvr_pll altera_iopll 16.0 -set_instance_parameter_value xcvr_pll {gui_device_speed_grade} {1} -set_instance_parameter_value xcvr_pll {gui_en_reconf} {1} -set_instance_parameter_value xcvr_pll {gui_en_dps_ports} {0} -set_instance_parameter_value xcvr_pll {gui_pll_mode} {Integer-N PLL} -set_instance_parameter_value xcvr_pll {gui_reference_clock_frequency} {122.88} -set_instance_parameter_value xcvr_pll {gui_fractional_cout} {32} -set_instance_parameter_value xcvr_pll {gui_dsm_out_sel} {1st_order} -set_instance_parameter_value xcvr_pll {gui_use_locked} {0} -set_instance_parameter_value xcvr_pll {gui_en_adv_params} {0} -set_instance_parameter_value xcvr_pll {gui_pll_bandwidth_preset} {Low} -set_instance_parameter_value xcvr_pll {gui_lock_setting} {Low Lock Time} -set_instance_parameter_value xcvr_pll {gui_pll_auto_reset} {0} -set_instance_parameter_value xcvr_pll {gui_en_lvds_ports} {Disabled} -set_instance_parameter_value xcvr_pll {gui_operation_mode} {direct} -set_instance_parameter_value xcvr_pll {gui_feedback_clock} {Global Clock} -set_instance_parameter_value xcvr_pll {gui_clock_to_compensate} {0} -set_instance_parameter_value xcvr_pll {gui_use_NDFB_modes} {0} -set_instance_parameter_value xcvr_pll {gui_refclk_switch} {0} -set_instance_parameter_value xcvr_pll {gui_refclk1_frequency} {100.0} -set_instance_parameter_value xcvr_pll {gui_en_phout_ports} {0} -set_instance_parameter_value xcvr_pll {gui_phout_division} {1} -set_instance_parameter_value xcvr_pll {gui_en_extclkout_ports} {0} -set_instance_parameter_value xcvr_pll {gui_number_of_clocks} {3} -set_instance_parameter_value xcvr_pll {gui_multiply_factor} {6} -set_instance_parameter_value xcvr_pll {gui_divide_factor_n} {1} -set_instance_parameter_value xcvr_pll {gui_frac_multiply_factor} {1.0} -set_instance_parameter_value xcvr_pll {gui_fix_vco_frequency} {0} -set_instance_parameter_value xcvr_pll {gui_fixed_vco_frequency} {600.0} -set_instance_parameter_value xcvr_pll {gui_vco_frequency} {600.0} -set_instance_parameter_value xcvr_pll {gui_enable_output_counter_cascading} {0} -set_instance_parameter_value xcvr_pll {gui_mif_gen_options} {Generate New MIF File} -set_instance_parameter_value xcvr_pll {gui_new_mif_file_path} {~/pll.mif} -set_instance_parameter_value xcvr_pll {gui_existing_mif_file_path} {~/pll.mif} -set_instance_parameter_value xcvr_pll {gui_mif_config_name} {unnamed} -set_instance_parameter_value xcvr_pll {gui_active_clk} {0} -set_instance_parameter_value xcvr_pll {gui_clk_bad} {0} -set_instance_parameter_value xcvr_pll {gui_switchover_mode} {Automatic Switchover} -set_instance_parameter_value xcvr_pll {gui_switchover_delay} {0} -set_instance_parameter_value xcvr_pll {gui_enable_cascade_out} {0} -set_instance_parameter_value xcvr_pll {gui_cascade_outclk_index} {0} -set_instance_parameter_value xcvr_pll {gui_enable_cascade_in} {0} -set_instance_parameter_value xcvr_pll {gui_pll_cascading_mode} {adjpllin} -set_instance_parameter_value xcvr_pll {gui_enable_mif_dps} {0} -set_instance_parameter_value xcvr_pll {gui_dps_cntr} {C0} -set_instance_parameter_value xcvr_pll {gui_dps_num} {1} -set_instance_parameter_value xcvr_pll {gui_dps_dir} {Positive} -set_instance_parameter_value xcvr_pll {gui_extclkout_0_source} {C0} -set_instance_parameter_value xcvr_pll {gui_extclkout_1_source} {C0} -set_instance_parameter_value xcvr_pll {gui_clock_name_global} {0} -set_instance_parameter_value xcvr_pll {gui_clock_name_string0} {tx_dac_clk} -set_instance_parameter_value xcvr_pll {gui_clock_name_string1} {rx_adc_clk} -set_instance_parameter_value xcvr_pll {gui_clock_name_string2} {rx_adc_os_clk} -set_instance_parameter_value xcvr_pll {gui_divide_factor_c0} {6} -set_instance_parameter_value xcvr_pll {gui_divide_factor_c1} {6} -set_instance_parameter_value xcvr_pll {gui_divide_factor_c2} {6} -set_instance_parameter_value xcvr_pll {gui_cascade_counter0} {0} -set_instance_parameter_value xcvr_pll {gui_cascade_counter1} {0} -set_instance_parameter_value xcvr_pll {gui_cascade_counter2} {0} -set_instance_parameter_value xcvr_pll {gui_output_clock_frequency0} {122.88} -set_instance_parameter_value xcvr_pll {gui_output_clock_frequency1} {122.88} -set_instance_parameter_value xcvr_pll {gui_output_clock_frequency2} {122.88} -set_instance_parameter_value xcvr_pll {gui_actual_output_clock_frequency0} {100.0} -set_instance_parameter_value xcvr_pll {gui_actual_output_clock_frequency1} {100.0} -set_instance_parameter_value xcvr_pll {gui_actual_output_clock_frequency2} {100.0} -set_instance_parameter_value xcvr_pll {gui_ps_units0} {ps} -set_instance_parameter_value xcvr_pll {gui_ps_units1} {ps} -set_instance_parameter_value xcvr_pll {gui_ps_units2} {ps} -set_instance_parameter_value xcvr_pll {gui_phase_shift0} {0.0} -set_instance_parameter_value xcvr_pll {gui_phase_shift1} {0.0} -set_instance_parameter_value xcvr_pll {gui_phase_shift2} {0.0} -set_instance_parameter_value xcvr_pll {gui_phase_shift_deg0} {0.0} -set_instance_parameter_value xcvr_pll {gui_phase_shift_deg1} {0.0} -set_instance_parameter_value xcvr_pll {gui_phase_shift_deg2} {0.0} -set_instance_parameter_value xcvr_pll {gui_actual_phase_shift0} {0.0} -set_instance_parameter_value xcvr_pll {gui_actual_phase_shift1} {0.0} -set_instance_parameter_value xcvr_pll {gui_actual_phase_shift2} {0.0} -set_instance_parameter_value xcvr_pll {gui_actual_phase_shift_deg0} {0.0} -set_instance_parameter_value xcvr_pll {gui_actual_phase_shift_deg1} {0.0} -set_instance_parameter_value xcvr_pll {gui_actual_phase_shift_deg2} {0.0} -set_instance_parameter_value xcvr_pll {gui_duty_cycle0} {50.0} -set_instance_parameter_value xcvr_pll {gui_duty_cycle1} {50.0} -set_instance_parameter_value xcvr_pll {gui_duty_cycle2} {50.0} -set_instance_parameter_value xcvr_pll {gui_actual_duty_cycle0} {50.0} -set_instance_parameter_value xcvr_pll {gui_actual_duty_cycle1} {50.0} -set_instance_parameter_value xcvr_pll {gui_actual_duty_cycle2} {50.0} +add_instance axi_ad9371_tx_xcvr axi_adxcvr 1.0 +set_instance_parameter_value axi_ad9371_tx_xcvr {ID} {0} +set_instance_parameter_value axi_ad9371_tx_xcvr {TX_OR_RX_N} {1} +set_instance_parameter_value axi_ad9371_tx_xcvr {NUM_OF_LANES} {4} +add_connection sys_clk.clk axi_ad9371_tx_xcvr.s_axi_clock +add_connection sys_clk.clk_reset axi_ad9371_tx_xcvr.s_axi_reset +add_connection axi_ad9371_tx_xcvr.if_up_rst avl_ad9371_tx_xcvr.rst +add_connection avl_ad9371_tx_xcvr.ready axi_ad9371_tx_xcvr.ready +add_connection axi_ad9371_tx_xcvr.core_pll_locked avl_ad9371_tx_xcvr.core_pll_locked -add_instance xcvr_pll_reconfig altera_pll_reconfig 16.0 -set_instance_parameter_value xcvr_pll_reconfig {ENABLE_MIF} {0} -set_instance_parameter_value xcvr_pll_reconfig {MIF_FILE_NAME} {} -set_instance_parameter_value xcvr_pll_reconfig {ENABLE_BYTEENABLE} {0} +# ad9371_rx-xcvr -add_instance xcvr_tx_rst_cntrl altera_xcvr_reset_control 16.0 -set_instance_parameter_value xcvr_tx_rst_cntrl {CHANNELS} {4} -set_instance_parameter_value xcvr_tx_rst_cntrl {PLLS} {1} -set_instance_parameter_value xcvr_tx_rst_cntrl {SYS_CLK_IN_MHZ} {100} -set_instance_parameter_value xcvr_tx_rst_cntrl {SYNCHRONIZE_RESET} {1} -set_instance_parameter_value xcvr_tx_rst_cntrl {REDUCED_SIM_TIME} {1} -set_instance_parameter_value xcvr_tx_rst_cntrl {gui_split_interfaces} {0} -set_instance_parameter_value xcvr_tx_rst_cntrl {TX_PLL_ENABLE} {1} -set_instance_parameter_value xcvr_tx_rst_cntrl {T_PLL_POWERDOWN} {1000} -set_instance_parameter_value xcvr_tx_rst_cntrl {SYNCHRONIZE_PLL_RESET} {0} -set_instance_parameter_value xcvr_tx_rst_cntrl {TX_ENABLE} {1} -set_instance_parameter_value xcvr_tx_rst_cntrl {TX_PER_CHANNEL} {0} -set_instance_parameter_value xcvr_tx_rst_cntrl {gui_tx_auto_reset} {0} -set_instance_parameter_value xcvr_tx_rst_cntrl {T_TX_ANALOGRESET} {70000} -set_instance_parameter_value xcvr_tx_rst_cntrl {T_TX_DIGITALRESET} {70000} -set_instance_parameter_value xcvr_tx_rst_cntrl {T_PLL_LOCK_HYST} {0} -set_instance_parameter_value xcvr_tx_rst_cntrl {gui_pll_cal_busy} {1} -set_instance_parameter_value xcvr_tx_rst_cntrl {RX_ENABLE} {0} -set_instance_parameter_value xcvr_tx_rst_cntrl {RX_PER_CHANNEL} {0} -set_instance_parameter_value xcvr_tx_rst_cntrl {gui_rx_auto_reset} {0} -set_instance_parameter_value xcvr_tx_rst_cntrl {T_RX_ANALOGRESET} {40} -set_instance_parameter_value xcvr_tx_rst_cntrl {T_RX_DIGITALRESET} {4000} +add_instance avl_ad9371_rx_xcvr avl_adxcvr 1.0 +set_instance_parameter_value avl_ad9371_rx_xcvr {ID} {1} +set_instance_parameter_value avl_ad9371_rx_xcvr {TX_OR_RX_N} {0} +set_instance_parameter_value avl_ad9371_rx_xcvr {PCS_CONFIG} {JESD_PCS_CFG2} +set_instance_parameter_value avl_ad9371_rx_xcvr {LANE_RATE} {4915.2} +set_instance_parameter_value avl_ad9371_rx_xcvr {PLLCLK_FREQUENCY} {2457.6} +set_instance_parameter_value avl_ad9371_rx_xcvr {REFCLK_FREQUENCY} {122.88} +set_instance_parameter_value avl_ad9371_rx_xcvr {CORECLK_FREQUENCY} {122.88} +set_instance_parameter_value avl_ad9371_rx_xcvr {NUM_OF_LANES} {2} +set_instance_parameter_value avl_ad9371_rx_xcvr {NUM_OF_CONVS} {4} +set_instance_parameter_value avl_ad9371_rx_xcvr {FRM_BCNT} {4} +set_instance_parameter_value avl_ad9371_rx_xcvr {FRM_SCNT} {1} +set_instance_parameter_value avl_ad9371_rx_xcvr {MF_FCNT} {32} +set_instance_parameter_value avl_ad9371_rx_xcvr {HD} {1} +add_connection sys_clk.clk avl_ad9371_rx_xcvr.sys_clk +add_connection sys_clk.clk_reset avl_ad9371_rx_xcvr.sys_resetn +add_interface rx_ref_clk clock sink +set_interface_property rx_ref_clk EXPORT_OF avl_ad9371_rx_xcvr.ref_clk +add_interface rx_data_0 conduit end +set_interface_property rx_data_0 EXPORT_OF avl_ad9371_rx_xcvr.rx_data_0 +add_interface rx_data_1 conduit end +set_interface_property rx_data_1 EXPORT_OF avl_ad9371_rx_xcvr.rx_data_1 +add_interface rx_sysref conduit end +set_interface_property rx_sysref EXPORT_OF avl_ad9371_rx_xcvr.sysref +add_interface rx_sync conduit end +set_interface_property rx_sync EXPORT_OF avl_ad9371_rx_xcvr.sync -add_instance xcvr_tx_lane_pll altera_xcvr_atx_pll_a10 16.0 -set_instance_parameter_value xcvr_tx_lane_pll {rcfg_debug} {0} -set_instance_parameter_value xcvr_tx_lane_pll {enable_pll_reconfig} {1} -set_instance_parameter_value xcvr_tx_lane_pll {rcfg_jtag_enable} {0} -set_instance_parameter_value xcvr_tx_lane_pll {rcfg_separate_avmm_busy} {1} -set_instance_parameter_value xcvr_tx_lane_pll {rcfg_enable_avmm_busy_port} {0} -set_instance_parameter_value xcvr_tx_lane_pll {set_capability_reg_enable} {1} -set_instance_parameter_value xcvr_tx_lane_pll {set_user_identifier} {0} -set_instance_parameter_value xcvr_tx_lane_pll {set_csr_soft_logic_enable} {1} -set_instance_parameter_value xcvr_tx_lane_pll {rcfg_file_prefix} {altera_xcvr_atx_pll_a10} -set_instance_parameter_value xcvr_tx_lane_pll {rcfg_sv_file_enable} {0} -set_instance_parameter_value xcvr_tx_lane_pll {rcfg_h_file_enable} {0} -set_instance_parameter_value xcvr_tx_lane_pll {rcfg_txt_file_enable} {0} -set_instance_parameter_value xcvr_tx_lane_pll {rcfg_mif_file_enable} {0} -set_instance_parameter_value xcvr_tx_lane_pll {rcfg_multi_enable} {0} -set_instance_parameter_value xcvr_tx_lane_pll {rcfg_profile_cnt} {2} -set_instance_parameter_value xcvr_tx_lane_pll {rcfg_profile_select} {1} -set_instance_parameter_value xcvr_tx_lane_pll {rcfg_param_vals1} {} -set_instance_parameter_value xcvr_tx_lane_pll {rcfg_param_vals2} {} -set_instance_parameter_value xcvr_tx_lane_pll {enable_manual_configuration} {1} -set_instance_parameter_value xcvr_tx_lane_pll {generate_docs} {1} -set_instance_parameter_value xcvr_tx_lane_pll {generate_add_hdl_instance_example} {0} -set_instance_parameter_value xcvr_tx_lane_pll {test_mode} {0} -set_instance_parameter_value xcvr_tx_lane_pll {enable_pld_atx_cal_busy_port} {1} -set_instance_parameter_value xcvr_tx_lane_pll {enable_debug_ports_parameters} {0} -set_instance_parameter_value xcvr_tx_lane_pll {support_mode} {user_mode} -set_instance_parameter_value xcvr_tx_lane_pll {message_level} {error} -set_instance_parameter_value xcvr_tx_lane_pll {prot_mode} {Basic} -set_instance_parameter_value xcvr_tx_lane_pll {bw_sel} {medium} -set_instance_parameter_value xcvr_tx_lane_pll {refclk_cnt} {1} -set_instance_parameter_value xcvr_tx_lane_pll {refclk_index} {0} -set_instance_parameter_value xcvr_tx_lane_pll {silicon_rev} {0} -set_instance_parameter_value xcvr_tx_lane_pll {primary_pll_buffer} {GX clock output buffer} -set_instance_parameter_value xcvr_tx_lane_pll {enable_8G_path} {1} -set_instance_parameter_value xcvr_tx_lane_pll {enable_16G_path} {0} -set_instance_parameter_value xcvr_tx_lane_pll {enable_pcie_clk} {0} -set_instance_parameter_value xcvr_tx_lane_pll {enable_cascade_out} {0} -set_instance_parameter_value xcvr_tx_lane_pll {enable_hip_cal_done_port} {0} -set_instance_parameter_value xcvr_tx_lane_pll {set_hip_cal_en} {0} -set_instance_parameter_value xcvr_tx_lane_pll {set_output_clock_frequency} {2457.6} -set_instance_parameter_value xcvr_tx_lane_pll {set_auto_reference_clock_frequency} {122.88} -set_instance_parameter_value xcvr_tx_lane_pll {set_manual_reference_clock_frequency} {200.0} -set_instance_parameter_value xcvr_tx_lane_pll {set_fref_clock_frequency} {156.25} -set_instance_parameter_value xcvr_tx_lane_pll {select_manual_config} {0} -set_instance_parameter_value xcvr_tx_lane_pll {set_m_counter} {24} -set_instance_parameter_value xcvr_tx_lane_pll {set_ref_clk_div} {1} -set_instance_parameter_value xcvr_tx_lane_pll {set_l_counter} {16} -set_instance_parameter_value xcvr_tx_lane_pll {set_l_cascade_counter} {15} -set_instance_parameter_value xcvr_tx_lane_pll {set_l_cascade_predivider} {1} -set_instance_parameter_value xcvr_tx_lane_pll {set_k_counter} {2000000000.0} -set_instance_parameter_value xcvr_tx_lane_pll {set_altera_xcvr_atx_pll_a10_calibration_en} {1} -set_instance_parameter_value xcvr_tx_lane_pll {enable_analog_resets} {0} -set_instance_parameter_value xcvr_tx_lane_pll {enable_mcgb} {0} -set_instance_parameter_value xcvr_tx_lane_pll {mcgb_div} {1} -set_instance_parameter_value xcvr_tx_lane_pll {enable_hfreq_clk} {0} -set_instance_parameter_value xcvr_tx_lane_pll {enable_mcgb_pcie_clksw} {0} -set_instance_parameter_value xcvr_tx_lane_pll {mcgb_aux_clkin_cnt} {0} -set_instance_parameter_value xcvr_tx_lane_pll {enable_bonding_clks} {0} -set_instance_parameter_value xcvr_tx_lane_pll {enable_fb_comp_bonding} {0} -set_instance_parameter_value xcvr_tx_lane_pll {pma_width} {64} -set_instance_parameter_value xcvr_tx_lane_pll {enable_pld_mcgb_cal_busy_port} {0} +# ad9371_rx-xcvr -add_instance xcvr_tx_core altera_jesd204 16.0 -set_instance_parameter_value xcvr_tx_core {wrapper_opt} {base_phy} -set_instance_parameter_value xcvr_tx_core {sdc_constraint} {1.0} -set_instance_parameter_value xcvr_tx_core {DATA_PATH} {TX} -set_instance_parameter_value xcvr_tx_core {SUBCLASSV} {1} -set_instance_parameter_value xcvr_tx_core {lane_rate} {4915.2} -set_instance_parameter_value xcvr_tx_core {PCS_CONFIG} {JESD_PCS_CFG1} -set_instance_parameter_value xcvr_tx_core {pll_type} {CMU} -set_instance_parameter_value xcvr_tx_core {bonded_mode} {non_bonded} -set_instance_parameter_value xcvr_tx_core {REFCLK_FREQ} {125.0} -set_instance_parameter_value xcvr_tx_core {bitrev_en} {0} -set_instance_parameter_value xcvr_tx_core {pll_reconfig_enable} {1} -set_instance_parameter_value xcvr_tx_core {rcfg_jtag_enable} {0} -set_instance_parameter_value xcvr_tx_core {set_capability_reg_enable} {1} -set_instance_parameter_value xcvr_tx_core {set_user_identifier} {0} -set_instance_parameter_value xcvr_tx_core {set_csr_soft_logic_enable} {1} -set_instance_parameter_value xcvr_tx_core {set_prbs_soft_logic_enable} {0} -set_instance_parameter_value xcvr_tx_core {L} {4} -set_instance_parameter_value xcvr_tx_core {M} {4} -set_instance_parameter_value xcvr_tx_core {GUI_EN_CFG_F} {0} -set_instance_parameter_value xcvr_tx_core {GUI_CFG_F} {4} -set_instance_parameter_value xcvr_tx_core {N} {16} -set_instance_parameter_value xcvr_tx_core {N_PRIME} {16} -set_instance_parameter_value xcvr_tx_core {S} {1} -set_instance_parameter_value xcvr_tx_core {K} {32} -set_instance_parameter_value xcvr_tx_core {SCR} {1} -set_instance_parameter_value xcvr_tx_core {CS} {0} -set_instance_parameter_value xcvr_tx_core {CF} {0} -set_instance_parameter_value xcvr_tx_core {HD} {0} -set_instance_parameter_value xcvr_tx_core {ECC_EN} {0} -set_instance_parameter_value xcvr_tx_core {DLB_TEST} {0} -set_instance_parameter_value xcvr_tx_core {PHADJ} {0} -set_instance_parameter_value xcvr_tx_core {ADJCNT} {0} -set_instance_parameter_value xcvr_tx_core {ADJDIR} {0} -set_instance_parameter_value xcvr_tx_core {OPTIMIZE} {0} -set_instance_parameter_value xcvr_tx_core {DID} {0} -set_instance_parameter_value xcvr_tx_core {BID} {0} -set_instance_parameter_value xcvr_tx_core {LID0} {0} -set_instance_parameter_value xcvr_tx_core {LID1} {1} -set_instance_parameter_value xcvr_tx_core {LID2} {2} -set_instance_parameter_value xcvr_tx_core {LID3} {3} -set_instance_parameter_value xcvr_tx_core {LID4} {4} -set_instance_parameter_value xcvr_tx_core {LID5} {5} -set_instance_parameter_value xcvr_tx_core {LID6} {6} -set_instance_parameter_value xcvr_tx_core {LID7} {7} -set_instance_parameter_value xcvr_tx_core {JESDV} {1} -set_instance_parameter_value xcvr_tx_core {RES1} {0} -set_instance_parameter_value xcvr_tx_core {RES2} {0} -set_instance_parameter_value xcvr_tx_core {TEST_COMPONENTS_EN} {0} -set_instance_parameter_value xcvr_tx_core {TERMINATE_RECONFIG_EN} {0} -set_instance_parameter_value xcvr_tx_core {ED_GENERIC_5SERIES} {No} -set_instance_parameter_value xcvr_tx_core {ED_GENERIC_A10} {No} -set_instance_parameter_value xcvr_tx_core {ED_FILESET_SIM} {0} -set_instance_parameter_value xcvr_tx_core {ED_FILESET_SYNTH} {0} -set_instance_parameter_value xcvr_tx_core {ED_HDL_FORMAT_SIM} {VERILOG} -set_instance_parameter_value xcvr_tx_core {ED_HDL_FORMAT_SYNTH} {VERILOG} -set_instance_parameter_value xcvr_tx_core {ED_DEV_KIT} {NONE} +add_instance axi_ad9371_rx_xcvr axi_adxcvr 1.0 +set_instance_parameter_value axi_ad9371_rx_xcvr {ID} {1} +set_instance_parameter_value axi_ad9371_rx_xcvr {TX_OR_RX_N} {0} +set_instance_parameter_value axi_ad9371_rx_xcvr {NUM_OF_LANES} {2} +add_connection sys_clk.clk axi_ad9371_rx_xcvr.s_axi_clock +add_connection sys_clk.clk_reset axi_ad9371_rx_xcvr.s_axi_reset +add_connection axi_ad9371_rx_xcvr.if_up_rst avl_ad9371_rx_xcvr.rst +add_connection avl_ad9371_rx_xcvr.ready axi_ad9371_rx_xcvr.ready +add_connection axi_ad9371_rx_xcvr.core_pll_locked avl_ad9371_rx_xcvr.core_pll_locked -add_instance axi_jesd_xcvr axi_jesd_xcvr 1.0 -set_instance_parameter_value axi_jesd_xcvr {ID} {0} -set_instance_parameter_value axi_jesd_xcvr {DEVICE_TYPE} {0} -set_instance_parameter_value axi_jesd_xcvr {TX_NUM_OF_LANES} {4} -set_instance_parameter_value axi_jesd_xcvr {RX_NUM_OF_LANES} {2} +# ad9371_rx_os-xcvr -add_instance xcvr_rx_rst_cntrl altera_xcvr_reset_control 16.0 -set_instance_parameter_value xcvr_rx_rst_cntrl {CHANNELS} {2} -set_instance_parameter_value xcvr_rx_rst_cntrl {PLLS} {1} -set_instance_parameter_value xcvr_rx_rst_cntrl {SYS_CLK_IN_MHZ} {100} -set_instance_parameter_value xcvr_rx_rst_cntrl {SYNCHRONIZE_RESET} {1} -set_instance_parameter_value xcvr_rx_rst_cntrl {REDUCED_SIM_TIME} {1} -set_instance_parameter_value xcvr_rx_rst_cntrl {gui_split_interfaces} {0} -set_instance_parameter_value xcvr_rx_rst_cntrl {TX_PLL_ENABLE} {0} -set_instance_parameter_value xcvr_rx_rst_cntrl {T_PLL_POWERDOWN} {1000} -set_instance_parameter_value xcvr_rx_rst_cntrl {SYNCHRONIZE_PLL_RESET} {0} -set_instance_parameter_value xcvr_rx_rst_cntrl {TX_ENABLE} {0} -set_instance_parameter_value xcvr_rx_rst_cntrl {TX_PER_CHANNEL} {0} -set_instance_parameter_value xcvr_rx_rst_cntrl {gui_tx_auto_reset} {0} -set_instance_parameter_value xcvr_rx_rst_cntrl {T_TX_ANALOGRESET} {70000} -set_instance_parameter_value xcvr_rx_rst_cntrl {T_TX_DIGITALRESET} {70000} -set_instance_parameter_value xcvr_rx_rst_cntrl {T_PLL_LOCK_HYST} {0} -set_instance_parameter_value xcvr_rx_rst_cntrl {gui_pll_cal_busy} {1} -set_instance_parameter_value xcvr_rx_rst_cntrl {RX_ENABLE} {1} -set_instance_parameter_value xcvr_rx_rst_cntrl {RX_PER_CHANNEL} {0} -set_instance_parameter_value xcvr_rx_rst_cntrl {gui_rx_auto_reset} {0} -set_instance_parameter_value xcvr_rx_rst_cntrl {T_RX_ANALOGRESET} {70000} -set_instance_parameter_value xcvr_rx_rst_cntrl {T_RX_DIGITALRESET} {4000} +add_instance avl_ad9371_rx_os_xcvr avl_adxcvr 1.0 +set_instance_parameter_value avl_ad9371_rx_os_xcvr {ID} {1} +set_instance_parameter_value avl_ad9371_rx_os_xcvr {TX_OR_RX_N} {0} +set_instance_parameter_value avl_ad9371_rx_os_xcvr {PCS_CONFIG} {JESD_PCS_CFG2} +set_instance_parameter_value avl_ad9371_rx_os_xcvr {LANE_RATE} {10000.0} +set_instance_parameter_value avl_ad9371_rx_os_xcvr {PLLCLK_FREQUENCY} {5000.0} +set_instance_parameter_value avl_ad9371_rx_os_xcvr {REFCLK_FREQUENCY} {500.0} +set_instance_parameter_value avl_ad9371_rx_os_xcvr {CORECLK_FREQUENCY} {250.0} +set_instance_parameter_value avl_ad9371_rx_os_xcvr {NUM_OF_LANES} {2} +set_instance_parameter_value avl_ad9371_rx_os_xcvr {NUM_OF_CONVS} {2} +set_instance_parameter_value avl_ad9371_rx_os_xcvr {FRM_BCNT} {2} +set_instance_parameter_value avl_ad9371_rx_os_xcvr {FRM_SCNT} {1} +set_instance_parameter_value avl_ad9371_rx_os_xcvr {MF_FCNT} {32} +set_instance_parameter_value avl_ad9371_rx_os_xcvr {HD} {1} +add_connection sys_clk.clk avl_ad9371_rx_os_xcvr.sys_clk +add_connection sys_clk.clk_reset avl_ad9371_rx_os_xcvr.sys_resetn +add_interface rx_os_ref_clk clock sink +set_interface_property rx_os_ref_clk EXPORT_OF avl_ad9371_rx_os_xcvr.ref_clk +add_interface rx_data_2 conduit end +set_interface_property rx_data_2 EXPORT_OF avl_ad9371_rx_os_xcvr.rx_data_0 +add_interface rx_data_3 conduit end +set_interface_property rx_data_3 EXPORT_OF avl_ad9371_rx_os_xcvr.rx_data_1 +add_interface rx_os_sysref conduit end +set_interface_property rx_os_sysref EXPORT_OF avl_ad9371_rx_os_xcvr.sysref +add_interface rx_os_sync conduit end +set_interface_property rx_os_sync EXPORT_OF avl_ad9371_rx_os_xcvr.sync -add_instance xcvr_rx_core altera_jesd204 16.0 -set_instance_parameter_value xcvr_rx_core {wrapper_opt} {base_phy} -set_instance_parameter_value xcvr_rx_core {sdc_constraint} {1.0} -set_instance_parameter_value xcvr_rx_core {DATA_PATH} {RX} -set_instance_parameter_value xcvr_rx_core {SUBCLASSV} {1} -set_instance_parameter_value xcvr_rx_core {lane_rate} {4915.2} -set_instance_parameter_value xcvr_rx_core {PCS_CONFIG} {JESD_PCS_CFG1} -set_instance_parameter_value xcvr_rx_core {pll_type} {CMU} -set_instance_parameter_value xcvr_rx_core {bonded_mode} {non_bonded} -set_instance_parameter_value xcvr_rx_core {REFCLK_FREQ} {122.88} -set_instance_parameter_value xcvr_rx_core {bitrev_en} {0} -set_instance_parameter_value xcvr_rx_core {pll_reconfig_enable} {0} -set_instance_parameter_value xcvr_rx_core {rcfg_jtag_enable} {0} -set_instance_parameter_value xcvr_rx_core {set_capability_reg_enable} {0} -set_instance_parameter_value xcvr_rx_core {set_user_identifier} {0} -set_instance_parameter_value xcvr_rx_core {set_csr_soft_logic_enable} {0} -set_instance_parameter_value xcvr_rx_core {set_prbs_soft_logic_enable} {0} -set_instance_parameter_value xcvr_rx_core {L} {2} -set_instance_parameter_value xcvr_rx_core {M} {4} -set_instance_parameter_value xcvr_rx_core {GUI_EN_CFG_F} {0} -set_instance_parameter_value xcvr_rx_core {GUI_CFG_F} {4} -set_instance_parameter_value xcvr_rx_core {N} {16} -set_instance_parameter_value xcvr_rx_core {N_PRIME} {16} -set_instance_parameter_value xcvr_rx_core {S} {1} -set_instance_parameter_value xcvr_rx_core {K} {32} -set_instance_parameter_value xcvr_rx_core {SCR} {1} -set_instance_parameter_value xcvr_rx_core {CS} {0} -set_instance_parameter_value xcvr_rx_core {CF} {0} -set_instance_parameter_value xcvr_rx_core {HD} {0} -set_instance_parameter_value xcvr_rx_core {ECC_EN} {0} -set_instance_parameter_value xcvr_rx_core {DLB_TEST} {0} -set_instance_parameter_value xcvr_rx_core {PHADJ} {0} -set_instance_parameter_value xcvr_rx_core {ADJCNT} {0} -set_instance_parameter_value xcvr_rx_core {ADJDIR} {0} -set_instance_parameter_value xcvr_rx_core {OPTIMIZE} {0} -set_instance_parameter_value xcvr_rx_core {DID} {0} -set_instance_parameter_value xcvr_rx_core {BID} {0} -set_instance_parameter_value xcvr_rx_core {LID0} {0} -set_instance_parameter_value xcvr_rx_core {LID1} {1} -set_instance_parameter_value xcvr_rx_core {LID2} {2} -set_instance_parameter_value xcvr_rx_core {LID3} {3} -set_instance_parameter_value xcvr_rx_core {LID4} {4} -set_instance_parameter_value xcvr_rx_core {LID5} {5} -set_instance_parameter_value xcvr_rx_core {LID6} {6} -set_instance_parameter_value xcvr_rx_core {LID7} {7} -set_instance_parameter_value xcvr_rx_core {JESDV} {1} -set_instance_parameter_value xcvr_rx_core {RES1} {0} -set_instance_parameter_value xcvr_rx_core {RES2} {0} -set_instance_parameter_value xcvr_rx_core {TEST_COMPONENTS_EN} {0} -set_instance_parameter_value xcvr_rx_core {TERMINATE_RECONFIG_EN} {0} -set_instance_parameter_value xcvr_rx_core {ED_GENERIC_5SERIES} {No} -set_instance_parameter_value xcvr_rx_core {ED_GENERIC_A10} {No} -set_instance_parameter_value xcvr_rx_core {ED_FILESET_SIM} {0} -set_instance_parameter_value xcvr_rx_core {ED_FILESET_SYNTH} {0} -set_instance_parameter_value xcvr_rx_core {ED_HDL_FORMAT_SIM} {VERILOG} -set_instance_parameter_value xcvr_rx_core {ED_HDL_FORMAT_SYNTH} {VERILOG} -set_instance_parameter_value xcvr_rx_core {ED_DEV_KIT} {NONE} +# ad9371_rx_os-xcvr -add_instance axi_os_jesd_xcvr axi_jesd_xcvr 1.0 -set_instance_parameter_value axi_os_jesd_xcvr {ID} {1} -set_instance_parameter_value axi_os_jesd_xcvr {DEVICE_TYPE} {0} -set_instance_parameter_value axi_os_jesd_xcvr {TX_NUM_OF_LANES} {0} -set_instance_parameter_value axi_os_jesd_xcvr {RX_NUM_OF_LANES} {2} +add_instance axi_ad9371_rx_os_xcvr axi_adxcvr 1.0 +set_instance_parameter_value axi_ad9371_rx_os_xcvr {ID} {2} +set_instance_parameter_value axi_ad9371_rx_os_xcvr {TX_OR_RX_N} {0} +set_instance_parameter_value axi_ad9371_rx_os_xcvr {NUM_OF_LANES} {2} +add_connection sys_clk.clk axi_ad9371_rx_os_xcvr.s_axi_clock +add_connection sys_clk.clk_reset axi_ad9371_rx_os_xcvr.s_axi_reset +add_connection axi_ad9371_rx_os_xcvr.if_up_rst avl_ad9371_rx_os_xcvr.rst +add_connection avl_ad9371_rx_os_xcvr.ready axi_ad9371_rx_os_xcvr.ready +add_connection axi_ad9371_rx_os_xcvr.core_pll_locked avl_ad9371_rx_os_xcvr.core_pll_locked -add_instance xcvr_rx_os_rst_cntrl altera_xcvr_reset_control 16.0 -set_instance_parameter_value xcvr_rx_os_rst_cntrl {CHANNELS} {2} -set_instance_parameter_value xcvr_rx_os_rst_cntrl {PLLS} {1} -set_instance_parameter_value xcvr_rx_os_rst_cntrl {SYS_CLK_IN_MHZ} {100} -set_instance_parameter_value xcvr_rx_os_rst_cntrl {SYNCHRONIZE_RESET} {1} -set_instance_parameter_value xcvr_rx_os_rst_cntrl {REDUCED_SIM_TIME} {1} -set_instance_parameter_value xcvr_rx_os_rst_cntrl {gui_split_interfaces} {0} -set_instance_parameter_value xcvr_rx_os_rst_cntrl {TX_PLL_ENABLE} {0} -set_instance_parameter_value xcvr_rx_os_rst_cntrl {T_PLL_POWERDOWN} {1000} -set_instance_parameter_value xcvr_rx_os_rst_cntrl {SYNCHRONIZE_PLL_RESET} {0} -set_instance_parameter_value xcvr_rx_os_rst_cntrl {TX_ENABLE} {0} -set_instance_parameter_value xcvr_rx_os_rst_cntrl {TX_PER_CHANNEL} {0} -set_instance_parameter_value xcvr_rx_os_rst_cntrl {gui_tx_auto_reset} {0} -set_instance_parameter_value xcvr_rx_os_rst_cntrl {T_TX_ANALOGRESET} {70000} -set_instance_parameter_value xcvr_rx_os_rst_cntrl {T_TX_DIGITALRESET} {70000} -set_instance_parameter_value xcvr_rx_os_rst_cntrl {T_PLL_LOCK_HYST} {0} -set_instance_parameter_value xcvr_rx_os_rst_cntrl {gui_pll_cal_busy} {1} -set_instance_parameter_value xcvr_rx_os_rst_cntrl {RX_ENABLE} {1} -set_instance_parameter_value xcvr_rx_os_rst_cntrl {RX_PER_CHANNEL} {0} -set_instance_parameter_value xcvr_rx_os_rst_cntrl {gui_rx_auto_reset} {0} -set_instance_parameter_value xcvr_rx_os_rst_cntrl {T_RX_ANALOGRESET} {70000} -set_instance_parameter_value xcvr_rx_os_rst_cntrl {T_RX_DIGITALRESET} {4000} - -add_instance xcvr_rx_os_core altera_jesd204 16.0 -set_instance_parameter_value xcvr_rx_os_core {wrapper_opt} {base_phy} -set_instance_parameter_value xcvr_rx_os_core {sdc_constraint} {1.0} -set_instance_parameter_value xcvr_rx_os_core {DATA_PATH} {RX} -set_instance_parameter_value xcvr_rx_os_core {SUBCLASSV} {1} -set_instance_parameter_value xcvr_rx_os_core {lane_rate} {4915.2} -set_instance_parameter_value xcvr_rx_os_core {PCS_CONFIG} {JESD_PCS_CFG1} -set_instance_parameter_value xcvr_rx_os_core {pll_type} {CMU} -set_instance_parameter_value xcvr_rx_os_core {bonded_mode} {non_bonded} -set_instance_parameter_value xcvr_rx_os_core {REFCLK_FREQ} {122.88} -set_instance_parameter_value xcvr_rx_os_core {bitrev_en} {0} -set_instance_parameter_value xcvr_rx_os_core {pll_reconfig_enable} {0} -set_instance_parameter_value xcvr_rx_os_core {rcfg_jtag_enable} {0} -set_instance_parameter_value xcvr_rx_os_core {set_capability_reg_enable} {0} -set_instance_parameter_value xcvr_rx_os_core {set_user_identifier} {0} -set_instance_parameter_value xcvr_rx_os_core {set_csr_soft_logic_enable} {0} -set_instance_parameter_value xcvr_rx_os_core {set_prbs_soft_logic_enable} {0} -set_instance_parameter_value xcvr_rx_os_core {L} {2} -set_instance_parameter_value xcvr_rx_os_core {M} {2} -set_instance_parameter_value xcvr_rx_os_core {GUI_EN_CFG_F} {0} -set_instance_parameter_value xcvr_rx_os_core {GUI_CFG_F} {4} -set_instance_parameter_value xcvr_rx_os_core {N} {16} -set_instance_parameter_value xcvr_rx_os_core {N_PRIME} {16} -set_instance_parameter_value xcvr_rx_os_core {S} {1} -set_instance_parameter_value xcvr_rx_os_core {K} {16} -set_instance_parameter_value xcvr_rx_os_core {SCR} {1} -set_instance_parameter_value xcvr_rx_os_core {CS} {0} -set_instance_parameter_value xcvr_rx_os_core {CF} {0} -set_instance_parameter_value xcvr_rx_os_core {HD} {0} -set_instance_parameter_value xcvr_rx_os_core {ECC_EN} {0} -set_instance_parameter_value xcvr_rx_os_core {DLB_TEST} {0} -set_instance_parameter_value xcvr_rx_os_core {PHADJ} {0} -set_instance_parameter_value xcvr_rx_os_core {ADJCNT} {0} -set_instance_parameter_value xcvr_rx_os_core {ADJDIR} {0} -set_instance_parameter_value xcvr_rx_os_core {OPTIMIZE} {0} -set_instance_parameter_value xcvr_rx_os_core {DID} {0} -set_instance_parameter_value xcvr_rx_os_core {BID} {0} -set_instance_parameter_value xcvr_rx_os_core {LID0} {0} -set_instance_parameter_value xcvr_rx_os_core {LID1} {1} -set_instance_parameter_value xcvr_rx_os_core {LID2} {2} -set_instance_parameter_value xcvr_rx_os_core {LID3} {3} -set_instance_parameter_value xcvr_rx_os_core {LID4} {4} -set_instance_parameter_value xcvr_rx_os_core {LID5} {5} -set_instance_parameter_value xcvr_rx_os_core {LID6} {6} -set_instance_parameter_value xcvr_rx_os_core {LID7} {7} -set_instance_parameter_value xcvr_rx_os_core {JESDV} {1} -set_instance_parameter_value xcvr_rx_os_core {RES1} {0} -set_instance_parameter_value xcvr_rx_os_core {RES2} {0} -set_instance_parameter_value xcvr_rx_os_core {TEST_COMPONENTS_EN} {0} -set_instance_parameter_value xcvr_rx_os_core {TERMINATE_RECONFIG_EN} {0} -set_instance_parameter_value xcvr_rx_os_core {ED_GENERIC_5SERIES} {No} -set_instance_parameter_value xcvr_rx_os_core {ED_GENERIC_A10} {No} -set_instance_parameter_value xcvr_rx_os_core {ED_FILESET_SIM} {0} -set_instance_parameter_value xcvr_rx_os_core {ED_FILESET_SYNTH} {0} -set_instance_parameter_value xcvr_rx_os_core {ED_HDL_FORMAT_SIM} {VERILOG} -set_instance_parameter_value xcvr_rx_os_core {ED_HDL_FORMAT_SYNTH} {VERILOG} -set_instance_parameter_value xcvr_rx_os_core {ED_DEV_KIT} {NONE} +# ad9371-core add_instance axi_ad9371 axi_ad9371 1.0 -set_instance_parameter_value axi_ad9371 {ID} {0} -set_instance_parameter_value axi_ad9371 {DAC_DATAPATH_DISABLE} {0} -set_instance_parameter_value axi_ad9371 {ADC_DATAPATH_DISABLE} {0} - -add_instance adc_pack util_cpack 1.0 -set_instance_parameter_value adc_pack {CHANNEL_DATA_WIDTH} {16} -set_instance_parameter_value adc_pack {NUM_OF_CHANNELS} {4} - -add_instance dac_upack util_upack 1.0 -set_instance_parameter_value dac_upack {CHANNEL_DATA_WIDTH} {32} -set_instance_parameter_value dac_upack {NUM_OF_CHANNELS} {4} - -add_instance adc_os_pack util_cpack 1.0 -set_instance_parameter_value adc_os_pack {CHANNEL_DATA_WIDTH} {32} -set_instance_parameter_value adc_os_pack {NUM_OF_CHANNELS} {2} - -add_instance rx_adcfifo util_adcfifo 1.0 -set_instance_parameter_value rx_adcfifo {ADC_DATA_WIDTH} {64} -set_instance_parameter_value rx_adcfifo {DMA_DATA_WIDTH} {64} -set_instance_parameter_value rx_adcfifo {DMA_READY_ENABLE} {1} -set_instance_parameter_value rx_adcfifo {DMA_ADDRESS_WIDTH} {16} - -add_instance rx_os_adcfifo util_adcfifo 1.0 -set_instance_parameter_value rx_os_adcfifo {ADC_DATA_WIDTH} {64} -set_instance_parameter_value rx_os_adcfifo {DMA_DATA_WIDTH} {64} -set_instance_parameter_value rx_os_adcfifo {DMA_READY_ENABLE} {1} -set_instance_parameter_value rx_os_adcfifo {DMA_ADDRESS_WIDTH} {16} - -add_instance axi_adc_dma axi_dmac 1.0 -set_instance_parameter_value axi_adc_dma {ID} {0} -set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_SRC} {64} -set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_DEST} {128} -set_instance_parameter_value axi_adc_dma {DMA_LENGTH_WIDTH} {24} -set_instance_parameter_value axi_adc_dma {DMA_2D_TRANSFER} {0} -set_instance_parameter_value axi_adc_dma {ASYNC_CLK_REQ_SRC} {1} -set_instance_parameter_value axi_adc_dma {ASYNC_CLK_SRC_DEST} {1} -set_instance_parameter_value axi_adc_dma {ASYNC_CLK_DEST_REQ} {1} -set_instance_parameter_value axi_adc_dma {AXI_SLICE_DEST} {0} -set_instance_parameter_value axi_adc_dma {AXI_SLICE_SRC} {0} -set_instance_parameter_value axi_adc_dma {SYNC_TRANSFER_START} {0} -set_instance_parameter_value axi_adc_dma {CYCLIC} {0} -set_instance_parameter_value axi_adc_dma {DMA_TYPE_DEST} {0} -set_instance_parameter_value axi_adc_dma {DMA_TYPE_SRC} {1} -set_instance_parameter_value axi_adc_dma {FIFO_SIZE} {16} - -add_instance axi_os_adc_dma axi_dmac 1.0 -set_instance_parameter_value axi_os_adc_dma {ID} {0} -set_instance_parameter_value axi_os_adc_dma {DMA_DATA_WIDTH_SRC} {64} -set_instance_parameter_value axi_os_adc_dma {DMA_DATA_WIDTH_DEST} {128} -set_instance_parameter_value axi_os_adc_dma {DMA_LENGTH_WIDTH} {24} -set_instance_parameter_value axi_os_adc_dma {DMA_2D_TRANSFER} {0} -set_instance_parameter_value axi_os_adc_dma {ASYNC_CLK_REQ_SRC} {1} -set_instance_parameter_value axi_os_adc_dma {ASYNC_CLK_SRC_DEST} {1} -set_instance_parameter_value axi_os_adc_dma {ASYNC_CLK_DEST_REQ} {1} -set_instance_parameter_value axi_os_adc_dma {AXI_SLICE_DEST} {0} -set_instance_parameter_value axi_os_adc_dma {AXI_SLICE_SRC} {0} -set_instance_parameter_value axi_os_adc_dma {SYNC_TRANSFER_START} {0} -set_instance_parameter_value axi_os_adc_dma {CYCLIC} {0} -set_instance_parameter_value axi_os_adc_dma {DMA_TYPE_DEST} {0} -set_instance_parameter_value axi_os_adc_dma {DMA_TYPE_SRC} {1} -set_instance_parameter_value axi_os_adc_dma {FIFO_SIZE} {16} - -add_instance axi_dac_dma axi_dmac 1.0 -set_instance_parameter_value axi_dac_dma {ID} {0} -set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_SRC} {128} -set_instance_parameter_value axi_dac_dma {DMA_DATA_WIDTH_DEST} {128} -set_instance_parameter_value axi_dac_dma {DMA_LENGTH_WIDTH} {24} -set_instance_parameter_value axi_dac_dma {DMA_2D_TRANSFER} {0} -set_instance_parameter_value axi_dac_dma {ASYNC_CLK_REQ_SRC} {1} -set_instance_parameter_value axi_dac_dma {ASYNC_CLK_SRC_DEST} {1} -set_instance_parameter_value axi_dac_dma {ASYNC_CLK_DEST_REQ} {1} -set_instance_parameter_value axi_dac_dma {AXI_SLICE_DEST} {0} -set_instance_parameter_value axi_dac_dma {AXI_SLICE_SRC} {0} -set_instance_parameter_value axi_dac_dma {SYNC_TRANSFER_START} {0} -set_instance_parameter_value axi_dac_dma {CYCLIC} {1} -set_instance_parameter_value axi_dac_dma {DMA_TYPE_DEST} {2} -set_instance_parameter_value axi_dac_dma {DMA_TYPE_SRC} {0} -set_instance_parameter_value axi_dac_dma {FIFO_SIZE} {16} - -add_instance ad9371_gpio altera_avalon_pio 16.0 -set_instance_parameter_value ad9371_gpio {bitClearingEdgeCapReg} {0} -set_instance_parameter_value ad9371_gpio {bitModifyingOutReg} {1} -set_instance_parameter_value ad9371_gpio {captureEdge} {0} -set_instance_parameter_value ad9371_gpio {direction} {Bidir} -set_instance_parameter_value ad9371_gpio {edgeType} {RISING} -set_instance_parameter_value ad9371_gpio {generateIRQ} {0} -set_instance_parameter_value ad9371_gpio {irqType} {LEVEL} -set_instance_parameter_value ad9371_gpio {resetValue} {0.0} -set_instance_parameter_value ad9371_gpio {simDoTestBenchWiring} {0} -set_instance_parameter_value ad9371_gpio {simDrivenValue} {0.0} -set_instance_parameter_value ad9371_gpio {width} {19} - -# connections - -add_connection axi_jesd_xcvr.if_tx_ip_avl xcvr_tx_core.jesd204_tx_link - -add_connection xcvr_rx_core.jesd204_rx_link axi_jesd_xcvr.if_rx_ip_avl - -add_connection xcvr_rx_os_core.jesd204_rx_link axi_os_jesd_xcvr.if_rx_ip_avl - -add_connection sys_clk.clk xcvr_tx_rst_cntrl.clock -add_connection sys_clk.clk xcvr_rx_rst_cntrl.clock -add_connection sys_clk.clk xcvr_rx_os_rst_cntrl.clock -add_connection sys_clk.clk xcvr_rx_core.jesd204_rx_avs_clk -add_connection sys_clk.clk xcvr_rx_os_core.jesd204_rx_avs_clk -add_connection sys_clk.clk xcvr_tx_core.jesd204_tx_avs_clk -add_connection sys_clk.clk xcvr_pll_reconfig.mgmt_clk -#add_connection sys_clk.clk xcvr_rx_core.reconfig_clk -#add_connection sys_clk.clk xcvr_rx_os_core.reconfig_clk -add_connection sys_clk.clk xcvr_tx_core.reconfig_clk -add_connection sys_clk.clk xcvr_tx_lane_pll.reconfig_clk0 -add_connection sys_clk.clk axi_adc_dma.s_axi_clock -add_connection sys_clk.clk axi_dac_dma.s_axi_clock -add_connection sys_clk.clk axi_jesd_xcvr.s_axi_clock -add_connection sys_clk.clk axi_os_jesd_xcvr.s_axi_clock +add_connection avl_ad9371_tx_xcvr.core_clk axi_ad9371.if_dac_clk +add_connection axi_ad9371.if_dac_tx_data avl_ad9371_tx_xcvr.ip_data +add_connection avl_ad9371_rx_xcvr.core_clk axi_ad9371.if_adc_clk +add_connection avl_ad9371_rx_xcvr.ip_sof axi_ad9371.if_adc_rx_sof +add_connection avl_ad9371_rx_xcvr.ip_data axi_ad9371.if_adc_rx_data +add_connection avl_ad9371_rx_os_xcvr.core_clk axi_ad9371.if_adc_os_clk +add_connection avl_ad9371_rx_os_xcvr.ip_sof axi_ad9371.if_adc_rx_os_sof +add_connection avl_ad9371_rx_os_xcvr.ip_data axi_ad9371.if_adc_rx_os_data add_connection sys_clk.clk axi_ad9371.s_axi_clock -add_connection sys_clk.clk axi_os_adc_dma.s_axi_clock -add_connection sys_clk.clk ad9371_gpio.clk - -add_connection sys_clk.clk_reset xcvr_rx_core.jesd204_rx_avs_rst_n -add_connection sys_clk.clk_reset xcvr_rx_os_core.jesd204_rx_avs_rst_n -add_connection sys_clk.clk_reset xcvr_tx_core.jesd204_tx_avs_rst_n -add_connection sys_clk.clk_reset xcvr_pll_reconfig.mgmt_reset -add_connection sys_clk.clk_reset xcvr_tx_lane_pll.reconfig_reset0 -add_connection sys_clk.clk_reset xcvr_pll.reset -add_connection sys_clk.clk_reset xcvr_rx_rst_cntrl.reset -add_connection sys_clk.clk_reset xcvr_tx_rst_cntrl.reset -add_connection sys_clk.clk_reset xcvr_rx_os_rst_cntrl.reset -#add_connection sys_clk.clk_reset xcvr_rx_core.reconfig_reset -#add_connection sys_clk.clk_reset xcvr_rx_os_core.reconfig_reset -add_connection sys_clk.clk_reset xcvr_tx_core.reconfig_reset -add_connection sys_clk.clk_reset axi_adc_dma.s_axi_reset -add_connection sys_clk.clk_reset axi_dac_dma.s_axi_reset -add_connection sys_clk.clk_reset axi_jesd_xcvr.s_axi_reset -add_connection sys_clk.clk_reset axi_os_jesd_xcvr.s_axi_reset add_connection sys_clk.clk_reset axi_ad9371.s_axi_reset -add_connection sys_clk.clk_reset axi_os_adc_dma.s_axi_reset -add_connection sys_clk.clk_reset ad9371_gpio.reset -add_connection sys_clk.clk_reset rx_adcfifo.if_adc_rst -add_connection sys_clk.clk_reset rx_os_adcfifo.if_adc_rst -if { $system_type=="a10soc" } { - add_connection sys_rst.out_reset xcvr_rx_core.jesd204_rx_avs_rst_n - add_connection sys_rst.out_reset xcvr_rx_os_core.jesd204_rx_avs_rst_n - add_connection sys_rst.out_reset xcvr_tx_core.jesd204_tx_avs_rst_n - add_connection sys_rst.out_reset xcvr_pll_reconfig.mgmt_reset - add_connection sys_rst.out_reset xcvr_tx_lane_pll.reconfig_reset0 - add_connection sys_rst.out_reset xcvr_pll.reset - add_connection sys_rst.out_reset xcvr_rx_rst_cntrl.reset - add_connection sys_rst.out_reset xcvr_tx_rst_cntrl.reset - add_connection sys_rst.out_reset xcvr_rx_os_rst_cntrl.reset - #add_connection sys_rst.out_reset xcvr_rx_core.reconfig_reset - #add_connection sys_rst.out_reset xcvr_rx_os_core.reconfig_reset - add_connection sys_rst.out_reset xcvr_tx_core.reconfig_reset - add_connection sys_rst.out_reset axi_adc_dma.s_axi_reset - add_connection sys_rst.out_reset axi_dac_dma.s_axi_reset - add_connection sys_rst.out_reset axi_jesd_xcvr.s_axi_reset - add_connection sys_rst.out_reset axi_os_jesd_xcvr.s_axi_reset - add_connection sys_rst.out_reset axi_ad9371.s_axi_reset - add_connection sys_rst.out_reset axi_os_adc_dma.s_axi_reset - add_connection sys_rst.out_reset ad9371_gpio.reset - add_connection sys_rst.out_reset rx_adcfifo.if_adc_rst - add_connection sys_rst.out_reset rx_os_adcfifo.if_adc_rst -} +# pack(s) & unpack(s) -add_connection xcvr_pll.outclk0 axi_ad9371.if_dac_clk -add_connection xcvr_pll.outclk0 dac_upack.if_dac_clk -add_connection xcvr_pll.outclk0 axi_dac_dma.if_fifo_rd_clk -add_connection xcvr_pll.outclk0 axi_jesd_xcvr.if_tx_clk -add_connection xcvr_pll.outclk0 xcvr_tx_core.txlink_clk -add_connection xcvr_pll.outclk1 adc_pack.if_adc_clk -add_connection xcvr_pll.outclk1 axi_ad9371.if_adc_clk -add_connection xcvr_pll.outclk1 axi_jesd_xcvr.if_rx_clk -add_connection xcvr_pll.outclk1 xcvr_rx_core.rxlink_clk -add_connection xcvr_pll.outclk1 rx_adcfifo.if_adc_clk -add_connection xcvr_pll.outclk1 rx_adcfifo.if_dma_clk -add_connection xcvr_pll.outclk1 axi_adc_dma.if_s_axis_aclk -add_connection xcvr_pll.outclk2 adc_os_pack.if_adc_clk -add_connection xcvr_pll.outclk2 axi_ad9371.if_adc_os_clk -add_connection xcvr_pll.outclk2 axi_os_jesd_xcvr.if_rx_clk -add_connection xcvr_pll.outclk2 xcvr_rx_os_core.rxlink_clk -add_connection xcvr_pll.outclk2 rx_os_adcfifo.if_adc_clk -add_connection xcvr_pll.outclk2 rx_os_adcfifo.if_dma_clk -add_connection xcvr_pll.outclk2 axi_os_adc_dma.if_s_axis_aclk +add_instance axi_ad9371_tx_upack util_upack 1.0 +set_instance_parameter_value axi_ad9371_tx_upack {NUM_OF_CHANNELS} {4} +set_instance_parameter_value axi_ad9371_tx_upack {CHANNEL_DATA_WIDTH} {32} +add_connection avl_ad9371_tx_xcvr.core_clk axi_ad9371_tx_upack.if_dac_clk +add_connection axi_ad9371_tx_upack.dac_ch_0 axi_ad9371.dac_ch_0 +add_connection axi_ad9371_tx_upack.dac_ch_1 axi_ad9371.dac_ch_1 +add_connection axi_ad9371_tx_upack.dac_ch_2 axi_ad9371.dac_ch_2 +add_connection axi_ad9371_tx_upack.dac_ch_3 axi_ad9371.dac_ch_3 -# NIOS -if { $system_type=="nios" } { - add_connection sys_ddr3_cntrl.emif_usr_clk axi_adc_dma.m_dest_axi_clock - add_connection sys_ddr3_cntrl.emif_usr_clk axi_os_adc_dma.m_dest_axi_clock - add_connection sys_ddr3_cntrl.emif_usr_clk axi_dac_dma.m_src_axi_clock - add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_adc_dma.m_dest_axi_reset - add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_os_adc_dma.m_dest_axi_reset - add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_dac_dma.m_src_axi_reset -} +add_instance axi_ad9371_rx_cpack util_cpack 1.0 +set_instance_parameter_value axi_ad9371_rx_cpack {NUM_OF_CHANNELS} {4} +set_instance_parameter_value axi_ad9371_rx_cpack {CHANNEL_DATA_WIDTH} {16} +add_connection sys_clk.clk_reset axi_ad9371_rx_cpack.if_adc_rst +add_connection avl_ad9371_rx_xcvr.core_clk axi_ad9371_rx_cpack.if_adc_clk +add_connection axi_ad9371.adc_ch_0 axi_ad9371_rx_cpack.adc_ch_0 +add_connection axi_ad9371.adc_ch_1 axi_ad9371_rx_cpack.adc_ch_1 +add_connection axi_ad9371.adc_ch_2 axi_ad9371_rx_cpack.adc_ch_2 +add_connection axi_ad9371.adc_ch_3 axi_ad9371_rx_cpack.adc_ch_3 -# SOC -if { $system_type=="a10soc" } { - add_connection arria10_hps_0.h2f_user0_clock axi_adc_dma.m_dest_axi_clock - add_connection arria10_hps_0.h2f_user0_clock axi_os_adc_dma.m_dest_axi_clock - add_connection arria10_hps_0.h2f_user0_clock axi_dac_dma.m_src_axi_clock - add_connection sys_rst.out_reset axi_adc_dma.m_dest_axi_reset - add_connection sys_rst.out_reset axi_os_adc_dma.m_dest_axi_reset - add_connection sys_rst.out_reset axi_dac_dma.m_src_axi_reset -} +add_instance axi_ad9371_rx_os_cpack util_cpack 1.0 +set_instance_parameter_value axi_ad9371_rx_os_cpack {NUM_OF_CHANNELS} {2} +set_instance_parameter_value axi_ad9371_rx_os_cpack {CHANNEL_DATA_WIDTH} {32} +add_connection sys_clk.clk_reset axi_ad9371_rx_os_cpack.if_adc_rst +add_connection avl_ad9371_rx_os_xcvr.core_clk axi_ad9371_rx_os_cpack.if_adc_clk +add_connection axi_ad9371.adc_os_ch_0 axi_ad9371_rx_os_cpack.adc_ch_0 +add_connection axi_ad9371.adc_os_ch_1 axi_ad9371_rx_os_cpack.adc_ch_1 -add_connection adc_pack.adc_ch_0 axi_ad9371.adc_ch_0 -add_connection adc_pack.adc_ch_1 axi_ad9371.adc_ch_1 -add_connection adc_pack.adc_ch_2 axi_ad9371.adc_ch_2 -add_connection adc_pack.adc_ch_3 axi_ad9371.adc_ch_3 +# dac & adc fifos -add_connection adc_pack.if_adc_valid rx_adcfifo.if_adc_wr -add_connection adc_pack.if_adc_data rx_adcfifo.if_adc_wdata +add_instance axi_ad9371_rx_fifo util_adcfifo 1.0 +set_instance_parameter_value axi_ad9371_rx_fifo {ADC_DATA_WIDTH} {64} +set_instance_parameter_value axi_ad9371_rx_fifo {DMA_DATA_WIDTH} {64} +set_instance_parameter_value axi_ad9371_rx_fifo {DMA_READY_ENABLE} {1} +set_instance_parameter_value axi_ad9371_rx_fifo {DMA_ADDRESS_WIDTH} {16} +add_connection sys_clk.clk_reset axi_ad9371_rx_fifo.if_adc_rst +add_connection avl_ad9371_rx_xcvr.core_clk axi_ad9371_rx_fifo.if_adc_clk +add_connection axi_ad9371_rx_cpack.if_adc_valid axi_ad9371_rx_fifo.if_adc_wr +add_connection axi_ad9371_rx_cpack.if_adc_data axi_ad9371_rx_fifo.if_adc_wdata +add_connection axi_ad9371_rx_fifo.if_adc_wovf axi_ad9371.if_adc_dovf -add_connection rx_adcfifo.if_dma_wr axi_adc_dma.if_s_axis_valid -add_connection rx_adcfifo.if_dma_wdata axi_adc_dma.if_s_axis_data -add_connection rx_adcfifo.if_dma_wready axi_adc_dma.if_s_axis_ready -add_connection rx_adcfifo.if_dma_xfer_req axi_adc_dma.if_s_axis_xfer_req -add_connection rx_adcfifo.if_adc_wovf axi_ad9371.if_adc_dovf +add_instance axi_ad9371_rx_os_fifo util_adcfifo 1.0 +set_instance_parameter_value axi_ad9371_rx_os_fifo {ADC_DATA_WIDTH} {64} +set_instance_parameter_value axi_ad9371_rx_os_fifo {DMA_DATA_WIDTH} {64} +set_instance_parameter_value axi_ad9371_rx_os_fifo {DMA_READY_ENABLE} {1} +set_instance_parameter_value axi_ad9371_rx_os_fifo {DMA_ADDRESS_WIDTH} {16} -add_connection adc_os_pack.adc_ch_0 axi_ad9371.adc_os_ch_0 -add_connection adc_os_pack.adc_ch_1 axi_ad9371.adc_os_ch_1 +add_connection sys_clk.clk_reset axi_ad9371_rx_os_fifo.if_adc_rst +add_connection avl_ad9371_rx_os_xcvr.core_clk axi_ad9371_rx_os_fifo.if_adc_clk +add_connection axi_ad9371_rx_os_cpack.if_adc_valid axi_ad9371_rx_os_fifo.if_adc_wr +add_connection axi_ad9371_rx_os_cpack.if_adc_data axi_ad9371_rx_os_fifo.if_adc_wdata +add_connection axi_ad9371_rx_os_fifo.if_adc_wovf axi_ad9371.if_adc_dovf -add_connection adc_os_pack.if_adc_valid rx_os_adcfifo.if_adc_wr -add_connection adc_os_pack.if_adc_data rx_os_adcfifo.if_adc_wdata +# dac & adc dma -add_connection rx_os_adcfifo.if_dma_wr axi_os_adc_dma.if_s_axis_valid -add_connection rx_os_adcfifo.if_dma_wdata axi_os_adc_dma.if_s_axis_data -add_connection rx_os_adcfifo.if_dma_wready axi_os_adc_dma.if_s_axis_ready -add_connection rx_os_adcfifo.if_dma_xfer_req axi_os_adc_dma.if_s_axis_xfer_req -add_connection rx_os_adcfifo.if_adc_wovf axi_ad9371.if_adc_dovf +add_instance axi_ad9371_tx_dma axi_dmac 1.0 +set_instance_parameter_value axi_ad9371_tx_dma {ID} {0} +set_instance_parameter_value axi_ad9371_tx_dma {DMA_DATA_WIDTH_SRC} {128} +set_instance_parameter_value axi_ad9371_tx_dma {DMA_DATA_WIDTH_DEST} {128} +set_instance_parameter_value axi_ad9371_tx_dma {DMA_LENGTH_WIDTH} {24} +set_instance_parameter_value axi_ad9371_tx_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value axi_ad9371_tx_dma {ASYNC_CLK_REQ_SRC} {1} +set_instance_parameter_value axi_ad9371_tx_dma {ASYNC_CLK_SRC_DEST} {1} +set_instance_parameter_value axi_ad9371_tx_dma {ASYNC_CLK_DEST_REQ} {1} +set_instance_parameter_value axi_ad9371_tx_dma {AXI_SLICE_DEST} {0} +set_instance_parameter_value axi_ad9371_tx_dma {AXI_SLICE_SRC} {0} +set_instance_parameter_value axi_ad9371_tx_dma {SYNC_TRANSFER_START} {0} +set_instance_parameter_value axi_ad9371_tx_dma {CYCLIC} {1} +set_instance_parameter_value axi_ad9371_tx_dma {DMA_TYPE_DEST} {2} +set_instance_parameter_value axi_ad9371_tx_dma {DMA_TYPE_SRC} {0} +set_instance_parameter_value axi_ad9371_tx_dma {FIFO_SIZE} {16} +add_connection avl_ad9371_tx_xcvr.core_clk axi_ad9371_tx_dma.if_fifo_rd_clk +add_connection axi_ad9371_tx_upack.if_dac_valid axi_ad9371_tx_dma.if_fifo_rd_en +add_connection axi_ad9371_tx_dma.if_fifo_rd_dout axi_ad9371_tx_upack.if_dac_data +add_connection axi_ad9371_tx_dma.if_fifo_rd_underflow axi_ad9371.if_dac_dunf +add_connection sys_clk.clk axi_ad9371_tx_dma.s_axi_clock +add_connection sys_clk.clk_reset axi_ad9371_tx_dma.s_axi_reset +add_connection sys_dma_clk.clk axi_ad9371_tx_dma.m_src_axi_clock +add_connection sys_dma_clk.clk_reset axi_ad9371_tx_dma.m_src_axi_reset -add_connection dac_upack.dac_ch_0 axi_ad9371.dac_ch_0 -add_connection dac_upack.dac_ch_1 axi_ad9371.dac_ch_1 -add_connection dac_upack.dac_ch_2 axi_ad9371.dac_ch_2 -add_connection dac_upack.dac_ch_3 axi_ad9371.dac_ch_3 +add_instance axi_ad9371_rx_dma axi_dmac 1.0 +set_instance_parameter_value axi_ad9371_rx_dma {ID} {0} +set_instance_parameter_value axi_ad9371_rx_dma {DMA_DATA_WIDTH_SRC} {64} +set_instance_parameter_value axi_ad9371_rx_dma {DMA_DATA_WIDTH_DEST} {128} +set_instance_parameter_value axi_ad9371_rx_dma {DMA_LENGTH_WIDTH} {24} +set_instance_parameter_value axi_ad9371_rx_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value axi_ad9371_rx_dma {ASYNC_CLK_REQ_SRC} {1} +set_instance_parameter_value axi_ad9371_rx_dma {ASYNC_CLK_SRC_DEST} {1} +set_instance_parameter_value axi_ad9371_rx_dma {ASYNC_CLK_DEST_REQ} {1} +set_instance_parameter_value axi_ad9371_rx_dma {AXI_SLICE_DEST} {0} +set_instance_parameter_value axi_ad9371_rx_dma {AXI_SLICE_SRC} {0} +set_instance_parameter_value axi_ad9371_rx_dma {SYNC_TRANSFER_START} {0} +set_instance_parameter_value axi_ad9371_rx_dma {CYCLIC} {0} +set_instance_parameter_value axi_ad9371_rx_dma {DMA_TYPE_DEST} {0} +set_instance_parameter_value axi_ad9371_rx_dma {DMA_TYPE_SRC} {1} +set_instance_parameter_value axi_ad9371_rx_dma {FIFO_SIZE} {16} +add_connection avl_ad9371_rx_xcvr.core_clk axi_ad9371_rx_fifo.if_dma_clk +add_connection avl_ad9371_rx_xcvr.core_clk axi_ad9371_rx_dma.if_s_axis_aclk +add_connection axi_ad9371_rx_fifo.if_dma_wr axi_ad9371_rx_dma.if_s_axis_valid +add_connection axi_ad9371_rx_fifo.if_dma_wdata axi_ad9371_rx_dma.if_s_axis_data +add_connection axi_ad9371_rx_dma.if_s_axis_ready axi_ad9371_rx_fifo.if_dma_wready +add_connection axi_ad9371_rx_dma.if_s_axis_xfer_req axi_ad9371_rx_fifo.if_dma_xfer_req +add_connection sys_clk.clk axi_ad9371_rx_dma.s_axi_clock +add_connection sys_clk.clk_reset axi_ad9371_rx_dma.s_axi_reset +add_connection sys_dma_clk.clk axi_ad9371_rx_dma.m_dest_axi_clock +add_connection sys_dma_clk.clk_reset axi_ad9371_rx_dma.m_dest_axi_reset -add_connection xcvr_rx_os_core.alldev_lane_aligned xcvr_rx_os_core.dev_lane_aligned -add_connection xcvr_rx_core.dev_lane_aligned xcvr_rx_core.alldev_lane_aligned -add_connection xcvr_rx_core.dev_sync_n axi_jesd_xcvr.if_rx_ip_sync -add_connection xcvr_tx_core.dev_sync_n xcvr_tx_core.mdev_sync_n +add_instance axi_ad9371_rx_os_dma axi_dmac 1.0 +set_instance_parameter_value axi_ad9371_rx_os_dma {ID} {0} +set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_DATA_WIDTH_SRC} {64} +set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_DATA_WIDTH_DEST} {128} +set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_LENGTH_WIDTH} {24} +set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value axi_ad9371_rx_os_dma {ASYNC_CLK_REQ_SRC} {1} +set_instance_parameter_value axi_ad9371_rx_os_dma {ASYNC_CLK_SRC_DEST} {1} +set_instance_parameter_value axi_ad9371_rx_os_dma {ASYNC_CLK_DEST_REQ} {1} +set_instance_parameter_value axi_ad9371_rx_os_dma {AXI_SLICE_DEST} {0} +set_instance_parameter_value axi_ad9371_rx_os_dma {AXI_SLICE_SRC} {0} +set_instance_parameter_value axi_ad9371_rx_os_dma {SYNC_TRANSFER_START} {0} +set_instance_parameter_value axi_ad9371_rx_os_dma {CYCLIC} {0} +set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_TYPE_DEST} {0} +set_instance_parameter_value axi_ad9371_rx_os_dma {DMA_TYPE_SRC} {1} +set_instance_parameter_value axi_ad9371_rx_os_dma {FIFO_SIZE} {16} +add_connection avl_ad9371_rx_os_xcvr.core_clk axi_ad9371_rx_os_fifo.if_dma_clk +add_connection avl_ad9371_rx_os_xcvr.core_clk axi_ad9371_rx_os_dma.if_s_axis_aclk +add_connection axi_ad9371_rx_os_fifo.if_dma_wr axi_ad9371_rx_os_dma.if_s_axis_valid +add_connection axi_ad9371_rx_os_fifo.if_dma_wdata axi_ad9371_rx_os_dma.if_s_axis_data +add_connection axi_ad9371_rx_os_dma.if_s_axis_ready axi_ad9371_rx_os_fifo.if_dma_wready +add_connection axi_ad9371_rx_os_dma.if_s_axis_xfer_req axi_ad9371_rx_os_fifo.if_dma_xfer_req +add_connection sys_clk.clk axi_ad9371_rx_os_dma.s_axi_clock +add_connection sys_clk.clk_reset axi_ad9371_rx_os_dma.s_axi_reset +add_connection sys_dma_clk.clk axi_ad9371_rx_os_dma.m_dest_axi_clock +add_connection sys_dma_clk.clk_reset axi_ad9371_rx_os_dma.m_dest_axi_reset -add_connection axi_ad9371.if_adc_rx_data axi_jesd_xcvr.if_rx_data -add_connection axi_ad9371.if_adc_rx_os_data axi_os_jesd_xcvr.if_rx_data -add_connection dac_upack.if_dac_data axi_dac_dma.if_fifo_rd_dout -add_connection axi_dac_dma.if_fifo_rd_en dac_upack.if_dac_valid -add_connection axi_dac_dma.if_fifo_rd_underflow axi_ad9371.if_dac_dunf -add_connection axi_jesd_xcvr.if_rx_ip_sof xcvr_rx_core.sof -add_connection axi_os_jesd_xcvr.if_rx_ip_sync xcvr_rx_os_core.dev_sync_n -add_connection axi_jesd_xcvr.if_rx_ip_sysref xcvr_rx_core.sysref -add_connection axi_jesd_xcvr.if_rx_ready xcvr_rx_rst_cntrl.rx_ready -add_connection axi_jesd_xcvr.if_tx_data axi_ad9371.if_dac_tx_data -add_connection axi_jesd_xcvr.if_tx_ip_sync xcvr_tx_core.sync_n -add_connection axi_jesd_xcvr.if_tx_ip_sysref xcvr_tx_core.sysref -add_connection xcvr_tx_lane_pll.pll_cal_busy xcvr_tx_rst_cntrl.pll_cal_busy -add_connection xcvr_tx_lane_pll.pll_locked xcvr_tx_rst_cntrl.pll_locked -add_connection xcvr_tx_lane_pll.pll_powerdown xcvr_tx_rst_cntrl.pll_powerdown -add_connection xcvr_pll_reconfig.reconfig_from_pll xcvr_pll.reconfig_from_pll -add_connection xcvr_pll_reconfig.reconfig_to_pll xcvr_pll.reconfig_to_pll -add_connection xcvr_rx_core.rx_analogreset xcvr_rx_rst_cntrl.rx_analogreset -add_connection xcvr_rx_os_core.rx_analogreset xcvr_rx_os_rst_cntrl.rx_analogreset -add_connection xcvr_rx_rst_cntrl.rx_cal_busy xcvr_rx_core.rx_cal_busy -add_connection xcvr_rx_os_rst_cntrl.rx_cal_busy xcvr_rx_os_core.rx_cal_busy -add_connection xcvr_rx_rst_cntrl.rx_digitalreset xcvr_rx_core.rx_digitalreset -add_connection xcvr_rx_os_rst_cntrl.rx_digitalreset xcvr_rx_os_core.rx_digitalreset -add_connection xcvr_rx_core.rx_islockedtodata xcvr_rx_rst_cntrl.rx_is_lockedtodata -add_connection xcvr_rx_os_core.rx_islockedtodata xcvr_rx_os_rst_cntrl.rx_is_lockedtodata -add_connection xcvr_rx_os_rst_cntrl.rx_ready axi_os_jesd_xcvr.if_rx_ready -add_connection xcvr_rx_os_core.sof axi_os_jesd_xcvr.if_rx_ip_sof -add_connection xcvr_rx_os_core.sysref axi_os_jesd_xcvr.if_rx_ip_sysref -add_connection xcvr_tx_core.tx_analogreset xcvr_tx_rst_cntrl.tx_analogreset -add_connection xcvr_tx_core.tx_cal_busy xcvr_tx_rst_cntrl.tx_cal_busy -add_connection xcvr_tx_rst_cntrl.tx_digitalreset xcvr_tx_core.tx_digitalreset -add_connection xcvr_tx_rst_cntrl.tx_ready axi_jesd_xcvr.if_tx_ready +# ad9371 gpio -add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_tx_core.tx_serial_clk0_ch0 -add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_tx_core.tx_serial_clk0_ch1 -add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_tx_core.tx_serial_clk0_ch2 -add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_tx_core.tx_serial_clk0_ch3 -add_connection axi_jesd_xcvr.if_rst xcvr_tx_rst_cntrl.reset -add_connection axi_os_jesd_xcvr.if_rst xcvr_rx_os_rst_cntrl.reset -add_connection axi_jesd_xcvr.if_rx_rstn adc_pack.if_adc_rst -add_connection axi_os_jesd_xcvr.if_rx_rstn adc_os_pack.if_adc_rst -add_connection axi_jesd_xcvr.if_rx_rstn xcvr_rx_core.rxlink_rst_n -add_connection axi_os_jesd_xcvr.if_rx_rstn xcvr_rx_os_core.rxlink_rst_n -add_connection axi_jesd_xcvr.if_tx_rstn xcvr_tx_core.txlink_rst_n +add_instance avl_ad9371_gpio altera_avalon_pio 16.0 +set_instance_parameter_value avl_ad9371_gpio {direction} {Bidir} +set_instance_parameter_value avl_ad9371_gpio {generateIRQ} {1} +set_instance_parameter_value avl_ad9371_gpio {width} {19} +add_connection sys_clk.clk avl_ad9371_gpio.clk +add_connection sys_clk.clk_reset avl_ad9371_gpio.reset +add_interface avl_ad9371_gpio conduit end +set_interface_property avl_ad9371_gpio EXPORT_OF avl_ad9371_gpio.external_connection +# reconfig sharing -add_interface rx_data conduit end -set_interface_property rx_data EXPORT_OF xcvr_rx_core.rx_serial_data -add_interface rx_os_data conduit end -set_interface_property rx_os_data EXPORT_OF xcvr_rx_os_core.rx_serial_data -add_interface rx_os_sync conduit end -set_interface_property rx_os_sync EXPORT_OF axi_os_jesd_xcvr.if_rx_sync -add_interface rx_os_sysref conduit end -set_interface_property rx_os_sysref EXPORT_OF axi_os_jesd_xcvr.if_rx_ext_sysref_in -add_interface rx_sync conduit end -set_interface_property rx_sync EXPORT_OF axi_jesd_xcvr.if_rx_sync -add_interface rx_sysref conduit end -set_interface_property rx_sysref EXPORT_OF axi_jesd_xcvr.if_rx_ext_sysref_in -add_interface tx_data conduit end -set_interface_property tx_data EXPORT_OF xcvr_tx_core.tx_serial_data -add_interface tx_sync conduit end -set_interface_property tx_sync EXPORT_OF axi_jesd_xcvr.if_tx_sync -add_interface tx_sysref conduit end -set_interface_property tx_sysref EXPORT_OF axi_jesd_xcvr.if_tx_ext_sysref_in +add_instance avl_adxcfg_0 avl_adxcfg 1.0 +add_connection sys_clk.clk avl_adxcfg_0.rcfg_clk +add_connection sys_clk.clk_reset avl_adxcfg_0.rcfg_reset_n +add_connection avl_adxcfg_0.rcfg_m0 avl_ad9371_tx_xcvr.phy_reconfig_0 +add_connection avl_adxcfg_0.rcfg_m1 avl_ad9371_rx_xcvr.phy_reconfig_0 -add_interface xcvr_ref_clk clock sink -set_interface_property xcvr_ref_clk EXPORT_OF xcvr_ref_clk.in_clk +add_instance avl_adxcfg_1 avl_adxcfg 1.0 +add_connection sys_clk.clk avl_adxcfg_1.rcfg_clk +add_connection sys_clk.clk_reset avl_adxcfg_1.rcfg_reset_n +add_connection avl_adxcfg_1.rcfg_m0 avl_ad9371_tx_xcvr.phy_reconfig_1 +add_connection avl_adxcfg_1.rcfg_m1 avl_ad9371_rx_xcvr.phy_reconfig_1 -add_connection xcvr_ref_clk.out_clk xcvr_pll.refclk -add_connection xcvr_ref_clk.out_clk xcvr_rx_core.pll_ref_clk -add_connection xcvr_ref_clk.out_clk xcvr_rx_os_core.pll_ref_clk -add_connection xcvr_ref_clk.out_clk xcvr_tx_lane_pll.pll_refclk0 +add_instance avl_adxcfg_2 avl_adxcfg 1.0 +add_connection sys_clk.clk avl_adxcfg_2.rcfg_clk +add_connection sys_clk.clk_reset avl_adxcfg_2.rcfg_reset_n +add_connection avl_adxcfg_2.rcfg_m0 avl_ad9371_tx_xcvr.phy_reconfig_2 +add_connection avl_adxcfg_2.rcfg_m1 avl_ad9371_rx_os_xcvr.phy_reconfig_0 -add_interface ad9371_gpio conduit end -set_interface_property ad9371_gpio EXPORT_OF ad9371_gpio.external_connection +add_instance avl_adxcfg_3 avl_adxcfg 1.0 +add_connection sys_clk.clk avl_adxcfg_3.rcfg_clk +add_connection sys_clk.clk_reset avl_adxcfg_3.rcfg_reset_n +add_connection avl_adxcfg_3.rcfg_m0 avl_ad9371_tx_xcvr.phy_reconfig_3 +add_connection avl_adxcfg_3.rcfg_m1 avl_ad9371_rx_os_xcvr.phy_reconfig_1 # addresses -# NIOS -if { $system_type=="nios" } { - add_connection sys_cpu.data_master xcvr_pll_reconfig.mgmt_avalon_slave - add_connection sys_cpu.data_master xcvr_tx_lane_pll.reconfig_avmm0 - add_connection sys_cpu.data_master axi_adc_dma.s_axi - add_connection sys_cpu.data_master axi_dac_dma.s_axi - add_connection sys_cpu.data_master axi_jesd_xcvr.s_axi - add_connection sys_cpu.data_master axi_os_jesd_xcvr.s_axi - add_connection sys_cpu.data_master axi_ad9371.s_axi - add_connection sys_cpu.data_master axi_os_adc_dma.s_axi - #add_connection sys_cpu.data_master xcvr_rx_core.reconfig_avmm - add_connection sys_cpu.data_master xcvr_rx_core.jesd204_rx_avs - #add_connection sys_cpu.data_master xcvr_rx_os_core.reconfig_avmm - add_connection sys_cpu.data_master xcvr_rx_os_core.jesd204_rx_avs - add_connection sys_cpu.data_master xcvr_tx_core.reconfig_avmm - add_connection sys_cpu.data_master xcvr_tx_core.jesd204_tx_avs - add_connection sys_cpu.data_master ad9371_gpio.s1 +ad_cpu_interconnect 0x00010000 avl_adxcfg_0.rcfg_s0 +ad_cpu_interconnect 0x00011000 avl_adxcfg_0.rcfg_s1 +ad_cpu_interconnect 0x00012000 avl_adxcfg_1.rcfg_s0 +ad_cpu_interconnect 0x00013000 avl_adxcfg_1.rcfg_s1 +ad_cpu_interconnect 0x00014000 avl_adxcfg_2.rcfg_s0 +ad_cpu_interconnect 0x00015000 avl_adxcfg_2.rcfg_s1 +ad_cpu_interconnect 0x00016000 avl_adxcfg_3.rcfg_s0 +ad_cpu_interconnect 0x00017000 avl_adxcfg_3.rcfg_s1 +ad_cpu_interconnect 0x00018000 avl_ad9371_tx_xcvr.core_pll_reconfig +ad_cpu_interconnect 0x00019000 avl_ad9371_tx_xcvr.ip_reconfig +ad_cpu_interconnect 0x0001a000 avl_ad9371_tx_xcvr.lane_pll_reconfig +ad_cpu_interconnect 0x0001b000 avl_ad9371_rx_xcvr.core_pll_reconfig +ad_cpu_interconnect 0x0001c000 avl_ad9371_rx_xcvr.ip_reconfig +ad_cpu_interconnect 0x0001d000 avl_ad9371_rx_os_xcvr.core_pll_reconfig +ad_cpu_interconnect 0x0001e000 avl_ad9371_rx_os_xcvr.ip_reconfig +ad_cpu_interconnect 0x00020000 axi_ad9371_tx_xcvr.s_axi +ad_cpu_interconnect 0x00030000 axi_ad9371_rx_xcvr.s_axi +ad_cpu_interconnect 0x00040000 axi_ad9371_rx_os_xcvr.s_axi +ad_cpu_interconnect 0x00050000 axi_ad9371_tx_dma.s_axi +ad_cpu_interconnect 0x00060000 axi_ad9371_rx_dma.s_axi +ad_cpu_interconnect 0x00070000 axi_ad9371_rx_os_dma.s_axi +ad_cpu_interconnect 0x00080000 axi_ad9371.s_axi +ad_cpu_interconnect 0x00090000 avl_ad9371_gpio.s1 - add_connection axi_adc_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0 - add_connection axi_os_adc_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0 - add_connection axi_dac_dma.m_src_axi sys_ddr3_cntrl.ctrl_amm_0 +# dma interconnects - set_connection_parameter_value sys_cpu.data_master/xcvr_pll_reconfig.mgmt_avalon_slave baseAddress {0x1003d800} - set_connection_parameter_value sys_cpu.data_master/xcvr_tx_lane_pll.reconfig_avmm0 baseAddress {0x1003c000} - set_connection_parameter_value sys_cpu.data_master/axi_adc_dma.s_axi baseAddress {0x10034000} - set_connection_parameter_value sys_cpu.data_master/axi_dac_dma.s_axi baseAddress {0x10010000} - set_connection_parameter_value sys_cpu.data_master/axi_jesd_xcvr.s_axi baseAddress {0x10040000} - set_connection_parameter_value sys_cpu.data_master/axi_os_jesd_xcvr.s_axi baseAddress {0x10020000} - set_connection_parameter_value sys_cpu.data_master/axi_ad9371.s_axi baseAddress {0x10000000} - set_connection_parameter_value sys_cpu.data_master/axi_os_adc_dma.s_axi baseAddress {0x10500000} - #set_connection_parameter_value sys_cpu.data_master/xcvr_rx_core.reconfig_avmm baseAddress {0x10030000} - set_connection_parameter_value sys_cpu.data_master/xcvr_rx_core.jesd204_rx_avs baseAddress {0x1003e400} - #set_connection_parameter_value sys_cpu.data_master/xcvr_rx_os_core.reconfig_avmm baseAddress {0x10130000} - set_connection_parameter_value sys_cpu.data_master/xcvr_rx_os_core.jesd204_rx_avs baseAddress {0x1013e400} - set_connection_parameter_value sys_cpu.data_master/xcvr_tx_core.reconfig_avmm baseAddress {0x10050000} - set_connection_parameter_value sys_cpu.data_master/xcvr_tx_core.jesd204_tx_avs baseAddress {0x1005e400} - set_connection_parameter_value sys_cpu.data_master/ad9371_gpio.s1 baseAddress {0x10060000} - - set_connection_parameter_value axi_adc_dma.m_dest_axi/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x00000000} - set_connection_parameter_value axi_os_adc_dma.m_dest_axi/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x00000000} - set_connection_parameter_value axi_dac_dma.m_src_axi/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x00000000} -} - -# SOC -if { $system_type=="a10soc" } { - add_connection arria10_hps_0.h2f_lw_axi_master xcvr_pll_reconfig.mgmt_avalon_slave - add_connection arria10_hps_0.h2f_lw_axi_master xcvr_tx_lane_pll.reconfig_avmm0 - add_connection arria10_hps_0.h2f_lw_axi_master axi_adc_dma.s_axi - add_connection arria10_hps_0.h2f_lw_axi_master axi_dac_dma.s_axi - add_connection arria10_hps_0.h2f_lw_axi_master axi_jesd_xcvr.s_axi - add_connection arria10_hps_0.h2f_lw_axi_master axi_os_jesd_xcvr.s_axi - add_connection arria10_hps_0.h2f_lw_axi_master axi_ad9371.s_axi - add_connection arria10_hps_0.h2f_lw_axi_master axi_os_adc_dma.s_axi - #add_connection arria10_hps_0.h2f_lw_axi_master xcvr_rx_core.reconfig_avmm - add_connection arria10_hps_0.h2f_lw_axi_master xcvr_rx_core.jesd204_rx_avs - #add_connection arria10_hps_0.h2f_lw_axi_master xcvr_rx_os_core.reconfig_avmm - add_connection arria10_hps_0.h2f_lw_axi_master xcvr_rx_os_core.jesd204_rx_avs - add_connection arria10_hps_0.h2f_lw_axi_master xcvr_tx_core.reconfig_avmm - add_connection arria10_hps_0.h2f_lw_axi_master xcvr_tx_core.jesd204_tx_avs - add_connection arria10_hps_0.h2f_lw_axi_master ad9371_gpio.s1 - - add_connection axi_adc_dma.m_dest_axi arria10_hps_0.f2sdram0_data - add_connection axi_os_adc_dma.m_dest_axi arria10_hps_0.f2sdram0_data - add_connection axi_dac_dma.m_src_axi arria10_hps_0.f2sdram0_data - - set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/ad9371_gpio.s1 baseAddress {0x00001000} - set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/xcvr_pll_reconfig.mgmt_avalon_slave baseAddress {0x00010000} - set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/xcvr_tx_lane_pll.reconfig_avmm0 baseAddress {0x00011000} - set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/axi_jesd_xcvr.s_axi baseAddress {0x00020000} - set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/xcvr_rx_core.jesd204_rx_avs baseAddress {0x00030000} - set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/axi_os_jesd_xcvr.s_axi baseAddress {0x00040000} - set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/xcvr_rx_os_core.jesd204_rx_avs baseAddress {0x00050000} - set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/xcvr_tx_core.jesd204_tx_avs baseAddress {0x00060000} - set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/xcvr_tx_core.reconfig_avmm baseAddress {0x00064000} - set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/axi_ad9371.s_axi baseAddress {0x00070000} - set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/axi_dac_dma.s_axi baseAddress {0x00080000} - set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/axi_os_adc_dma.s_axi baseAddress {0x0090000} - set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/axi_adc_dma.s_axi baseAddress {0x000a0000} - - set_connection_parameter_value axi_dac_dma.m_src_axi/arria10_hps_0.f2sdram0_data baseAddress {0x0000} - set_connection_parameter_value axi_os_adc_dma.m_dest_axi/arria10_hps_0.f2sdram0_data baseAddress {0x0000} - set_connection_parameter_value axi_adc_dma.m_dest_axi/arria10_hps_0.f2sdram0_data baseAddress {0x0000} -} +ad_dma_interconnect axi_ad9371_tx_dma.m_src_axi +ad_dma_interconnect axi_ad9371_rx_dma.m_dest_axi +ad_dma_interconnect axi_ad9371_rx_os_dma.m_dest_axi # interrupts -# NIOS -if { $system_type=="nios" } { - add_connection sys_cpu.irq axi_adc_dma.interrupt_sender - add_connection sys_cpu.irq axi_dac_dma.interrupt_sender - add_connection sys_cpu.irq axi_os_adc_dma.interrupt_sender +ad_cpu_interrupt 11 axi_ad9371_tx_dma.interrupt_sender +ad_cpu_interrupt 12 axi_ad9371_rx_dma.interrupt_sender +ad_cpu_interrupt 13 axi_ad9371_rx_os_dma.interrupt_sender +ad_cpu_interrupt 14 avl_ad9371_gpio.irq - set_connection_parameter_value sys_cpu.irq/axi_adc_dma.interrupt_sender irqNumber {10} - set_connection_parameter_value sys_cpu.irq/axi_dac_dma.interrupt_sender irqNumber {11} - set_connection_parameter_value sys_cpu.irq/axi_os_adc_dma.interrupt_sender irqNumber {12} -} - -# SOC -if { $system_type=="a10soc" } { - add_connection arria10_hps_0.f2h_irq0 axi_adc_dma.interrupt_sender - add_connection arria10_hps_0.f2h_irq0 axi_dac_dma.interrupt_sender - add_connection arria10_hps_0.f2h_irq0 axi_os_adc_dma.interrupt_sender - - set_connection_parameter_value arria10_hps_0.f2h_irq0/axi_adc_dma.interrupt_sender irqNumber {10} - set_connection_parameter_value arria10_hps_0.f2h_irq0/axi_dac_dma.interrupt_sender irqNumber {11} - set_connection_parameter_value arria10_hps_0.f2h_irq0/axi_os_adc_dma.interrupt_sender irqNumber {12} -} diff --git a/projects/common/a10soc/a10soc_system_qsys.tcl b/projects/common/a10soc/a10soc_system_qsys.tcl index 5df47d810..935e9bc0a 100755 --- a/projects/common/a10soc/a10soc_system_qsys.tcl +++ b/projects/common/a10soc/a10soc_system_qsys.tcl @@ -1,3 +1,4 @@ + package require qsys set_module_property NAME {system_bd} @@ -7,1292 +8,240 @@ set_project_property DEVICE {10AS066N3F40E2SGE2} set system_type a10soc add_instance sys_clk clock_source 16.0 -add_interface sys_rst reset sink +add_interface sys_clk clock sink set_interface_property sys_clk EXPORT_OF sys_clk.clk_in -set_interface_property sys_rst EXPORT_OF sys_clk.clk_in_reset +add_interface sys_rstn reset sink +set_interface_property sys_rstn EXPORT_OF sys_clk.clk_in_reset set_instance_parameter_value sys_clk {clockFrequency} {100000000.0} set_instance_parameter_value sys_clk {clockFrequencyKnown} {1} set_instance_parameter_value sys_clk {resetSynchronousEdges} {DEASSERT} -add_instance sys_rst altera_reset_bridge 16.0 -set_instance_parameter_value sys_rst {ACTIVE_LOW_RESET} {0} -set_instance_parameter_value sys_rst {SYNCHRONOUS_EDGES} {deassert} -set_instance_parameter_value sys_rst {NUM_RESET_OUTPUTS} {1} -set_instance_parameter_value sys_rst {USE_RESET_REQUEST} {0} +# hps +# round-about way - qsys-script doesn't support {*}? -# HPS -add_instance arria10_hps_0 altera_arria10_hps 16.0 -set_instance_parameter_value arria10_hps_0 {MPU_EVENTS_Enable} {0} -set_instance_parameter_value arria10_hps_0 {GP_Enable} {0} -set_instance_parameter_value arria10_hps_0 {DEBUG_APB_Enable} {0} -set_instance_parameter_value arria10_hps_0 {STM_Enable} {0} -set_instance_parameter_value arria10_hps_0 {CTI_Enable} {0} -set_instance_parameter_value arria10_hps_0 {JTAG_Enable} {0} -set_instance_parameter_value arria10_hps_0 {TEST_Enable} {0} -set_instance_parameter_value arria10_hps_0 {BOOT_FROM_FPGA_Enable} {0} -set_instance_parameter_value arria10_hps_0 {BSEL_EN} {0} -set_instance_parameter_value arria10_hps_0 {BSEL} {1} -set_instance_parameter_value arria10_hps_0 {F2S_Width} {0} -set_instance_parameter_value arria10_hps_0 {S2F_Width} {0} -set_instance_parameter_value arria10_hps_0 {LWH2F_Enable} {1} -set_instance_parameter_value arria10_hps_0 {RUN_INTERNAL_BUILD_CHECKS} {0} -set_instance_parameter_value arria10_hps_0 {F2SDRAM_PORT_CONFIG} {6} -set_instance_parameter_value arria10_hps_0 {F2SDRAM0_ENABLED} {1} -set_instance_parameter_value arria10_hps_0 {F2SDRAM1_ENABLED} {0} -set_instance_parameter_value arria10_hps_0 {F2SDRAM2_ENABLED} {0} -set_instance_parameter_value arria10_hps_0 {F2SDRAM_READY_LATENCY} {0} -set_instance_parameter_value arria10_hps_0 {F2SDRAM2_DELAY} {4} -set_instance_parameter_value arria10_hps_0 {F2SDRAM_ADDRESS_WIDTH} {32} -set_instance_parameter_value arria10_hps_0 {DMA_Enable} {No No No No No No No No} -set_instance_parameter_value arria10_hps_0 {SECURITY_MODULE_Enable} {0} -set_instance_parameter_value arria10_hps_0 {EMAC0_SWITCH_Enable} {0} -set_instance_parameter_value arria10_hps_0 {EMAC1_SWITCH_Enable} {0} -set_instance_parameter_value arria10_hps_0 {EMAC2_SWITCH_Enable} {0} -set_instance_parameter_value arria10_hps_0 {F2SINTERRUPT_Enable} {1} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_CLOCKPERIPHERAL_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_CTI_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_DMA_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_EMAC0_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_EMAC1_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_EMAC2_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_FPGAMANAGER_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_GPIO_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_HMC_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_I2CEMAC0_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_I2CEMAC1_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_I2CEMAC2_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_I2C0_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_I2C1_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_L4TIMER_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_NAND_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_QSPI_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_SYSTIMER_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_SDMMC_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_SPIM0_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_SPIM1_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_SPIS0_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_SPIS1_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_SYSTEMMANAGER_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_UART0_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_UART1_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_USB0_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_USB1_Enable} {0} -set_instance_parameter_value arria10_hps_0 {S2FINTERRUPT_WATCHDOG_Enable} {0} -set_instance_parameter_value arria10_hps_0 {eosc1_clk_mhz} {25.0} -set_instance_parameter_value arria10_hps_0 {INTERNAL_OSCILLATOR_ENABLE} {60} -set_instance_parameter_value arria10_hps_0 {F2H_FREE_CLK_Enable} {0} -set_instance_parameter_value arria10_hps_0 {F2H_FREE_CLK_FREQ} {200} -set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK} {2.5} -set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK} {100} -set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK} {2.5} -set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK} {100} -set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_MD_CLK} {2.5} -set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_GTX_CLK} {100} -set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT} {100} -set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDMMC_CCLK} {100} -set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT} {100} -set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT} {100} -set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK} {100} -set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK} {100} -set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC0_CLK} {100} -set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC1_CLK} {100} -set_instance_parameter_value arria10_hps_0 {FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC2_CLK} {100} -set_instance_parameter_value arria10_hps_0 {MPU_CLK_VCCL} {0} -set_instance_parameter_value arria10_hps_0 {USE_DEFAULT_MPU_CLK} {0} -set_instance_parameter_value arria10_hps_0 {CUSTOM_MPU_CLK} {800} -set_instance_parameter_value arria10_hps_0 {H2F_USER0_CLK_Enable} {1} -set_instance_parameter_value arria10_hps_0 {H2F_USER0_CLK_FREQ} {175} -set_instance_parameter_value arria10_hps_0 {H2F_USER1_CLK_Enable} {0} -set_instance_parameter_value arria10_hps_0 {H2F_USER1_CLK_FREQ} {400} -set_instance_parameter_value arria10_hps_0 {HMC_PLL_REF_CLK} {800} -set_instance_parameter_value arria10_hps_0 {EMAC_PTP_REF_CLK} {100} -set_instance_parameter_value arria10_hps_0 {SDMMC_REF_CLK} {200} -set_instance_parameter_value arria10_hps_0 {GPIO_REF_CLK} {4} -set_instance_parameter_value arria10_hps_0 {L3_MAIN_FREE_CLK} {400} -set_instance_parameter_value arria10_hps_0 {L4_SYS_FREE_CLK} {1} -set_instance_parameter_value arria10_hps_0 {NOCDIV_L4MAINCLK} {0} -set_instance_parameter_value arria10_hps_0 {NOCDIV_L4MPCLK} {1} -set_instance_parameter_value arria10_hps_0 {NOCDIV_L4SPCLK} {2} -set_instance_parameter_value arria10_hps_0 {NOCDIV_CS_ATCLK} {0} -set_instance_parameter_value arria10_hps_0 {NOCDIV_CS_PDBGCLK} {1} -set_instance_parameter_value arria10_hps_0 {NOCDIV_CS_TRACECLK} {0} -set_instance_parameter_value arria10_hps_0 {HPS_DIV_GPIO_FREQ} {125} -set_instance_parameter_value arria10_hps_0 {EMAC0_CLK} {250} -set_instance_parameter_value arria10_hps_0 {EMAC1_CLK} {250} -set_instance_parameter_value arria10_hps_0 {EMAC2_CLK} {250} -set_instance_parameter_value arria10_hps_0 {DISABLE_PERI_PLL} {0} -set_instance_parameter_value arria10_hps_0 {OVERIDE_PERI_PLL} {0} -set_instance_parameter_value arria10_hps_0 {PERI_PLL_MANUAL_VCO_FREQ} {2000} -set_instance_parameter_value arria10_hps_0 {CLK_MAIN_PLL_SOURCE2} {0} -set_instance_parameter_value arria10_hps_0 {CLK_PERI_PLL_SOURCE2} {0} -set_instance_parameter_value arria10_hps_0 {CLK_MPU_SOURCE} {0} -set_instance_parameter_value arria10_hps_0 {CLK_MPU_CNT} {0} -set_instance_parameter_value arria10_hps_0 {CLK_NOC_SOURCE} {0} -set_instance_parameter_value arria10_hps_0 {CLK_NOC_CNT} {0} -set_instance_parameter_value arria10_hps_0 {CLK_S2F_USER0_SOURCE} {0} -set_instance_parameter_value arria10_hps_0 {CLK_S2F_USER1_SOURCE} {0} -set_instance_parameter_value arria10_hps_0 {CLK_HMC_PLL_SOURCE} {0} -set_instance_parameter_value arria10_hps_0 {CLK_EMAC_PTP_SOURCE} {1} -set_instance_parameter_value arria10_hps_0 {CLK_GPIO_SOURCE} {1} -set_instance_parameter_value arria10_hps_0 {CLK_SDMMC_SOURCE} {1} -set_instance_parameter_value arria10_hps_0 {CLK_EMACA_SOURCE} {1} -set_instance_parameter_value arria10_hps_0 {CLK_EMACB_SOURCE} {1} -set_instance_parameter_value arria10_hps_0 {H2F_PENDING_RST_Enable} {0} -set_instance_parameter_value arria10_hps_0 {H2F_COLD_RST_Enable} {0} -set_instance_parameter_value arria10_hps_0 {F2H_DBG_RST_Enable} {0} -set_instance_parameter_value arria10_hps_0 {F2H_WARM_RST_Enable} {0} -set_instance_parameter_value arria10_hps_0 {F2H_COLD_RST_Enable} {1} -set_instance_parameter_value arria10_hps_0 {TESTIOCTRL_MAINCLKSEL} {8} -set_instance_parameter_value arria10_hps_0 {TESTIOCTRL_PERICLKSEL} {8} -set_instance_parameter_value arria10_hps_0 {TESTIOCTRL_DEBUGCLKSEL} {16} -set_instance_parameter_value arria10_hps_0 {EMIF_CONDUIT_Enable} {1} -set_instance_parameter_value arria10_hps_0 {EMIF_BYPASS_CHECK} {0} -set_instance_parameter_value arria10_hps_0 {EMAC0_PTP} {0} -set_instance_parameter_value arria10_hps_0 {EMAC1_PTP} {0} -set_instance_parameter_value arria10_hps_0 {EMAC2_PTP} {0} -set_instance_parameter_value arria10_hps_0 {EMAC0_PinMuxing} {IO} -set_instance_parameter_value arria10_hps_0 {EMAC0_Mode} {RGMII_with_MDIO} -set_instance_parameter_value arria10_hps_0 {EMAC1_PinMuxing} {Unused} -set_instance_parameter_value arria10_hps_0 {EMAC1_Mode} {N/A} -set_instance_parameter_value arria10_hps_0 {EMAC2_PinMuxing} {Unused} -set_instance_parameter_value arria10_hps_0 {EMAC2_Mode} {N/A} -set_instance_parameter_value arria10_hps_0 {NAND_PinMuxing} {Unused} -set_instance_parameter_value arria10_hps_0 {NAND_Mode} {N/A} -set_instance_parameter_value arria10_hps_0 {QSPI_PinMuxing} {Unused} -set_instance_parameter_value arria10_hps_0 {QSPI_Mode} {N/A} -set_instance_parameter_value arria10_hps_0 {SDMMC_PinMuxing} {IO} -set_instance_parameter_value arria10_hps_0 {SDMMC_Mode} {8-bit} -set_instance_parameter_value arria10_hps_0 {USB0_PinMuxing} {IO} -set_instance_parameter_value arria10_hps_0 {USB0_Mode} {default} -set_instance_parameter_value arria10_hps_0 {USB1_PinMuxing} {Unused} -set_instance_parameter_value arria10_hps_0 {USB1_Mode} {N/A} -set_instance_parameter_value arria10_hps_0 {SPIM0_PinMuxing} {Unused} -set_instance_parameter_value arria10_hps_0 {SPIM0_Mode} {N/A} -set_instance_parameter_value arria10_hps_0 {SPIM1_PinMuxing} {Unused} -set_instance_parameter_value arria10_hps_0 {SPIM1_Mode} {N/A} -set_instance_parameter_value arria10_hps_0 {SPIS0_PinMuxing} {Unused} -set_instance_parameter_value arria10_hps_0 {SPIS0_Mode} {N/A} -set_instance_parameter_value arria10_hps_0 {SPIS1_PinMuxing} {Unused} -set_instance_parameter_value arria10_hps_0 {SPIS1_Mode} {N/A} -set_instance_parameter_value arria10_hps_0 {UART0_PinMuxing} {Unused} -set_instance_parameter_value arria10_hps_0 {UART0_Mode} {N/A} -set_instance_parameter_value arria10_hps_0 {UART1_PinMuxing} {IO} -set_instance_parameter_value arria10_hps_0 {UART1_Mode} {No_flow_control} -set_instance_parameter_value arria10_hps_0 {I2C0_PinMuxing} {Unused} -set_instance_parameter_value arria10_hps_0 {I2C0_Mode} {N/A} -set_instance_parameter_value arria10_hps_0 {I2C1_PinMuxing} {IO} -set_instance_parameter_value arria10_hps_0 {I2C1_Mode} {default} -set_instance_parameter_value arria10_hps_0 {I2CEMAC0_PinMuxing} {Unused} -set_instance_parameter_value arria10_hps_0 {I2CEMAC0_Mode} {N/A} -set_instance_parameter_value arria10_hps_0 {I2CEMAC1_PinMuxing} {Unused} -set_instance_parameter_value arria10_hps_0 {I2CEMAC1_Mode} {N/A} -set_instance_parameter_value arria10_hps_0 {I2CEMAC2_PinMuxing} {Unused} -set_instance_parameter_value arria10_hps_0 {I2CEMAC2_Mode} {N/A} -set_instance_parameter_value arria10_hps_0 {TRACE_PinMuxing} {Unused} -set_instance_parameter_value arria10_hps_0 {TRACE_Mode} {N/A} -set_instance_parameter_value arria10_hps_0 {CM_PinMuxing} {Unused} -set_instance_parameter_value arria10_hps_0 {CM_Mode} {N/A} -set_instance_parameter_value arria10_hps_0 {PLL_CLK0} {Unused} -set_instance_parameter_value arria10_hps_0 {PLL_CLK1} {Unused} -set_instance_parameter_value arria10_hps_0 {PLL_CLK2} {Unused} -set_instance_parameter_value arria10_hps_0 {PLL_CLK3} {Unused} -set_instance_parameter_value arria10_hps_0 {PLL_CLK4} {Unused} -set_instance_parameter_value arria10_hps_0 {HPS_IO_Enable} {SDMMC:D0 SDMMC:CMD SDMMC:CCLK SDMMC:D1 SDMMC:D2 SDMMC:D3 NONE NONE SDMMC:D4 SDMMC:D5 SDMMC:D6 SDMMC:D7 UART1:TX UART1:RX USB0:CLK USB0:STP USB0:DIR USB0:DATA0 USB0:DATA1 USB0:NXT USB0:DATA2 USB0:DATA3 USB0:DATA4 USB0:DATA5 USB0:DATA6 USB0:DATA7 EMAC0:TX_CLK EMAC0:TX_CTL EMAC0:RX_CLK EMAC0:RX_CTL EMAC0:TXD0 EMAC0:TXD1 EMAC0:RXD0 EMAC0:RXD1 EMAC0:TXD2 EMAC0:TXD3 EMAC0:RXD2 EMAC0:RXD3 NONE NONE NONE NONE NONE GPIO NONE NONE NONE NONE MDIO0:MDIO MDIO0:MDC I2C1:SDA I2C1:SCL GPIO NONE GPIO GPIO NONE NONE NONE NONE NONE NONE} +variable hps_io_list -add_instance emif_a10_hps_0 altera_emif_a10_hps 16.0 -set_instance_parameter_value emif_a10_hps_0 {PROTOCOL_ENUM} {PROTOCOL_DDR4} -set_instance_parameter_value emif_a10_hps_0 {IS_ED_SLAVE} {0} -set_instance_parameter_value emif_a10_hps_0 {INTERNAL_TESTING_MODE} {0} -set_instance_parameter_value emif_a10_hps_0 {PLL_ADD_EXTRA_CLKS} {0} -set_instance_parameter_value emif_a10_hps_0 {PLL_USER_NUM_OF_EXTRA_CLKS} {0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0} {0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1} {0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2} {0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3} {0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4} {0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5} {100.0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5} {100.0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5} {0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5} {0.0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5} {0.0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5} {0.0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5} {50.0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5} {50.0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6} {100.0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6} {100.0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6} {0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6} {0.0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6} {0.0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6} {0.0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6} {50.0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6} {50.0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7} {100.0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7} {100.0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7} {0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7} {0.0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7} {0.0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7} {0.0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7} {50.0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7} {50.0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8} {100.0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8} {100.0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8} {0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8} {0.0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8} {0.0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8} {0.0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8} {50.0} -set_instance_parameter_value emif_a10_hps_0 {PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8} {50.0} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_CONFIG_ENUM} {CONFIG_PHY_AND_HARD_CTRL} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_PING_PONG_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_MEM_CLK_FREQ_MHZ} {1066.667} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_DEFAULT_REF_CLK_FREQ} {0} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_REF_CLK_FREQ_MHZ} {133.333} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_REF_CLK_JITTER_PS} {10.0} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_RATE_ENUM} {RATE_HALF} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_IO_VOLTAGE} {1.5} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_DEFAULT_IO} {1} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_HPS_ENABLE_EARLY_RELEASE} {0} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_CAL_ADDR0} {0} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_CAL_ADDR1} {8} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_CAL_ENABLE_NON_DES} {1} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_AC_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_AC_MODE_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_AC_SLEW_RATE_ENUM} {SLEW_RATE_FAST} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_CK_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_CK_MODE_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_CK_SLEW_RATE_ENUM} {SLEW_RATE_FAST} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_DATA_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_DATA_OUT_MODE_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_DATA_IN_MODE_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR3_USER_RZQ_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_CONFIG_ENUM} {CONFIG_PHY_AND_HARD_CTRL} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_PING_PONG_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_MEM_CLK_FREQ_MHZ} {1066.667} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_DEFAULT_REF_CLK_FREQ} {0} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_REF_CLK_FREQ_MHZ} {133.333} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_REF_CLK_JITTER_PS} {10.0} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_RATE_ENUM} {RATE_HALF} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_IO_VOLTAGE} {1.2} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_DEFAULT_IO} {0} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_STARTING_VREFIN} {70.0} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_HPS_ENABLE_EARLY_RELEASE} {0} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_AC_IO_STD_ENUM} {IO_STD_SSTL_12} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_AC_MODE_ENUM} {OUT_OCT_40_CAL} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_AC_SLEW_RATE_ENUM} {SLEW_RATE_FAST} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_CK_IO_STD_ENUM} {IO_STD_SSTL_12} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_CK_MODE_ENUM} {OUT_OCT_40_CAL} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_CK_SLEW_RATE_ENUM} {SLEW_RATE_FAST} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_DATA_IO_STD_ENUM} {IO_STD_POD_12} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_DATA_OUT_MODE_ENUM} {OUT_OCT_34_CAL} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_DATA_IN_MODE_ENUM} {IN_OCT_60_CAL} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM} {IO_STD_CMOS_12} -set_instance_parameter_value emif_a10_hps_0 {PHY_DDR4_USER_RZQ_IO_STD_ENUM} {IO_STD_CMOS_12} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_CONFIG_ENUM} {CONFIG_PHY_AND_SOFT_CTRL} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_PING_PONG_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_MEM_CLK_FREQ_MHZ} {633.333} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_DEFAULT_REF_CLK_FREQ} {1} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_REF_CLK_FREQ_MHZ} {-1.0} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_REF_CLK_JITTER_PS} {10.0} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_RATE_ENUM} {RATE_HALF} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_IO_VOLTAGE} {1.5} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_DEFAULT_IO} {1} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_HPS_ENABLE_EARLY_RELEASE} {0} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_AC_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_AC_MODE_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_AC_SLEW_RATE_ENUM} {SLEW_RATE_FAST} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_CK_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_CK_MODE_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_CK_SLEW_RATE_ENUM} {SLEW_RATE_FAST} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_DATA_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_DATA_OUT_MODE_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_DATA_IN_MODE_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR2_USER_RZQ_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_CONFIG_ENUM} {CONFIG_PHY_AND_SOFT_CTRL} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_PING_PONG_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_MEM_CLK_FREQ_MHZ} {1066.667} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_DEFAULT_REF_CLK_FREQ} {1} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_REF_CLK_FREQ_MHZ} {-1.0} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_REF_CLK_JITTER_PS} {10.0} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_RATE_ENUM} {RATE_QUARTER} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_IO_VOLTAGE} {1.2} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_DEFAULT_IO} {1} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_STARTING_VREFIN} {70.0} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_HPS_ENABLE_EARLY_RELEASE} {0} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_AC_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_AC_MODE_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_AC_SLEW_RATE_ENUM} {SLEW_RATE_FAST} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_CK_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_CK_MODE_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_CK_SLEW_RATE_ENUM} {SLEW_RATE_FAST} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_DATA_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_DATA_OUT_MODE_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_DATA_IN_MODE_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_QDR4_USER_RZQ_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_CONFIG_ENUM} {CONFIG_PHY_AND_SOFT_CTRL} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_PING_PONG_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_MEM_CLK_FREQ_MHZ} {533.333} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_DEFAULT_REF_CLK_FREQ} {1} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_REF_CLK_FREQ_MHZ} {-1.0} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_REF_CLK_JITTER_PS} {10.0} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_RATE_ENUM} {RATE_HALF} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_IO_VOLTAGE} {1.8} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_DEFAULT_IO} {1} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_HPS_ENABLE_EARLY_RELEASE} {0} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_AC_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_AC_MODE_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_AC_SLEW_RATE_ENUM} {SLEW_RATE_FAST} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_CK_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_CK_MODE_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_CK_SLEW_RATE_ENUM} {SLEW_RATE_FAST} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_DATA_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_DATA_OUT_MODE_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_DATA_IN_MODE_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD2_USER_RZQ_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_CONFIG_ENUM} {CONFIG_PHY_ONLY} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_PING_PONG_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_MEM_CLK_FREQ_MHZ} {1066.667} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_DEFAULT_REF_CLK_FREQ} {1} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_REF_CLK_FREQ_MHZ} {-1.0} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_REF_CLK_JITTER_PS} {10.0} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_RATE_ENUM} {RATE_QUARTER} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_IO_VOLTAGE} {1.2} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_DEFAULT_IO} {1} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_HPS_ENABLE_EARLY_RELEASE} {0} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_AC_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_AC_MODE_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_AC_SLEW_RATE_ENUM} {SLEW_RATE_FAST} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_CK_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_CK_MODE_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_CK_SLEW_RATE_ENUM} {SLEW_RATE_FAST} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_DATA_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_DATA_OUT_MODE_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_DATA_IN_MODE_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_RLD3_USER_RZQ_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_CONFIG_ENUM} {CONFIG_PHY_AND_HARD_CTRL} -set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_PING_PONG_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_MEM_CLK_FREQ_MHZ} {800.0} -set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_DEFAULT_REF_CLK_FREQ} {1} -set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ} {-1.0} -set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_REF_CLK_JITTER_PS} {10.0} -set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_RATE_ENUM} {RATE_HALF} -set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_CORE_CLKS_SHARING_ENUM} {CORE_CLKS_SHARING_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_IO_VOLTAGE} {1.2} -set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_DEFAULT_IO} {1} -set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_HPS_ENABLE_EARLY_RELEASE} {0} -set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_PERIODIC_OCT_RECAL_ENUM} {PERIODIC_OCT_RECAL_AUTO} -set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_AC_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_AC_MODE_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM} {SLEW_RATE_FAST} -set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_CK_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_CK_MODE_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM} {SLEW_RATE_FAST} -set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_DATA_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_DATA_IN_MODE_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {PHY_LPDDR3_USER_RZQ_IO_STD_ENUM} {unset} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_FORMAT_ENUM} {MEM_FORMAT_UDIMM} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_DQ_WIDTH} {32} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_DQ_PER_DQS} {8} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_DISCRETE_CS_WIDTH} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_NUM_OF_DIMMS} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_RANKS_PER_DIMM} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_CKE_PER_DIMM} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_CK_WIDTH} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_ROW_ADDR_WIDTH} {15} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_COL_ADDR_WIDTH} {10} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_BANK_ADDR_WIDTH} {3} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_DM_EN} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_DISCRETE_MIRROR_ADDRESSING_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_MIRROR_ADDRESSING_EN} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_HIDE_ADV_MR_SETTINGS} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_RDIMM_CONFIG} {0000000000000000} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_LRDIMM_EXTENDED_CONFIG} {000000000000000000} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_ALERT_N_PLACEMENT_ENUM} {DDR3_ALERT_N_PLACEMENT_AC_LANES} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_ALERT_N_DQS_GROUP} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_BL_ENUM} {DDR3_BL_BL8} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_BT_ENUM} {DDR3_BT_SEQUENTIAL} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_ASR_ENUM} {DDR3_ASR_MANUAL} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_SRT_ENUM} {DDR3_SRT_NORMAL} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_PD_ENUM} {DDR3_PD_OFF} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_DRV_STR_ENUM} {DDR3_DRV_STR_RZQ_7} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_DLL_EN} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_RTT_NOM_ENUM} {DDR3_RTT_NOM_ODT_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_RTT_WR_ENUM} {DDR3_RTT_WR_RZQ_4} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_WTCL} {10} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_ATCL_ENUM} {DDR3_ATCL_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TCL} {14} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_USE_DEFAULT_ODT} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODTN_1X1} {Rank\ 0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODT0_1X1} {off} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODTN_1X1} {Rank\ 0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODT0_1X1} {on} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODTN_2X2} {Rank\ 0 Rank\ 1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODT0_2X2} {off off} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODT1_2X2} {off off} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODTN_2X2} {Rank\ 0 Rank\ 1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODT0_2X2} {on off} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODT1_2X2} {off on} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODTN_4X2} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODT0_4X2} {off off on on} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODT1_4X2} {on on off off} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODTN_4X2} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODT0_4X2} {off off on on} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODT1_4X2} {on on off off} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODTN_4X4} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODT0_4X4} {off off off off} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODT1_4X4} {off off on on} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODT2_4X4} {off off off off} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_R_ODT3_4X4} {on on off off} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODTN_4X4} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODT0_4X4} {on on off off} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODT1_4X4} {off off on on} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODT2_4X4} {off off on on} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_W_ODT3_4X4} {on on off off} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_SPEEDBIN_ENUM} {DDR3_SPEEDBIN_2133} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TIS_PS} {60} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TIS_AC_MV} {135} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TIH_PS} {95} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TIH_DC_MV} {100} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TDS_PS} {53} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TDS_AC_MV} {135} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TDH_PS} {55} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TDH_DC_MV} {100} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TDQSQ_PS} {75} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TQH_CYC} {0.38} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TDQSCK_PS} {180} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TDQSS_CYC} {0.27} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TQSH_CYC} {0.4} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TDSH_CYC} {0.18} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TWLS_PS} {125.0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TWLH_PS} {125.0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TDSS_CYC} {0.18} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TINIT_US} {500} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TMRD_CK_CYC} {4} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TRAS_NS} {33.0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TRCD_NS} {13.09} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TRP_NS} {13.09} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TREFI_US} {7.8} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TRFC_NS} {160.0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TWR_NS} {15.0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TWTR_CYC} {8} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TFAW_NS} {25.0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TRRD_CYC} {6} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR3_TRTP_CYC} {8} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_FORMAT_ENUM} {MEM_FORMAT_UDIMM} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DQ_WIDTH} {32} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DQ_PER_DQS} {8} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DISCRETE_CS_WIDTH} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_NUM_OF_DIMMS} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_RANKS_PER_DIMM} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_CKE_PER_DIMM} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_CK_WIDTH} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_ROW_ADDR_WIDTH} {15} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_COL_ADDR_WIDTH} {10} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_BANK_ADDR_WIDTH} {2} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_BANK_GROUP_WIDTH} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_CHIP_ID_WIDTH} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DM_EN} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_ALERT_PAR_EN} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_ALERT_N_PLACEMENT_ENUM} {DDR4_ALERT_N_PLACEMENT_DATA_LANES} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_ALERT_N_DQS_GROUP} {3} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_ALERT_N_AC_LANE} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_ALERT_N_AC_PIN} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DISCRETE_MIRROR_ADDRESSING_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_MIRROR_ADDRESSING_EN} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_HIDE_ADV_MR_SETTINGS} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_BL_ENUM} {DDR4_BL_BL8} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_BT_ENUM} {DDR4_BT_SEQUENTIAL} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TCL} {20} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_RTT_NOM_ENUM} {DDR4_RTT_NOM_RZQ_6} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DLL_EN} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_ATCL_ENUM} {DDR4_ATCL_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DRV_STR_ENUM} {DDR4_DRV_STR_RZQ_7} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_ASR_ENUM} {DDR4_ASR_MANUAL_NORMAL} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_RTT_WR_ENUM} {DDR4_RTT_WR_ODT_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_WTCL} {18} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_WRITE_CRC} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_GEARDOWN} {DDR4_GEARDOWN_HR} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_PER_DRAM_ADDR} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TEMP_SENSOR_READOUT} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_FINE_GRANULARITY_REFRESH} {DDR4_FINE_REFRESH_FIXED_1X} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_MPR_READ_FORMAT} {DDR4_MPR_READ_FORMAT_SERIAL} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_MAX_POWERDOWN} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE} {DDR4_TEMP_CONTROLLED_RFSH_NORMAL} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_INTERNAL_VREFDQ_MONITOR} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_CAL_MODE} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SELF_RFSH_ABORT} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_READ_PREAMBLE_TRAINING} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_READ_PREAMBLE} {2} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_WRITE_PREAMBLE} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_AC_PARITY_LATENCY} {DDR4_AC_PARITY_LATENCY_DISABLE} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_ODT_IN_POWERDOWN} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_RTT_PARK} {DDR4_RTT_PARK_ODT_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_AC_PERSISTENT_ERROR} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_WRITE_DBI} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_READ_DBI} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DEFAULT_VREFOUT} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_USER_VREFDQ_TRAINING_VALUE} {56.0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_USER_VREFDQ_TRAINING_RANGE} {DDR4_VREFDQ_TRAINING_RANGE_1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_RCD_CA_IBT_ENUM} {DDR4_RCD_CA_IBT_100} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_RCD_CS_IBT_ENUM} {DDR4_RCD_CS_IBT_100} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_RCD_CKE_IBT_ENUM} {DDR4_RCD_CKE_IBT_100} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_RCD_ODT_IBT_ENUM} {DDR4_RCD_ODT_IBT_100} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DB_RTT_NOM_ENUM} {DDR4_DB_RTT_NOM_ODT_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DB_RTT_WR_ENUM} {DDR4_DB_RTT_WR_RZQ_3} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DB_RTT_PARK_ENUM} {DDR4_DB_RTT_PARK_ODT_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_DB_DQ_DRV_ENUM} {DDR4_DB_DRV_STR_RZQ_7} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_137_RCD_CA_DRV} {101} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_138_RCD_CK_DRV} {5} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_140_DRAM_VREFDQ_R0} {29} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_141_DRAM_VREFDQ_R1} {29} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_142_DRAM_VREFDQ_R2} {29} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_143_DRAM_VREFDQ_R3} {29} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_144_DB_VREFDQ} {37} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_145_DB_MDQ_DRV} {21} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_148_DRAM_DRV} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM} {20} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_152_DRAM_RTT_PARK} {39} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_133_RCD_DB_VENDOR_LSB} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_134_RCD_DB_VENDOR_MSB} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_135_RCD_REV} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPD_139_DB_REV} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_LRDIMM_ODT_LESS_BS} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM} {240} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_USE_DEFAULT_ODT} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODTN_1X1} {Rank\ 0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODT0_1X1} {off} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODTN_1X1} {Rank\ 0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODT0_1X1} {on} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODTN_2X2} {Rank\ 0 Rank\ 1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODT0_2X2} {off off} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODT1_2X2} {off off} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODTN_2X2} {Rank\ 0 Rank\ 1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODT0_2X2} {on off} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODT1_2X2} {off on} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODTN_4X2} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODT0_4X2} {off off on on} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODT1_4X2} {on on off off} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODTN_4X2} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODT0_4X2} {off off on on} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODT1_4X2} {on on off off} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODTN_4X4} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODT0_4X4} {off off off off} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODT1_4X4} {off off on on} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODT2_4X4} {off off off off} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_R_ODT3_4X4} {on on off off} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODTN_4X4} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODT0_4X4} {on on off off} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODT1_4X4} {off off on on} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODT2_4X4} {off off on on} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_W_ODT3_4X4} {on on off off} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_SPEEDBIN_ENUM} {DDR4_SPEEDBIN_2666} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TIS_PS} {60} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TIS_AC_MV} {100} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TIH_PS} {95} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TIH_DC_MV} {75} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TDIVW_TOTAL_UI} {0.2} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_VDIVW_TOTAL} {136} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TDQSQ_UI} {0.16} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TQH_UI} {0.76} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TDVWP_UI} {0.72} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TDQSCK_PS} {165} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TDQSS_CYC} {0.27} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TQSH_CYC} {0.38} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TDSH_CYC} {0.18} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TDSS_CYC} {0.18} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TWLS_PS} {108.0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TWLH_PS} {108.0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TINIT_US} {500} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TMRD_CK_CYC} {8} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TRAS_NS} {32.0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TRCD_NS} {14.25} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TRP_NS} {14.25} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TREFI_US} {7.8} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TRFC_NS} {260.0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TWR_NS} {15.0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TWTR_L_CYC} {10} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TWTR_S_CYC} {4} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TFAW_NS} {30.0} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TRRD_L_CYC} {8} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TRRD_S_CYC} {7} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TCCD_L_CYC} {6} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TCCD_S_CYC} {4} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TDIVW_DJ_CYC} {0.1} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TDQSQ_PS} {66} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_TQH_CYC} {0.38} -set_instance_parameter_value emif_a10_hps_0 {MEM_DDR4_LRDIMM_VREFDQ_VALUE} {1D} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_WIDTH_EXPANDED} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_DATA_PER_DEVICE} {36} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_ADDR_WIDTH} {19} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_BWS_EN} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_BL} {4} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_SPEEDBIN_ENUM} {QDR2_SPEEDBIN_633} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_TRL_CYC} {2.5} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_TSA_NS} {0.23} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_THA_NS} {0.18} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_TSD_NS} {0.23} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_THD_NS} {0.18} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_TCQD_NS} {0.09} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_TCQDOH_NS} {-0.09} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_INTERNAL_JITTER_NS} {0.08} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_TCQH_NS} {0.71} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR2_TCCQO_NS} {0.45} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_WIDTH_EXPANDED} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_DQ_PER_PORT_PER_DEVICE} {36} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_ADDR_WIDTH} {21} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_CK_ODT_MODE_ENUM} {QDR4_ODT_25_PCT} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_AC_ODT_MODE_ENUM} {QDR4_ODT_25_PCT} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_DATA_ODT_MODE_ENUM} {QDR4_ODT_25_PCT} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM} {QDR4_OUTPUT_DRIVE_25_PCT} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM} {QDR4_OUTPUT_DRIVE_25_PCT} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_DATA_INV_ENA} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_ADDR_INV_ENA} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_SPEEDBIN_ENUM} {QDR4_SPEEDBIN_2133} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_TISH_PS} {150} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_TQKQ_MAX_PS} {75} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_TQH_CYC} {0.4} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_TCKDK_MAX_PS} {150} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_TCKDK_MIN_PS} {-150} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_TCKQK_MAX_PS} {225} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_TASH_PS} {170} -set_instance_parameter_value emif_a10_hps_0 {MEM_QDR4_TCSH_PS} {170} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_WIDTH_EXPANDED} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_DQ_PER_DEVICE} {9} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_ADDR_WIDTH} {21} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_BANK_ADDR_WIDTH} {3} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_DM_EN} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_BL} {4} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_CONFIG_ENUM} {RLD2_CONFIG_TRC_8_TRL_8_TWL_9} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_DRIVE_IMPEDENCE_ENUM} {RLD2_DRIVE_IMPEDENCE_INTERNAL_50} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_ODT_MODE_ENUM} {RLD2_ODT_ON} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_SPEEDBIN_ENUM} {RLD2_SPEEDBIN_18} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_REFRESH_INTERVAL_US} {0.24} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TCKH_CYC} {0.45} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TQKH_HCYC} {0.9} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TAS_NS} {0.3} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TAH_NS} {0.3} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TDS_NS} {0.17} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TDH_NS} {0.17} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TQKQ_MAX_NS} {0.12} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TQKQ_MIN_NS} {-0.12} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TCKDK_MAX_NS} {0.3} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TCKDK_MIN_NS} {-0.3} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD2_TCKQK_MAX_NS} {0.2} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_WIDTH_EXPANDED} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_DEPTH_EXPANDED} {0} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_DQ_PER_DEVICE} {36} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_ADDR_WIDTH} {20} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_BANK_ADDR_WIDTH} {4} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_DM_EN} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_BL} {2} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_DATA_LATENCY_MODE_ENUM} {RLD3_DL_RL16_WL17} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_T_RC_MODE_ENUM} {RLD3_TRC_9} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM} {RLD3_OUTPUT_DRIVE_40} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_ODT_MODE_ENUM} {RLD3_ODT_40} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_AREF_PROTOCOL_ENUM} {RLD3_AREF_BAC} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_WRITE_PROTOCOL_ENUM} {RLD3_WRITE_1BANK} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_SPEEDBIN_ENUM} {RLD3_SPEEDBIN_093E} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TDS_PS} {-30} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TDS_AC_MV} {150} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TDH_PS} {5} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TDH_DC_MV} {100} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TQKQ_MAX_PS} {75} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TQH_CYC} {0.38} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TCKDK_MAX_CYC} {0.27} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TCKDK_MIN_CYC} {-0.27} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TCKQK_MAX_PS} {135} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TIS_PS} {85} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TIS_AC_MV} {150} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TIH_PS} {65} -set_instance_parameter_value emif_a10_hps_0 {MEM_RLD3_TIH_DC_MV} {100} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_DQ_WIDTH} {32} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_DISCRETE_CS_WIDTH} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_CK_WIDTH} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_DM_EN} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_ROW_ADDR_WIDTH} {15} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_COL_ADDR_WIDTH} {10} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_BANK_ADDR_WIDTH} {3} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_BL} {LPDDR3_BL_BL8} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_DATA_LATENCY} {LPDDR3_DL_RL12_WL6} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_NWR} {LPDDR3_NWR_NWR10} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_DRV_STR} {LPDDR3_DRV_STR_40D_40U} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_DQODT} {LPDDR3_DQODT_DISABLE} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_PDODT} {LPDDR3_PDODT_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_USE_DEFAULT_ODT} {1} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODTN_1X1} {Rank\ 0} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODT0_1X1} {off} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODTN_1X1} {Rank\ 0} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODT0_1X1} {on} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODTN_2X2} {Rank\ 0 Rank\ 1} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODT0_2X2} {off off} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODT1_2X2} {off off} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODTN_2X2} {Rank\ 0 Rank\ 1} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODT0_2X2} {on off} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODT1_2X2} {off on} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODTN_4X4} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODT0_4X4} {off off on on} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODT1_4X4} {off off off off} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODT2_4X4} {on on off off} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_R_ODT3_4X4} {off off off off} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODTN_4X4} {Rank\ 0 Rank\ 1 Rank\ 2 Rank\ 3} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODT0_4X4} {on on on on} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODT1_4X4} {off off off off} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODT2_4X4} {on on on on} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_W_ODT3_4X4} {off off off off} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_SPEEDBIN_ENUM} {LPDDR3_SPEEDBIN_1600} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TIS_PS} {75} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TIS_AC_MV} {150} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TIH_PS} {100} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TIH_DC_MV} {100} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TDS_PS} {75} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TDS_AC_MV} {150} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TDH_PS} {100} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TDH_DC_MV} {100} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TDQSQ_PS} {135} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TQH_CYC} {0.38} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TDQSCKDL} {614} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TDQSS_CYC} {1.25} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TQSH_CYC} {0.38} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TDSH_CYC} {0.2} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TWLS_PS} {175.0} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TWLH_PS} {175.0} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TDSS_CYC} {0.2} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TINIT_US} {500} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TMRR_CK_CYC} {4} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TMRW_CK_CYC} {10} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TRAS_NS} {42.5} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TRCD_NS} {18.75} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TRP_NS} {18.75} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TREFI_US} {3.9} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TRFC_NS} {210.0} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TWR_NS} {15.0} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TWTR_CYC} {4} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TFAW_NS} {50.0} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TRRD_CYC} {2} -set_instance_parameter_value emif_a10_hps_0 {MEM_LPDDR3_TRTP_CYC} {4} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USE_DEFAULT_SLEW_RATES} {1} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USE_DEFAULT_ISI_VALUES} {1} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_CK_SLEW_RATE} {4.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_AC_SLEW_RATE} {2.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_RCLK_SLEW_RATE} {5.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_WCLK_SLEW_RATE} {4.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_RDATA_SLEW_RATE} {2.5} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_WDATA_SLEW_RATE} {2.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_AC_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_RCLK_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_WCLK_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_RDATA_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_USER_WDATA_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED} {0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED} {1} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_DQS_TO_CK_SKEW_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS} {0.05} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_SKEW_BETWEEN_DQS_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_AC_TO_CK_SKEW_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_MAX_CK_DELAY_NS} {0.6} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR3_MAX_DQS_DELAY_NS} {0.6} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USE_DEFAULT_SLEW_RATES} {1} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USE_DEFAULT_ISI_VALUES} {1} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_CK_SLEW_RATE} {4.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_AC_SLEW_RATE} {2.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_RCLK_SLEW_RATE} {8.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_WCLK_SLEW_RATE} {4.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_RDATA_SLEW_RATE} {4.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_WDATA_SLEW_RATE} {2.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_AC_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_RCLK_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_WCLK_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_RDATA_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_USER_WDATA_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED} {1} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED} {0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_DQS_TO_CK_SKEW_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS} {0.05} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_SKEW_BETWEEN_DQS_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_AC_TO_CK_SKEW_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_MAX_CK_DELAY_NS} {0.6} -set_instance_parameter_value emif_a10_hps_0 {BOARD_DDR4_MAX_DQS_DELAY_NS} {0.6} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USE_DEFAULT_SLEW_RATES} {1} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USE_DEFAULT_ISI_VALUES} {1} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_K_SLEW_RATE} {4.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_AC_SLEW_RATE} {2.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_RCLK_SLEW_RATE} {4.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_RDATA_SLEW_RATE} {2.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_WDATA_SLEW_RATE} {2.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_AC_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_RCLK_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_WCLK_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_RDATA_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_USER_WDATA_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED} {0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED} {0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED} {1} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_BRD_SKEW_WITHIN_D_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_AC_TO_K_SKEW_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR2_MAX_K_DELAY_NS} {0.6} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USE_DEFAULT_SLEW_RATES} {1} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USE_DEFAULT_ISI_VALUES} {1} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_CK_SLEW_RATE} {4.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_AC_SLEW_RATE} {2.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_RCLK_SLEW_RATE} {5.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_WCLK_SLEW_RATE} {4.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_RDATA_SLEW_RATE} {2.5} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_WDATA_SLEW_RATE} {2.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_AC_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_RCLK_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_WCLK_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_RDATA_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_USER_WDATA_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED} {0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED} {1} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_DK_TO_CK_SKEW_NS} {-0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS} {0.05} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_SKEW_BETWEEN_DK_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_AC_TO_CK_SKEW_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_MAX_CK_DELAY_NS} {0.6} -set_instance_parameter_value emif_a10_hps_0 {BOARD_QDR4_MAX_DK_DELAY_NS} {0.6} -set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USE_DEFAULT_SLEW_RATES} {1} -set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USE_DEFAULT_ISI_VALUES} {1} -set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_CK_SLEW_RATE} {4.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_AC_SLEW_RATE} {2.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_RCLK_SLEW_RATE} {7.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_WCLK_SLEW_RATE} {4.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_RDATA_SLEW_RATE} {3.5} -set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_WDATA_SLEW_RATE} {2.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_AC_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_RCLK_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_WCLK_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_RDATA_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_USER_WDATA_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED} {0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED} {1} -set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_DK_TO_CK_SKEW_NS} {-0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS} {0.05} -set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_SKEW_BETWEEN_DK_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_AC_TO_CK_SKEW_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_MAX_CK_DELAY_NS} {0.6} -set_instance_parameter_value emif_a10_hps_0 {BOARD_RLD3_MAX_DK_DELAY_NS} {0.6} -set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES} {1} -set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES} {1} -set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_CK_SLEW_RATE} {4.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_AC_SLEW_RATE} {2.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_RCLK_SLEW_RATE} {4.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_WCLK_SLEW_RATE} {4.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_RDATA_SLEW_RATE} {2.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_WDATA_SLEW_RATE} {2.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_AC_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_RCLK_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_WCLK_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_RDATA_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_USER_WDATA_ISI_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED} {0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED} {1} -set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_DQS_TO_CK_SKEW_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS} {0.05} -set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS} {0.02} -set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_AC_TO_CK_SKEW_NS} {0.0} -set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_MAX_CK_DELAY_NS} {0.6} -set_instance_parameter_value emif_a10_hps_0 {BOARD_LPDDR3_MAX_DQS_DELAY_NS} {0.6} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_ST} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_SELF_REFRESH_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_AUTO_POWER_DOWN_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_AUTO_POWER_DOWN_CYCS} {32} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_USER_REFRESH_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_USER_PRIORITY_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_AUTO_PRECHARGE_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_ADDR_ORDER_ENUM} {DDR3_CTRL_ADDR_ORDER_CS_R_B_C} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_ECC_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_ECC_AUTO_CORRECTION_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_REORDER_EN} {1} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_STARVE_LIMIT} {10} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_MMR_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_ST} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_SELF_REFRESH_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_AUTO_POWER_DOWN_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_AUTO_POWER_DOWN_CYCS} {32} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_USER_REFRESH_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_USER_PRIORITY_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_AUTO_PRECHARGE_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_ADDR_ORDER_ENUM} {DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_ECC_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_ECC_AUTO_CORRECTION_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_REORDER_EN} {1} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_STARVE_LIMIT} {10} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_MMR_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_QDR2_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_MM} -set_instance_parameter_value emif_a10_hps_0 {CTRL_QDR2_AVL_MAX_BURST_COUNT} {4} -set_instance_parameter_value emif_a10_hps_0 {CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_QDR4_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_MM} -set_instance_parameter_value emif_a10_hps_0 {CTRL_QDR4_AVL_MAX_BURST_COUNT} {4} -set_instance_parameter_value emif_a10_hps_0 {CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_RLD2_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_MM} -set_instance_parameter_value emif_a10_hps_0 {CTRL_RLD3_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_MM} -set_instance_parameter_value emif_a10_hps_0 {CTRL_RLD3_ADDR_ORDER_ENUM} {RLD3_CTRL_ADDR_ORDER_CS_R_B_C} -set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_AVL_PROTOCOL_ENUM} {CTRL_AVL_PROTOCOL_ST} -set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_SELF_REFRESH_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_AUTO_POWER_DOWN_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS} {32} -set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_USER_REFRESH_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_USER_PRIORITY_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_AUTO_PRECHARGE_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_ADDR_ORDER_ENUM} {LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C} -set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_REORDER_EN} {1} -set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_STARVE_LIMIT} {10} -set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_MMR_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS} {0} -set_instance_parameter_value emif_a10_hps_0 {CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_SIM_REGTEST_MODE} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_TIMING_REGTEST_MODE} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_SYNTH_FOR_SIM} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_FAST_SIM_OVERRIDE} {FAST_SIM_OVERRIDE_DEFAULT} -set_instance_parameter_value emif_a10_hps_0 {DIAG_VERBOSE_IOAUX} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_ECLIPSE_DEBUG} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_EXPORT_VJI} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_ENABLE_JTAG_UART} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_ENABLE_JTAG_UART_HEX} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_ENABLE_HPS_EMIF_DEBUG} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_SOFT_NIOS_MODE} {SOFT_NIOS_MODE_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {DIAG_SOFT_NIOS_CLOCK_FREQUENCY} {100} -set_instance_parameter_value emif_a10_hps_0 {DIAG_USE_RS232_UART} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RS232_UART_BAUDRATE} {57600} -set_instance_parameter_value emif_a10_hps_0 {DIAG_EX_DESIGN_ADD_TEST_EMIFS} {} -set_instance_parameter_value emif_a10_hps_0 {DIAG_EX_DESIGN_SEPARATE_RESETS} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_EXPOSE_DFT_SIGNALS} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_EXTRA_CONFIGS} {} -set_instance_parameter_value emif_a10_hps_0 {DIAG_USE_BOARD_DELAY_MODEL} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_BOARD_DELAY_CONFIG_STR} {} -set_instance_parameter_value emif_a10_hps_0 {DIAG_TG_AVL_2_EXPORT_CFG_INTERFACE} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_TG_AVL_2_NUM_CFG_INTERFACES} {0} -set_instance_parameter_value emif_a10_hps_0 {SHORT_QSYS_INTERFACE_NAMES} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_EX_DESIGN_ISSP_EN} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_INTERFACE_ID} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_USE_TG_AVL_2} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_ABSTRACT_PHY} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_BYPASS_DEFAULT_PATTERN} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_BYPASS_USER_STAGE} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_BYPASS_REPEAT_STAGE} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_BYPASS_STRESS_STAGE} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_TG_DATA_PATTERN_LENGTH} {8} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_TG_BE_PATTERN_LENGTH} {8} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_SEPARATE_READ_WRITE_ITFS} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_CA_LEVEL_EN} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_CAL_ADDR0} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_CAL_ADDR1} {8} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_CAL_ENABLE_NON_DES} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR3_CAL_FULL_CAL_ON_RESET} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_EX_DESIGN_ISSP_EN} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_INTERFACE_ID} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_USE_TG_AVL_2} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_ABSTRACT_PHY} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_BYPASS_DEFAULT_PATTERN} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_BYPASS_USER_STAGE} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_BYPASS_REPEAT_STAGE} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_BYPASS_STRESS_STAGE} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_TG_DATA_PATTERN_LENGTH} {8} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_TG_BE_PATTERN_LENGTH} {8} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_SEPARATE_READ_WRITE_ITFS} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_SKIP_CA_LEVEL} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_SKIP_CA_DESKEW} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_SKIP_VREF_CAL} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_CAL_ADDR0} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_CAL_ADDR1} {8} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_CAL_ENABLE_NON_DES} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_DDR4_CAL_FULL_CAL_ON_RESET} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_EX_DESIGN_ISSP_EN} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_INTERFACE_ID} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_USE_TG_AVL_2} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_ABSTRACT_PHY} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_BYPASS_DEFAULT_PATTERN} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_BYPASS_USER_STAGE} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_BYPASS_REPEAT_STAGE} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_BYPASS_STRESS_STAGE} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_TG_DATA_PATTERN_LENGTH} {8} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_TG_BE_PATTERN_LENGTH} {8} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR2_SEPARATE_READ_WRITE_ITFS} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_EX_DESIGN_ISSP_EN} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_INTERFACE_ID} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_USE_TG_AVL_2} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_ABSTRACT_PHY} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_BYPASS_DEFAULT_PATTERN} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_BYPASS_USER_STAGE} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_BYPASS_REPEAT_STAGE} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_BYPASS_STRESS_STAGE} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_TG_DATA_PATTERN_LENGTH} {8} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_TG_BE_PATTERN_LENGTH} {8} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_SEPARATE_READ_WRITE_ITFS} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_QDR4_SKIP_VREF_CAL} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_EX_DESIGN_ISSP_EN} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_INTERFACE_ID} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_USE_TG_AVL_2} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_ABSTRACT_PHY} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_BYPASS_DEFAULT_PATTERN} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_BYPASS_USER_STAGE} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_BYPASS_REPEAT_STAGE} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_BYPASS_STRESS_STAGE} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_TG_DATA_PATTERN_LENGTH} {8} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_TG_BE_PATTERN_LENGTH} {8} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD2_SEPARATE_READ_WRITE_ITFS} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_EX_DESIGN_ISSP_EN} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_INTERFACE_ID} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_USE_TG_AVL_2} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_ABSTRACT_PHY} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_BYPASS_DEFAULT_PATTERN} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_BYPASS_USER_STAGE} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_BYPASS_REPEAT_STAGE} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_BYPASS_STRESS_STAGE} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_TG_DATA_PATTERN_LENGTH} {8} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_TG_BE_PATTERN_LENGTH} {8} -set_instance_parameter_value emif_a10_hps_0 {DIAG_RLD3_SEPARATE_READ_WRITE_ITFS} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_SIM_CAL_MODE_ENUM} {SIM_CAL_MODE_SKIP} -set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE} {CAL_DEBUG_EXPORT_MODE_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_EX_DESIGN_ISSP_EN} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_INTERFACE_ID} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_EFFICIENCY_MONITOR} {EFFMON_MODE_DISABLED} -set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_USE_TG_AVL_2} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_ABSTRACT_PHY} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_BYPASS_DEFAULT_PATTERN} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_BYPASS_USER_STAGE} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_BYPASS_REPEAT_STAGE} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_BYPASS_STRESS_STAGE} {1} -set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_TG_DATA_PATTERN_LENGTH} {8} -set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_TG_BE_PATTERN_LENGTH} {8} -set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_SEPARATE_READ_WRITE_ITFS} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_SKIP_CA_LEVEL} {0} -set_instance_parameter_value emif_a10_hps_0 {DIAG_LPDDR3_SKIP_CA_DESKEW} {0} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR3_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR3_GEN_SIM} {1} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR3_GEN_SYNTH} {1} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR3_HDL_FORMAT} {HDL_FORMAT_VERILOG} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR3_PREV_PRESET} {TARGET_DEV_KIT_NONE} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR4_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR4_GEN_SIM} {1} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR4_GEN_SYNTH} {1} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR4_HDL_FORMAT} {HDL_FORMAT_VERILOG} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_DDR4_PREV_PRESET} {TARGET_DEV_KIT_NONE} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR2_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR2_GEN_SIM} {1} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR2_GEN_SYNTH} {1} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR2_HDL_FORMAT} {HDL_FORMAT_VERILOG} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR2_PREV_PRESET} {TARGET_DEV_KIT_NONE} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR4_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR4_GEN_SIM} {1} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR4_GEN_SYNTH} {1} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR4_HDL_FORMAT} {HDL_FORMAT_VERILOG} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_QDR4_PREV_PRESET} {TARGET_DEV_KIT_NONE} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD2_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD2_GEN_SIM} {1} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD2_GEN_SYNTH} {1} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD2_HDL_FORMAT} {HDL_FORMAT_VERILOG} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD2_PREV_PRESET} {TARGET_DEV_KIT_NONE} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD3_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD3_GEN_SIM} {1} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD3_GEN_SYNTH} {1} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD3_HDL_FORMAT} {HDL_FORMAT_VERILOG} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_RLD3_PREV_PRESET} {TARGET_DEV_KIT_NONE} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_LPDDR3_SEL_DESIGN} {AVAIL_EX_DESIGNS_GEN_DESIGN} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_LPDDR3_GEN_SIM} {1} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_LPDDR3_GEN_SYNTH} {1} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_LPDDR3_HDL_FORMAT} {HDL_FORMAT_VERILOG} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT} {TARGET_DEV_KIT_NONE} -set_instance_parameter_value emif_a10_hps_0 {EX_DESIGN_GUI_LPDDR3_PREV_PRESET} {TARGET_DEV_KIT_NONE} +proc set_hps_io {io_index io_type} { + + global hps_io_list + lappend hps_io_list $io_type +} + +set_hps_io IO_DEDICATED_04 SDMMC:D0 +set_hps_io IO_DEDICATED_05 SDMMC:CMD +set_hps_io IO_DEDICATED_06 SDMMC:CCLK +set_hps_io IO_DEDICATED_07 SDMMC:D1 +set_hps_io IO_DEDICATED_08 SDMMC:D2 +set_hps_io IO_DEDICATED_09 SDMMC:D3 +set_hps_io IO_DEDICATED_10 NONE +set_hps_io IO_DEDICATED_11 NONE +set_hps_io IO_DEDICATED_12 SDMMC:D4 +set_hps_io IO_DEDICATED_13 SDMMC:D5 +set_hps_io IO_DEDICATED_14 SDMMC:D6 +set_hps_io IO_DEDICATED_15 SDMMC:D7 +set_hps_io IO_DEDICATED_16 UART1:TX +set_hps_io IO_DEDICATED_17 UART1:RX +set_hps_io IO_SHARED_Q1_01 USB0:CLK +set_hps_io IO_SHARED_Q1_02 USB0:STP +set_hps_io IO_SHARED_Q1_03 USB0:DIR +set_hps_io IO_SHARED_Q1_04 USB0:DATA0 +set_hps_io IO_SHARED_Q1_05 USB0:DATA1 +set_hps_io IO_SHARED_Q1_06 USB0:NXT +set_hps_io IO_SHARED_Q1_07 USB0:DATA2 +set_hps_io IO_SHARED_Q1_08 USB0:DATA3 +set_hps_io IO_SHARED_Q1_09 USB0:DATA4 +set_hps_io IO_SHARED_Q1_10 USB0:DATA5 +set_hps_io IO_SHARED_Q1_11 USB0:DATA6 +set_hps_io IO_SHARED_Q1_12 USB0:DATA7 +set_hps_io IO_SHARED_Q2_01 EMAC0:TX_CLK +set_hps_io IO_SHARED_Q2_02 EMAC0:TX_CTL +set_hps_io IO_SHARED_Q2_03 EMAC0:RX_CLK +set_hps_io IO_SHARED_Q2_04 EMAC0:RX_CTL +set_hps_io IO_SHARED_Q2_05 EMAC0:TXD0 +set_hps_io IO_SHARED_Q2_06 EMAC0:TXD1 +set_hps_io IO_SHARED_Q2_07 EMAC0:RXD0 +set_hps_io IO_SHARED_Q2_08 EMAC0:RXD1 +set_hps_io IO_SHARED_Q2_09 EMAC0:TXD2 +set_hps_io IO_SHARED_Q2_10 EMAC0:TXD3 +set_hps_io IO_SHARED_Q2_11 EMAC0:RXD2 +set_hps_io IO_SHARED_Q2_12 EMAC0:RXD3 +set_hps_io IO_SHARED_Q3_01 NONE +set_hps_io IO_SHARED_Q3_02 NONE +set_hps_io IO_SHARED_Q3_03 NONE +set_hps_io IO_SHARED_Q3_04 NONE +set_hps_io IO_SHARED_Q3_05 NONE +set_hps_io IO_SHARED_Q3_06 GPIO +set_hps_io IO_SHARED_Q3_07 NONE +set_hps_io IO_SHARED_Q3_08 NONE +set_hps_io IO_SHARED_Q3_09 NONE +set_hps_io IO_SHARED_Q3_10 NONE +set_hps_io IO_SHARED_Q3_11 MDIO0:MDIO +set_hps_io IO_SHARED_Q3_12 MDIO0:MDC +set_hps_io IO_SHARED_Q4_01 I2C1:SDA +set_hps_io IO_SHARED_Q4_02 I2C1:SCL +set_hps_io IO_SHARED_Q4_03 GPIO +set_hps_io IO_SHARED_Q4_04 NONE +set_hps_io IO_SHARED_Q4_05 GPIO +set_hps_io IO_SHARED_Q4_06 GPIO +set_hps_io IO_SHARED_Q4_07 NONE +set_hps_io IO_SHARED_Q4_08 NONE +set_hps_io IO_SHARED_Q4_09 NONE +set_hps_io IO_SHARED_Q4_10 NONE +set_hps_io IO_SHARED_Q4_11 NONE +set_hps_io IO_SHARED_Q4_12 NONE + +add_instance sys_hps altera_arria10_hps 16.0 +set_instance_parameter_value sys_hps {MPU_EVENTS_Enable} {0} +set_instance_parameter_value sys_hps {F2S_Width} {0} +set_instance_parameter_value sys_hps {S2F_Width} {0} +set_instance_parameter_value sys_hps {LWH2F_Enable} {1} +set_instance_parameter_value sys_hps {F2SDRAM_PORT_CONFIG} {6} +set_instance_parameter_value sys_hps {F2SDRAM0_ENABLED} {1} +set_instance_parameter_value sys_hps {F2SINTERRUPT_Enable} {1} +set_instance_parameter_value sys_hps {HPS_IO_Enable} $hps_io_list +set_instance_parameter_value sys_hps {SDMMC_PinMuxing} {IO} +set_instance_parameter_value sys_hps {SDMMC_Mode} {8-bit} +set_instance_parameter_value sys_hps {USB0_PinMuxing} {IO} +set_instance_parameter_value sys_hps {USB0_Mode} {default} +set_instance_parameter_value sys_hps {EMAC0_PinMuxing} {IO} +set_instance_parameter_value sys_hps {EMAC0_Mode} {RGMII_with_MDIO} +set_instance_parameter_value sys_hps {UART1_PinMuxing} {IO} +set_instance_parameter_value sys_hps {UART1_Mode} {No_flow_control} +set_instance_parameter_value sys_hps {I2C1_PinMuxing} {IO} +set_instance_parameter_value sys_hps {I2C1_Mode} {default} +set_instance_parameter_value sys_hps {F2H_COLD_RST_Enable} {1} +set_instance_parameter_value sys_hps {H2F_USER0_CLK_Enable} {1} +set_instance_parameter_value sys_hps {H2F_USER0_CLK_FREQ} {175} +set_instance_parameter_value sys_hps {CLK_SDMMC_SOURCE} {1} + +add_interface sys_hps_rstn reset sink +set_interface_property sys_hps_rstn EXPORT_OF sys_hps.f2h_cold_reset_req +add_interface sys_hps_out_rstn reset source +set_interface_property sys_hps_out_rstn EXPORT_OF sys_hps.h2f_reset +add_connection sys_clk.clk sys_hps.h2f_lw_axi_clock +add_connection sys_hps.h2f_user0_clock sys_hps.f2sdram0_clock +add_interface sys_hps_io conduit end +set_interface_property sys_hps_io EXPORT_OF sys_hps.hps_io + +# ddr4 interface + +add_instance sys_hps_ddr4_cntrl altera_emif_a10_hps 16.0 +set_instance_parameter_value sys_hps_ddr4_cntrl {PROTOCOL_ENUM} {PROTOCOL_DDR4} +set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_MEM_CLK_FREQ_MHZ} {1066.667} +set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_DEFAULT_REF_CLK_FREQ} {0} +set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_REF_CLK_FREQ_MHZ} {133.333} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_BANK_GROUP_WIDTH} {1} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_ALERT_N_PLACEMENT_ENUM} {DDR4_ALERT_N_PLACEMENT_DATA_LANES} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_ALERT_N_DQS_GROUP} {3} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_READ_DBI} {1} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TCL} {20} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_WTCL} {18} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_RTT_NOM_ENUM} {DDR4_RTT_NOM_RZQ_6} +set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_DEFAULT_IO} {0} +set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_AC_IO_STD_ENUM} {IO_STD_SSTL_12} +set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_AC_MODE_ENUM} {OUT_OCT_40_CAL} +set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_CK_IO_STD_ENUM} {IO_STD_SSTL_12} +set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_CK_MODE_ENUM} {OUT_OCT_40_CAL} +set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_DATA_IO_STD_ENUM} {IO_STD_POD_12} +set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_DATA_OUT_MODE_ENUM} {OUT_OCT_34_CAL} +set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_DATA_IN_MODE_ENUM} {IN_OCT_60_CAL} +set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM} {IO_STD_CMOS_12} +set_instance_parameter_value sys_hps_ddr4_cntrl {PHY_DDR4_USER_RZQ_IO_STD_ENUM} {IO_STD_CMOS_12} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_SPEEDBIN_ENUM} {DDR4_SPEEDBIN_2666} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TRCD_NS} {14.25} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TRP_NS} {14.25} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TRRD_S_CYC} {7} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TRRD_L_CYC} {8} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TFAW_NS} {30.0} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TWTR_S_CYC} {4} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_TWTR_L_CYC} {10} +set_instance_parameter_value sys_hps_ddr4_cntrl {MEM_DDR4_LRDIMM_VREFDQ_VALUE} {1D} +set_instance_parameter_value sys_hps_ddr4_cntrl {DIAG_DDR4_SKIP_CA_LEVEL} {1} +set_instance_parameter_value sys_hps_ddr4_cntrl {SHORT_QSYS_INTERFACE_NAMES} {0} + +add_interface sys_hps_ddr_rstn reset sink +set_interface_property sys_hps_ddr_rstn EXPORT_OF sys_hps_ddr4_cntrl.global_reset_reset_sink +add_connection sys_hps_ddr4_cntrl.hps_emif_conduit_end sys_hps.emif +add_interface sys_hps_ddr conduit end +set_interface_property sys_hps_ddr EXPORT_OF sys_hps_ddr4_cntrl.mem_conduit_end +add_interface sys_hps_ddr_oct conduit end +set_interface_property sys_hps_ddr_oct EXPORT_OF sys_hps_ddr4_cntrl.oct_conduit_end +add_interface sys_hps_ddr_ref_clk clock sink +set_interface_property sys_hps_ddr_ref_clk EXPORT_OF sys_hps_ddr4_cntrl.pll_ref_clk_clock_sink + +# cpu/hps handling + +proc ad_cpu_interrupt {m_irq m_port} { + + add_connection sys_hps.f2h_irq0 ${m_port} + set_connection_parameter_value sys_hps.f2h_irq0/${m_port} irqNumber ${m_irq} +} + +proc ad_cpu_interconnect {m_base m_port} { + + add_connection sys_hps.h2f_lw_axi_master ${m_port} + set_connection_parameter_value sys_hps.h2f_lw_axi_master/${m_port} baseAddress ${m_base} +} + +proc ad_dma_interconnect {m_port} { + + add_connection ${m_port} sys_hps.f2sdram0_data + set_connection_parameter_value ${m_port}/sys_hps.f2sdram0_data baseAddress {0x0} +} + +# gpio-in + +add_instance sys_gpio_in altera_avalon_pio 16.0 +set_instance_parameter_value sys_gpio_in {direction} {Input} +set_instance_parameter_value sys_gpio_in {generateIRQ} {1} +set_instance_parameter_value sys_gpio_in {width} {32} + +add_connection sys_clk.clk_reset sys_gpio_in.reset +add_connection sys_clk.clk sys_gpio_in.clk +add_interface sys_gpio_in conduit end +set_interface_property sys_gpio_in EXPORT_OF sys_gpio_in.external_connection + +# gpio-out + +add_instance sys_gpio_out altera_avalon_pio 16.0 +set_instance_parameter_value sys_gpio_out {direction} {Output} +set_instance_parameter_value sys_gpio_out {generateIRQ} {0} +set_instance_parameter_value sys_gpio_out {width} {32} + +add_connection sys_clk.clk_reset sys_gpio_out.reset +add_connection sys_clk.clk sys_gpio_out.clk +add_interface sys_gpio_out conduit end +set_interface_property sys_gpio_out EXPORT_OF sys_gpio_out.external_connection + +# spi add_instance sys_spi altera_avalon_spi 16.0 -set_instance_parameter_value sys_spi {clockPhase} {1} -set_instance_parameter_value sys_spi {clockPolarity} {1} +set_instance_parameter_value sys_spi {clockPhase} {0} +set_instance_parameter_value sys_spi {clockPolarity} {0} set_instance_parameter_value sys_spi {dataWidth} {8} -set_instance_parameter_value sys_spi {disableAvalonFlowControl} {0} -set_instance_parameter_value sys_spi {insertDelayBetweenSlaveSelectAndSClk} {0} -set_instance_parameter_value sys_spi {insertSync} {0} -set_instance_parameter_value sys_spi {lsbOrderedFirst} {0} set_instance_parameter_value sys_spi {masterSPI} {1} -set_instance_parameter_value sys_spi {numberOfSlaves} {2} -set_instance_parameter_value sys_spi {syncRegDepth} {2} -set_instance_parameter_value sys_spi {targetClockRate} {5000000.0} -set_instance_parameter_value sys_spi {targetSlaveSelectToSClkDelay} {0.0} - -add_instance gpio_i altera_avalon_pio 16.0 -set_instance_parameter_value gpio_i {bitClearingEdgeCapReg} {0} -set_instance_parameter_value gpio_i {bitModifyingOutReg} {0} -set_instance_parameter_value gpio_i {captureEdge} {0} -set_instance_parameter_value gpio_i {direction} {Input} -set_instance_parameter_value gpio_i {edgeType} {RISING} -set_instance_parameter_value gpio_i {generateIRQ} {0} -set_instance_parameter_value gpio_i {irqType} {LEVEL} -set_instance_parameter_value gpio_i {resetValue} {0.0} -set_instance_parameter_value gpio_i {simDoTestBenchWiring} {0} -set_instance_parameter_value gpio_i {simDrivenValue} {0.0} -set_instance_parameter_value gpio_i {width} {32} - -add_instance gpio_o altera_avalon_pio 16.0 -set_instance_parameter_value gpio_o {bitClearingEdgeCapReg} {0} -set_instance_parameter_value gpio_o {bitModifyingOutReg} {1} -set_instance_parameter_value gpio_o {captureEdge} {0} -set_instance_parameter_value gpio_o {direction} {Output} -set_instance_parameter_value gpio_o {edgeType} {RISING} -set_instance_parameter_value gpio_o {generateIRQ} {0} -set_instance_parameter_value gpio_o {irqType} {LEVEL} -set_instance_parameter_value gpio_o {resetValue} {0.0} -set_instance_parameter_value gpio_o {simDoTestBenchWiring} {0} -set_instance_parameter_value gpio_o {simDrivenValue} {0.0} -set_instance_parameter_value gpio_o {width} {32} - -# connections and connection parameters -add_connection sys_clk.clk arria10_hps_0.h2f_lw_axi_clock clock -add_connection sys_clk.clk sys_spi.clk clock -add_connection sys_clk.clk gpio_i.clk clock -add_connection sys_clk.clk gpio_o.clk clock -add_connection sys_clk.clk sys_rst.clk clock - -add_connection arria10_hps_0.h2f_user0_clock arria10_hps_0.f2sdram0_clock clock - -add_connection emif_a10_hps_0.hps_emif_conduit_end arria10_hps_0.emif conduit -set_connection_parameter_value emif_a10_hps_0.hps_emif_conduit_end/arria10_hps_0.emif endPort {} -set_connection_parameter_value emif_a10_hps_0.hps_emif_conduit_end/arria10_hps_0.emif endPortLSB {0} -set_connection_parameter_value emif_a10_hps_0.hps_emif_conduit_end/arria10_hps_0.emif startPort {} -set_connection_parameter_value emif_a10_hps_0.hps_emif_conduit_end/arria10_hps_0.emif startPortLSB {0} -set_connection_parameter_value emif_a10_hps_0.hps_emif_conduit_end/arria10_hps_0.emif width {0} - -add_connection sys_clk.clk_reset arria10_hps_0.f2h_cold_reset_req reset -add_connection sys_clk.clk_reset emif_a10_hps_0.global_reset_reset_sink reset -add_connection sys_clk.clk_reset sys_rst.in_reset reset -add_connection arria10_hps_0.h2f_reset sys_rst.in_reset reset -add_connection sys_rst.out_reset sys_spi.reset reset -add_connection sys_rst.out_reset gpio_i.reset reset -add_connection sys_rst.out_reset gpio_o.reset reset - -# exported interfaces -add_interface hps_ddr conduit end -set_interface_property hps_ddr EXPORT_OF emif_a10_hps_0.mem_conduit_end -add_interface hps_ddr_oct conduit end -set_interface_property hps_ddr_oct EXPORT_OF emif_a10_hps_0.oct_conduit_end -add_interface hps_ddr_ref_clk clock sink -set_interface_property hps_ddr_ref_clk EXPORT_OF emif_a10_hps_0.pll_ref_clk_clock_sink - -add_interface hps_io conduit end -set_interface_property hps_io EXPORT_OF arria10_hps_0.hps_io -add_interface hps_s1_axi altera_axi slave +set_instance_parameter_value sys_spi {numberOfSlaves} {8} +set_instance_parameter_value sys_spi {targetClockRate} {128000.0} +add_connection sys_clk.clk_reset sys_spi.reset +add_connection sys_clk.clk sys_spi.clk +add_interface sys_spi conduit end set_interface_property sys_spi EXPORT_OF sys_spi.external -set_interface_property gpio_o EXPORT_OF gpio_o.external_connection -set_interface_property gpio_i EXPORT_OF gpio_i.external_connection + +# base-addresses + +ad_cpu_interconnect 0x00000000 sys_gpio_in.s1 +ad_cpu_interconnect 0x00000020 sys_gpio_out.s1 +ad_cpu_interconnect 0x00000040 sys_spi.spi_control_port # interrupts -add_connection arria10_hps_0.f2h_irq0 sys_spi.irq -set_connection_parameter_value arria10_hps_0.f2h_irq0/sys_spi.irq irqNumber {1} -# cpu connections -add_connection arria10_hps_0.h2f_lw_axi_master sys_spi.spi_control_port -add_connection arria10_hps_0.h2f_lw_axi_master gpio_i.s1 -add_connection arria10_hps_0.h2f_lw_axi_master gpio_o.s1 +ad_cpu_interrupt 5 sys_gpio_in.irq +ad_cpu_interrupt 7 sys_spi.irq -set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/sys_spi.spi_control_port baseAddress {0x00000000} -set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/gpio_i.s1 baseAddress {0x00000020} -set_connection_parameter_value arria10_hps_0.h2f_lw_axi_master/gpio_o.s1 baseAddress {0x00000040} +# common dma interfaces + +add_instance sys_dma_clk clock_source 16.0 +add_connection sys_hps.h2f_user0_clock sys_dma_clk.clk_in +add_connection sys_clk.clk_reset sys_dma_clk.clk_in_reset