From f81494f6c84f5393a8d681beed7104a61422261a Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Fri, 28 Jul 2017 15:25:56 -0400 Subject: [PATCH] util_upack- add valid turnaround --- library/util_upack/util_upack.v | 250 ++++++++++++------------- library/util_upack/util_upack_dmx.v | 127 ++++++++----- library/util_upack/util_upack_dsf.v | 277 ++++++++++++++-------------- 3 files changed, 339 insertions(+), 315 deletions(-) diff --git a/library/util_upack/util_upack.v b/library/util_upack/util_upack.v index 28a130391..07768bc14 100644 --- a/library/util_upack/util_upack.v +++ b/library/util_upack/util_upack.v @@ -37,175 +37,158 @@ module util_upack #( - parameter CHANNEL_DATA_WIDTH = 32, - parameter NUM_OF_CHANNELS = 8) ( + parameter CHANNEL_DATA_WIDTH = 32, + parameter NUM_OF_CHANNELS = 8) ( // dac interface - input dac_clk, - input dac_enable_0, - input dac_valid_0, - output [(CHANNEL_DATA_WIDTH-1):0] dac_data_0, - output upack_valid_0, - input dac_enable_1, - input dac_valid_1, - output [(CHANNEL_DATA_WIDTH-1):0] dac_data_1, - output upack_valid_1, - input dac_enable_2, - input dac_valid_2, - output [(CHANNEL_DATA_WIDTH-1):0] dac_data_2, - output upack_valid_2, - input dac_enable_3, - input dac_valid_3, - output [(CHANNEL_DATA_WIDTH-1):0] dac_data_3, - output upack_valid_3, - input dac_enable_4, - input dac_valid_4, - output [(CHANNEL_DATA_WIDTH-1):0] dac_data_4, - output upack_valid_4, - input dac_enable_5, - input dac_valid_5, - output [(CHANNEL_DATA_WIDTH-1):0] dac_data_5, - output upack_valid_5, - input dac_enable_6, - input dac_valid_6, - output [(CHANNEL_DATA_WIDTH-1):0] dac_data_6, - output upack_valid_6, - input dac_enable_7, - input dac_valid_7, - output [(CHANNEL_DATA_WIDTH-1):0] dac_data_7, - output upack_valid_7, - - input dma_xfer_in, - output reg dac_xfer_out, + input dac_clk, + input dac_enable_0, + input dac_valid_0, + output dac_valid_out_0, + output [(CHANNEL_DATA_WIDTH-1):0] dac_data_0, + input dac_enable_1, + input dac_valid_1, + output dac_valid_out_1, + output [(CHANNEL_DATA_WIDTH-1):0] dac_data_1, + input dac_enable_2, + input dac_valid_2, + output dac_valid_out_2, + output [(CHANNEL_DATA_WIDTH-1):0] dac_data_2, + input dac_enable_3, + input dac_valid_3, + output dac_valid_out_3, + output [(CHANNEL_DATA_WIDTH-1):0] dac_data_3, + input dac_enable_4, + input dac_valid_4, + output dac_valid_out_4, + output [(CHANNEL_DATA_WIDTH-1):0] dac_data_4, + input dac_enable_5, + input dac_valid_5, + output dac_valid_out_5, + output [(CHANNEL_DATA_WIDTH-1):0] dac_data_5, + input dac_enable_6, + input dac_valid_6, + output dac_valid_out_6, + output [(CHANNEL_DATA_WIDTH-1):0] dac_data_6, + input dac_enable_7, + input dac_valid_7, + output dac_valid_out_7, + output [(CHANNEL_DATA_WIDTH-1):0] dac_data_7, // fifo interface - output reg dac_valid, - output reg dac_sync, - input [((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] dac_data); + output dac_valid, + output dac_sync, + input [((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] dac_data); + // internal parameters - localparam NUM_OF_CHANNELS_M = 8; - localparam NUM_OF_CHANNELS_P = NUM_OF_CHANNELS; - localparam CH_SCNT = CHANNEL_DATA_WIDTH/16; - localparam M_WIDTH = CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS_M; - localparam P_WIDTH = CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS_P; + localparam MAX_CHANNELS = 8; // internal registers - reg [(M_WIDTH-1):0] dac_dsf_data = 'd0; - reg [ 7:0] dac_dmx_enable = 'd0; - reg xfer_valid_d1; - reg xfer_valid_d2; - reg xfer_valid_d3; - reg xfer_valid_d4; - reg xfer_valid_d5; + reg dac_valid_int = 'd0; + reg dac_sync_int = 'd0; // internal signals - wire dac_valid_s; - wire dac_dsf_valid_s[(NUM_OF_CHANNELS_M-1):0]; - wire dac_dsf_sync_s[(NUM_OF_CHANNELS_M-1):0]; - wire [(M_WIDTH-1):0] dac_dsf_data_s[(NUM_OF_CHANNELS_M-1):0]; - wire [(CH_SCNT-1):0] dac_dmx_enable_7_s; - wire [(CH_SCNT-1):0] dac_dmx_enable_6_s; - wire [(CH_SCNT-1):0] dac_dmx_enable_5_s; - wire [(CH_SCNT-1):0] dac_dmx_enable_4_s; - wire [(CH_SCNT-1):0] dac_dmx_enable_3_s; - wire [(CH_SCNT-1):0] dac_dmx_enable_2_s; - wire [(CH_SCNT-1):0] dac_dmx_enable_1_s; - wire [(CH_SCNT-1):0] dac_dmx_enable_0_s; + wire dac_valid_s; + wire [ 7:0] dac_enable_s; + wire dac_dsf_valid_m_s; + wire [((CHANNEL_DATA_WIDTH*MAX_CHANNELS)-1):0] dac_dsf_data_m_s; + wire [ 7:0] dac_dmx_enable_m_s; + wire [(MAX_CHANNELS-1):0] dac_dsf_req_s; + wire [(MAX_CHANNELS-1):0] dac_dsf_sync_s; + wire [(MAX_CHANNELS-1):0] dac_dsf_valid_s; + wire [((CHANNEL_DATA_WIDTH*MAX_CHANNELS)-1):0] dac_dsf_data_s[(MAX_CHANNELS-1):0]; + wire [((CHANNEL_DATA_WIDTH/16)-1):0] dac_dmx_valid_s; + wire [((CHANNEL_DATA_WIDTH/16)-1):0] dac_dmx_enable_7_s; + wire [((CHANNEL_DATA_WIDTH/16)-1):0] dac_dmx_enable_6_s; + wire [((CHANNEL_DATA_WIDTH/16)-1):0] dac_dmx_enable_5_s; + wire [((CHANNEL_DATA_WIDTH/16)-1):0] dac_dmx_enable_4_s; + wire [((CHANNEL_DATA_WIDTH/16)-1):0] dac_dmx_enable_3_s; + wire [((CHANNEL_DATA_WIDTH/16)-1):0] dac_dmx_enable_2_s; + wire [((CHANNEL_DATA_WIDTH/16)-1):0] dac_dmx_enable_1_s; + wire [((CHANNEL_DATA_WIDTH/16)-1):0] dac_dmx_enable_0_s; - // loop variables + // data interleaving - genvar n; + assign dac_valid = dac_valid_int; + assign dac_sync = dac_sync_int; + assign dac_valid_out_0 = dac_dmx_valid_s[0]; + assign dac_valid_out_1 = dac_dmx_valid_s[0]; + assign dac_valid_out_2 = dac_dmx_valid_s[0]; + assign dac_valid_out_3 = dac_dmx_valid_s[0]; + assign dac_valid_out_4 = dac_dmx_valid_s[0]; + assign dac_valid_out_5 = dac_dmx_valid_s[0]; + assign dac_valid_out_6 = dac_dmx_valid_s[0]; + assign dac_valid_out_7 = dac_dmx_valid_s[0]; + always @(posedge dac_clk) begin + dac_valid_int <= | dac_dsf_req_s; + dac_sync_int <= | dac_dsf_sync_s; + end assign dac_valid_s = dac_valid_7 | dac_valid_6 | dac_valid_5 | dac_valid_4 | - dac_valid_3 | dac_valid_2 | dac_valid_1 | dac_valid_0; + dac_valid_3 | dac_valid_2 | dac_valid_1 | dac_valid_0; + assign dac_enable_s = {dac_enable_7, dac_enable_6, dac_enable_5, dac_enable_4, + dac_enable_3, dac_enable_2, dac_enable_1, dac_enable_0}; - assign upack_valid_0 = | dac_dmx_enable & dac_enable_0 & dac_xfer_out; - assign upack_valid_1 = | dac_dmx_enable & dac_enable_1 & dac_xfer_out; - assign upack_valid_2 = | dac_dmx_enable & dac_enable_2 & dac_xfer_out; - assign upack_valid_3 = | dac_dmx_enable & dac_enable_3 & dac_xfer_out; - assign upack_valid_4 = | dac_dmx_enable & dac_enable_4 & dac_xfer_out; - assign upack_valid_5 = | dac_dmx_enable & dac_enable_5 & dac_xfer_out; - assign upack_valid_6 = | dac_dmx_enable & dac_enable_6 & dac_xfer_out; - assign upack_valid_7 = | dac_dmx_enable & dac_enable_7 & dac_xfer_out; + assign dac_dsf_valid_m_s = | dac_dsf_valid_s; + assign dac_dsf_data_m_s = dac_dsf_data_s[7] | dac_dsf_data_s[6] | + dac_dsf_data_s[5] | dac_dsf_data_s[4] | dac_dsf_data_s[3] | + dac_dsf_data_s[2] | dac_dsf_data_s[1] | dac_dsf_data_s[0]; - always @(posedge dac_clk) begin - xfer_valid_d1 <= dma_xfer_in; - xfer_valid_d2 <= xfer_valid_d1; - xfer_valid_d3 <= xfer_valid_d2; - xfer_valid_d4 <= xfer_valid_d3; - xfer_valid_d5 <= xfer_valid_d4; - if (dac_dmx_enable[NUM_OF_CHANNELS_P-1] == 1'b1) begin - dac_xfer_out <= xfer_valid_d4; - end else begin - dac_xfer_out <= xfer_valid_d5; - end - end + assign dac_dmx_enable_m_s[7] = | dac_dmx_enable_7_s; + assign dac_dmx_enable_m_s[6] = | dac_dmx_enable_6_s; + assign dac_dmx_enable_m_s[5] = | dac_dmx_enable_5_s; + assign dac_dmx_enable_m_s[4] = | dac_dmx_enable_4_s; + assign dac_dmx_enable_m_s[3] = | dac_dmx_enable_3_s; + assign dac_dmx_enable_m_s[2] = | dac_dmx_enable_2_s; + assign dac_dmx_enable_m_s[1] = | dac_dmx_enable_1_s; + assign dac_dmx_enable_m_s[0] = | dac_dmx_enable_0_s; - always @(posedge dac_clk) begin - dac_valid <= dac_dsf_valid_s[7] | dac_dsf_valid_s[6] | - dac_dsf_valid_s[5] | dac_dsf_valid_s[4] | - dac_dsf_valid_s[3] | dac_dsf_valid_s[2] | - dac_dsf_valid_s[1] | dac_dsf_valid_s[0]; - dac_sync <= dac_dsf_sync_s[7] | dac_dsf_sync_s[6] | - dac_dsf_sync_s[5] | dac_dsf_sync_s[4] | - dac_dsf_sync_s[3] | dac_dsf_sync_s[2] | - dac_dsf_sync_s[1] | dac_dsf_sync_s[0]; - dac_dsf_data <= dac_dsf_data_s[7] | dac_dsf_data_s[6] | - dac_dsf_data_s[5] | dac_dsf_data_s[4] | - dac_dsf_data_s[3] | dac_dsf_data_s[2] | - dac_dsf_data_s[1] | dac_dsf_data_s[0]; - dac_dmx_enable[7] <= | dac_dmx_enable_7_s; - dac_dmx_enable[6] <= | dac_dmx_enable_6_s; - dac_dmx_enable[5] <= | dac_dmx_enable_5_s; - dac_dmx_enable[4] <= | dac_dmx_enable_4_s; - dac_dmx_enable[3] <= | dac_dmx_enable_3_s; - dac_dmx_enable[2] <= | dac_dmx_enable_2_s; - dac_dmx_enable[1] <= | dac_dmx_enable_1_s; - dac_dmx_enable[0] <= | dac_dmx_enable_0_s; - end - - // store & fwd + // instantiations + genvar n; generate - if (NUM_OF_CHANNELS_P < NUM_OF_CHANNELS_M) begin - for (n = NUM_OF_CHANNELS_P; n < NUM_OF_CHANNELS_M; n = n + 1) begin: g_def - assign dac_dsf_valid_s[n] = 'd0; - assign dac_dsf_sync_s[n] = 'd0; - assign dac_dsf_data_s[n] = 'd0; - end + + // defaults + + for (n = NUM_OF_CHANNELS; n < MAX_CHANNELS; n = n + 1) begin: g_defaults + assign dac_dsf_req_s[n] = 'd0; + assign dac_dsf_sync_s[n] = 'd0; + assign dac_dsf_valid_s[n] = 'd0; + assign dac_dsf_data_s[n] = 'd0; end - for (n = 0; n < NUM_OF_CHANNELS_P; n = n + 1) begin: g_dsf + // dsf + + for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_dsf util_upack_dsf #( - .NUM_OF_CHANNELS_P (NUM_OF_CHANNELS_P), - .NUM_OF_CHANNELS_M (NUM_OF_CHANNELS_M), .CHANNEL_DATA_WIDTH (CHANNEL_DATA_WIDTH), - .NUM_OF_CHANNELS_O ((n+1))) + .NUM_OF_CHANNELS (NUM_OF_CHANNELS), + .MAX_CHANNELS (MAX_CHANNELS), + .SEL_CHANNELS ((n+1))) i_dsf ( .dac_clk (dac_clk), .dac_valid (dac_valid_s), .dac_data (dac_data), - .dac_dmx_enable (dac_dmx_enable[n]), - .dac_dsf_valid (dac_dsf_valid_s[n]), + .dac_dmx_enable (dac_dmx_enable_m_s[n]), + .dac_dsf_req (dac_dsf_req_s[n]), .dac_dsf_sync (dac_dsf_sync_s[n]), + .dac_dsf_valid (dac_dsf_valid_s[n]), .dac_dsf_data (dac_dsf_data_s[n])); end - endgenerate // demux - generate - for (n = 0; n < CH_SCNT; n = n + 1) begin: g_dmx + for (n = 0; n < (CHANNEL_DATA_WIDTH/16); n = n + 1) begin: g_dmx util_upack_dmx i_dmx ( .dac_clk (dac_clk), - .dac_enable ({dac_enable_7, dac_enable_6, dac_enable_5, dac_enable_4, - dac_enable_3, dac_enable_2, dac_enable_1, dac_enable_0}), + .dac_enable (dac_enable_s), + .dac_valid (dac_dmx_valid_s[n]), .dac_data_0 (dac_data_0[((16*n)+15):(16*n)]), .dac_data_1 (dac_data_1[((16*n)+15):(16*n)]), .dac_data_2 (dac_data_2[((16*n)+15):(16*n)]), @@ -215,11 +198,12 @@ module util_upack #( .dac_data_6 (dac_data_6[((16*n)+15):(16*n)]), .dac_data_7 (dac_data_7[((16*n)+15):(16*n)]), .dac_dmx_enable ({dac_dmx_enable_7_s[n], dac_dmx_enable_6_s[n], - dac_dmx_enable_5_s[n], dac_dmx_enable_4_s[n], - dac_dmx_enable_3_s[n], dac_dmx_enable_2_s[n], - dac_dmx_enable_1_s[n], dac_dmx_enable_0_s[n]}), - .dac_dsf_data (dac_dsf_data[((NUM_OF_CHANNELS_M*16*(n+1))-1):(NUM_OF_CHANNELS_M*16*n)])); + dac_dmx_enable_5_s[n], dac_dmx_enable_4_s[n], dac_dmx_enable_3_s[n], + dac_dmx_enable_2_s[n], dac_dmx_enable_1_s[n], dac_dmx_enable_0_s[n]}), + .dac_dsf_valid (dac_dsf_valid_m_s), + .dac_dsf_data (dac_dsf_data_m_s[((MAX_CHANNELS*16*(n+1))-1):(MAX_CHANNELS*16*n)])); end + endgenerate endmodule diff --git a/library/util_upack/util_upack_dmx.v b/library/util_upack/util_upack_dmx.v index a3ae0d7e8..441d91cda 100644 --- a/library/util_upack/util_upack_dmx.v +++ b/library/util_upack/util_upack_dmx.v @@ -39,24 +39,38 @@ module util_upack_dmx ( // dac interface - input dac_clk, - input [ 7:0] dac_enable, - output reg [ 15:0] dac_data_0, - output reg [ 15:0] dac_data_1, - output reg [ 15:0] dac_data_2, - output reg [ 15:0] dac_data_3, - output reg [ 15:0] dac_data_4, - output reg [ 15:0] dac_data_5, - output reg [ 15:0] dac_data_6, - output reg [ 15:0] dac_data_7, + input dac_clk, + input [ 7:0] dac_enable, + output dac_valid, + output [ 15:0] dac_data_0, + output [ 15:0] dac_data_1, + output [ 15:0] dac_data_2, + output [ 15:0] dac_data_3, + output [ 15:0] dac_data_4, + output [ 15:0] dac_data_5, + output [ 15:0] dac_data_6, + output [ 15:0] dac_data_7, // dmx interface - output reg [ 7:0] dac_dmx_enable, - input [127:0] dac_dsf_data); + output [ 7:0] dac_dmx_enable, + input dac_dsf_valid, + input [127:0] dac_dsf_data); // internal registers + reg [ 7:0] dac_dmx_enable_int = 'd0; + reg dac_valid_int = 'd0; + reg dac_valid_d2 = 'd0; + reg dac_valid_d1 = 'd0; + reg [ 15:0] dac_data_int_0 = 'd0; + reg [ 15:0] dac_data_int_1 = 'd0; + reg [ 15:0] dac_data_int_2 = 'd0; + reg [ 15:0] dac_data_int_3 = 'd0; + reg [ 15:0] dac_data_int_4 = 'd0; + reg [ 15:0] dac_data_int_5 = 'd0; + reg [ 15:0] dac_data_int_6 = 'd0; + reg [ 15:0] dac_data_int_7 = 'd0; reg dac_dmx_enable_0 = 'd0; reg [ 15:0] dac_dmx_data_0_0 = 'd0; reg [ 15:0] dac_dmx_data_1_0 = 'd0; @@ -312,46 +326,63 @@ module util_upack_dmx ( // simple data or for pipe line registers + assign dac_dmx_enable = dac_dmx_enable_int; + assign dac_valid = dac_valid_int; + assign dac_data_0 = dac_data_int_0; + assign dac_data_1 = dac_data_int_1; + assign dac_data_2 = dac_data_int_2; + assign dac_data_3 = dac_data_int_3; + assign dac_data_4 = dac_data_int_4; + assign dac_data_5 = dac_data_int_5; + assign dac_data_6 = dac_data_int_6; + assign dac_data_7 = dac_data_int_7; + always @(posedge dac_clk) begin - dac_dmx_enable <= { dac_dmx_enable_7, dac_dmx_enable_6, - dac_dmx_enable_5, dac_dmx_enable_4, - dac_dmx_enable_3, dac_dmx_enable_2, - dac_dmx_enable_1, dac_dmx_enable_0}; + dac_dmx_enable_int <= { dac_dmx_enable_7, dac_dmx_enable_6, + dac_dmx_enable_5, dac_dmx_enable_4, + dac_dmx_enable_3, dac_dmx_enable_2, + dac_dmx_enable_1, dac_dmx_enable_0}; end always @(posedge dac_clk) begin - dac_data_0 <= dac_dmx_data_0_0 | dac_dmx_data_0_1 | - dac_dmx_data_0_2 | dac_dmx_data_0_3 | - dac_dmx_data_0_4 | dac_dmx_data_0_5 | - dac_dmx_data_0_6 | dac_dmx_data_0_7; - dac_data_1 <= dac_dmx_data_1_0 | dac_dmx_data_1_1 | - dac_dmx_data_1_2 | dac_dmx_data_1_3 | - dac_dmx_data_1_4 | dac_dmx_data_1_5 | - dac_dmx_data_1_6 | dac_dmx_data_1_7; - dac_data_2 <= dac_dmx_data_2_0 | dac_dmx_data_2_1 | - dac_dmx_data_2_2 | dac_dmx_data_2_3 | - dac_dmx_data_2_4 | dac_dmx_data_2_5 | - dac_dmx_data_2_6 | dac_dmx_data_2_7; - dac_data_3 <= dac_dmx_data_3_0 | dac_dmx_data_3_1 | - dac_dmx_data_3_2 | dac_dmx_data_3_3 | - dac_dmx_data_3_4 | dac_dmx_data_3_5 | - dac_dmx_data_3_6 | dac_dmx_data_3_7; - dac_data_4 <= dac_dmx_data_4_0 | dac_dmx_data_4_1 | - dac_dmx_data_4_2 | dac_dmx_data_4_3 | - dac_dmx_data_4_4 | dac_dmx_data_4_5 | - dac_dmx_data_4_6 | dac_dmx_data_4_7; - dac_data_5 <= dac_dmx_data_5_0 | dac_dmx_data_5_1 | - dac_dmx_data_5_2 | dac_dmx_data_5_3 | - dac_dmx_data_5_4 | dac_dmx_data_5_5 | - dac_dmx_data_5_6 | dac_dmx_data_5_7; - dac_data_6 <= dac_dmx_data_6_0 | dac_dmx_data_6_1 | - dac_dmx_data_6_2 | dac_dmx_data_6_3 | - dac_dmx_data_6_4 | dac_dmx_data_6_5 | - dac_dmx_data_6_6 | dac_dmx_data_6_7; - dac_data_7 <= dac_dmx_data_7_0 | dac_dmx_data_7_1 | - dac_dmx_data_7_2 | dac_dmx_data_7_3 | - dac_dmx_data_7_4 | dac_dmx_data_7_5 | - dac_dmx_data_7_6 | dac_dmx_data_7_7; + dac_valid_int <= dac_valid_d2; + dac_valid_d2 <= dac_valid_d1; + dac_valid_d1 <= dac_dsf_valid; + end + + always @(posedge dac_clk) begin + dac_data_int_0 <= dac_dmx_data_0_0 | dac_dmx_data_0_1 | + dac_dmx_data_0_2 | dac_dmx_data_0_3 | + dac_dmx_data_0_4 | dac_dmx_data_0_5 | + dac_dmx_data_0_6 | dac_dmx_data_0_7; + dac_data_int_1 <= dac_dmx_data_1_0 | dac_dmx_data_1_1 | + dac_dmx_data_1_2 | dac_dmx_data_1_3 | + dac_dmx_data_1_4 | dac_dmx_data_1_5 | + dac_dmx_data_1_6 | dac_dmx_data_1_7; + dac_data_int_2 <= dac_dmx_data_2_0 | dac_dmx_data_2_1 | + dac_dmx_data_2_2 | dac_dmx_data_2_3 | + dac_dmx_data_2_4 | dac_dmx_data_2_5 | + dac_dmx_data_2_6 | dac_dmx_data_2_7; + dac_data_int_3 <= dac_dmx_data_3_0 | dac_dmx_data_3_1 | + dac_dmx_data_3_2 | dac_dmx_data_3_3 | + dac_dmx_data_3_4 | dac_dmx_data_3_5 | + dac_dmx_data_3_6 | dac_dmx_data_3_7; + dac_data_int_4 <= dac_dmx_data_4_0 | dac_dmx_data_4_1 | + dac_dmx_data_4_2 | dac_dmx_data_4_3 | + dac_dmx_data_4_4 | dac_dmx_data_4_5 | + dac_dmx_data_4_6 | dac_dmx_data_4_7; + dac_data_int_5 <= dac_dmx_data_5_0 | dac_dmx_data_5_1 | + dac_dmx_data_5_2 | dac_dmx_data_5_3 | + dac_dmx_data_5_4 | dac_dmx_data_5_5 | + dac_dmx_data_5_6 | dac_dmx_data_5_7; + dac_data_int_6 <= dac_dmx_data_6_0 | dac_dmx_data_6_1 | + dac_dmx_data_6_2 | dac_dmx_data_6_3 | + dac_dmx_data_6_4 | dac_dmx_data_6_5 | + dac_dmx_data_6_6 | dac_dmx_data_6_7; + dac_data_int_7 <= dac_dmx_data_7_0 | dac_dmx_data_7_1 | + dac_dmx_data_7_2 | dac_dmx_data_7_3 | + dac_dmx_data_7_4 | dac_dmx_data_7_5 | + dac_dmx_data_7_6 | dac_dmx_data_7_7; end always @(posedge dac_clk) begin diff --git a/library/util_upack/util_upack_dsf.v b/library/util_upack/util_upack_dsf.v index b76630b5a..6d495d0b2 100644 --- a/library/util_upack/util_upack_dsf.v +++ b/library/util_upack/util_upack_dsf.v @@ -37,197 +37,206 @@ module util_upack_dsf #( - parameter NUM_OF_CHANNELS_P = 4, - parameter NUM_OF_CHANNELS_M = 8, - parameter CHANNEL_DATA_WIDTH = 32, - parameter NUM_OF_CHANNELS_O = 4) ( + parameter CHANNEL_DATA_WIDTH = 32, + parameter NUM_OF_CHANNELS = 4, + parameter MAX_CHANNELS = 8, + parameter SEL_CHANNELS = 4) ( // dac interface - input dac_clk, - input dac_valid, - input [(P_WIDTH-1):0] dac_data, + input dac_clk, + input dac_valid, + input [((CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS)-1):0] dac_data, // dmx interface - input dac_dmx_enable, - output reg dac_dsf_valid, - output reg dac_dsf_sync, - output reg [(M_WIDTH-1):0] dac_dsf_data); + input dac_dmx_enable, + output dac_dsf_req, + output dac_dsf_sync, + output dac_dsf_valid, + output [((CHANNEL_DATA_WIDTH*MAX_CHANNELS)-1):0] dac_dsf_data); + // internal parameters - localparam CH_SCNT = CHANNEL_DATA_WIDTH/16; - localparam P_WIDTH = CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS_P; - localparam M_WIDTH = CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS_M; - localparam O_WIDTH = CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS_O; - localparam E_WIDTH = CHANNEL_DATA_WIDTH*(NUM_OF_CHANNELS_M+1); - localparam CH_DCNT = NUM_OF_CHANNELS_P - NUM_OF_CHANNELS_O; + localparam INT_WIDTH = CHANNEL_DATA_WIDTH*NUM_OF_CHANNELS; + localparam MAX_WIDTH = CHANNEL_DATA_WIDTH*MAX_CHANNELS; + localparam SEL_WIDTH = CHANNEL_DATA_WIDTH*SEL_CHANNELS; + localparam EXT_WIDTH = CHANNEL_DATA_WIDTH*(MAX_CHANNELS+1); // internal registers - reg dac_dmx_valid = 'd0; - reg [ 2:0] dac_samples_int = 'd0; - reg dac_dmx_valid_d = 'd0; - reg dac_dsf_valid_d = 'd0; - reg [ 2:0] dac_samples_int_d = 'd0; - reg [(M_WIDTH-1):0] dac_data_int = 'd0; - reg [(M_WIDTH-1):0] dac_dsf_data_int = 'd0; - reg dac_valid_d1 = 'd0; + reg dac_valid_d1 = 'd0; + reg dac_dsf_req_d1 = 'd0; + reg dac_dsf_sync_d1 = 'd0; + reg [ 2:0] dac_samples_d1 = 'd0; + reg dac_valid_d2 = 'd0; + reg dac_dsf_req_d2 = 'd0; + reg [ 2:0] dac_samples_d2 = 'd0; + reg dac_valid_d3 = 'd0; + reg [(MAX_WIDTH-1):0] dac_data_i_d3 = 'd0; + reg [(MAX_WIDTH-1):0] dac_data_d3 = 'd0; + reg dac_valid_d4 = 'd0; + reg [(MAX_WIDTH-1):0] dac_data_d4 = 'd0; // internal signals - wire [ 2:0] dac_samples_int_s; - wire [(E_WIDTH-1):0] dac_data_s; - wire [(E_WIDTH-1):0] dac_data_int_0_s; - wire [(E_WIDTH-1):0] dac_data_int_1_s; - wire [M_WIDTH:0] dac_dsf_data_s; + wire [ 2:0] dac_samples_i_s; + wire [ 2:0] dac_samples_s; + wire [(EXT_WIDTH-1):0] dac_data_d2_s; + wire [(EXT_WIDTH-1):0] dac_data_i_d2_0_s; + wire [(EXT_WIDTH-1):0] dac_data_i_d2_1_s; + wire [(MAX_WIDTH-1):0] dac_data_d3_s; - // bypass + // bypass (all channels selected) genvar i; generate - if (NUM_OF_CHANNELS_O == NUM_OF_CHANNELS_P) begin - for (i = 0; i < CH_SCNT ; i = i +1) begin: g_dsf_data - assign dac_dsf_data_s[(((i +1) * NUM_OF_CHANNELS_M * 16)-1):(i*NUM_OF_CHANNELS_M*16)] = - dac_data[(((i+1)*16*NUM_OF_CHANNELS_P)-1): (i*16*NUM_OF_CHANNELS_P)]; - end - end - endgenerate + if (SEL_CHANNELS == NUM_OF_CHANNELS) begin - generate - if (NUM_OF_CHANNELS_O == NUM_OF_CHANNELS_P) begin + assign dac_dsf_req = dac_dsf_req_d1; + assign dac_dsf_sync = dac_dsf_sync_d1; + assign dac_dsf_valid = dac_valid_d4; + assign dac_dsf_data = dac_data_d4; - assign dac_samples_int_s = 'd0; - assign dac_data_s = 'd0; - assign dac_data_int_0_s = 'd0; - assign dac_data_int_1_s = 'd0; + assign dac_samples_i_s = 3'd0; + assign dac_samples_s = 'd0; + + always @(posedge dac_clk) begin + dac_valid_d1 <= dac_valid & dac_dmx_enable; + dac_dsf_req_d1 <= dac_valid & dac_dmx_enable; + dac_dsf_sync_d1 <= dac_valid & dac_dmx_enable; + dac_samples_d1 <= 'd0; + end + + assign dac_data_d2_s = 'd0; + assign dac_data_i_d2_0_s = 'd0; + assign dac_data_i_d2_1_s = 'd0; + + always @(posedge dac_clk) begin + dac_valid_d2 <= dac_valid_d1; + dac_dsf_req_d2 <= 'd0; + dac_samples_d2 <= 'd0; + end + + always @(posedge dac_clk) begin + dac_valid_d3 <= 'd0; + dac_data_i_d3 <= 'd0; + dac_data_d3 <= 'd0; + end + + for (i = 0; i < (CHANNEL_DATA_WIDTH/16); i = i +1) begin: g_dsf_data_0 + assign dac_data_d3_s[(((i +1)*MAX_CHANNELS*16)-1):(i*MAX_CHANNELS*16)] = + dac_data[(((i+1)*16*NUM_OF_CHANNELS)-1):(i*16*NUM_OF_CHANNELS)]; + end always @(posedge dac_clk) begin - dac_dmx_valid <= dac_valid & dac_dmx_enable; - dac_dsf_valid <= dac_valid & dac_dmx_enable; - dac_dsf_sync <= dac_valid & dac_dmx_enable; - dac_samples_int <= 'd0; - dac_dmx_valid_d <= 'd0; - dac_dsf_valid_d <= 'd0; - dac_samples_int_d <= 'd0; - dac_data_int <= 'd0; - dac_dsf_data_int <= 'd0; if (dac_dmx_enable == 1'b1) begin - dac_dsf_data <= dac_dsf_data_s[(M_WIDTH-1):0]; + dac_valid_d4 <= dac_valid_d2; + dac_data_d4 <= dac_data_d3_s[(MAX_WIDTH-1):0]; end else begin - dac_dsf_data <= 'd0; + dac_valid_d4 <= 1'd0; + dac_data_d4 <= 'd0; end end + end endgenerate - // data store & forward + // data store & forward (not all channels selected) generate - if (NUM_OF_CHANNELS_P > NUM_OF_CHANNELS_O) begin + if (NUM_OF_CHANNELS > SEL_CHANNELS) begin - assign dac_samples_int_s = (dac_dsf_valid == 1'b1) ? (dac_samples_int + CH_DCNT) : - ((dac_samples_int >= NUM_OF_CHANNELS_O) ? (dac_samples_int - NUM_OF_CHANNELS_O) : dac_samples_int); + assign dac_dsf_req = dac_dsf_req_d1; + assign dac_dsf_sync = dac_dsf_sync_d1; + assign dac_dsf_valid = dac_valid_d4; + assign dac_dsf_data = dac_data_d4; + + assign dac_samples_i_s = (dac_valid_d1 == 1'b1) ? dac_samples_s : dac_samples_d1; + assign dac_samples_s = (dac_dsf_req_d1 == 1'b1) ? (dac_samples_d1+(NUM_OF_CHANNELS-SEL_CHANNELS)) : + ((dac_samples_d1 >= SEL_CHANNELS) ? (dac_samples_d1-SEL_CHANNELS) : dac_samples_d1); always @(posedge dac_clk) begin - dac_dmx_valid <= dac_valid & dac_dmx_enable; - dac_valid_d1 <= dac_valid; - if (dac_valid_d1 == 1'b1) begin - if (dac_samples_int_s < NUM_OF_CHANNELS_O) begin - dac_dsf_valid <= dac_valid & dac_dmx_enable; - end else begin - dac_dsf_valid <= 1'b0; - end - if (dac_samples_int_s == 0) begin - dac_dsf_sync <= dac_valid & dac_dmx_enable; - end else begin - dac_dsf_sync <= 1'b0; - end + dac_valid_d1 <= dac_valid & dac_dmx_enable; + if ((dac_dmx_enable == 1'b0) || (dac_samples_i_s >= SEL_CHANNELS)) begin + dac_dsf_req_d1 <= 1'b0; end else begin - if (dac_samples_int < NUM_OF_CHANNELS_O) begin - dac_dsf_valid <= dac_valid & dac_dmx_enable; - end else begin - dac_dsf_valid <= 1'b0; - end - if (dac_samples_int == 0) begin - dac_dsf_sync <= dac_valid & dac_dmx_enable; - end else begin - dac_dsf_sync <= 1'b0; - end + dac_dsf_req_d1 <= dac_valid; end - if (dac_dmx_valid == 1'b1) begin - dac_samples_int <= dac_samples_int_s; + if ((dac_dmx_enable == 1'b1) && (dac_samples_i_s == 3'd0)) begin + dac_dsf_sync_d1 <= 1'b0; + end else begin + dac_dsf_sync_d1 <= dac_valid; + end + if (dac_dmx_enable == 1'b0) begin + dac_samples_d1 <= 3'd0; + end else if (dac_valid_d1 == 1'b1) begin + dac_samples_d1 <= dac_samples_s; end end - assign dac_data_s[(E_WIDTH-1):P_WIDTH] = 'd0; - assign dac_data_s[(P_WIDTH-1):0] = dac_data; + assign dac_data_d2_s[(EXT_WIDTH-1):INT_WIDTH] = 'd0; + assign dac_data_d2_s[(INT_WIDTH-1):0] = dac_data; - assign dac_data_int_0_s[(E_WIDTH-1):(E_WIDTH-P_WIDTH)] = dac_data; - assign dac_data_int_0_s[((E_WIDTH-P_WIDTH)-1):0] = - dac_data_int[(M_WIDTH-1):(M_WIDTH-(E_WIDTH-P_WIDTH))]; + assign dac_data_i_d2_0_s[(EXT_WIDTH-1):(EXT_WIDTH-INT_WIDTH)] = dac_data; + assign dac_data_i_d2_0_s[((EXT_WIDTH-INT_WIDTH)-1):0] = + dac_data_i_d3[(MAX_WIDTH-1):(MAX_WIDTH-(EXT_WIDTH-INT_WIDTH))]; - assign dac_data_int_1_s[(E_WIDTH-1):(E_WIDTH-(M_WIDTH-O_WIDTH))] = - dac_data_int[(M_WIDTH-1):O_WIDTH]; - assign dac_data_int_1_s[((E_WIDTH-(M_WIDTH-O_WIDTH))-1):0] = 'd0; + assign dac_data_i_d2_1_s[(EXT_WIDTH-1):(EXT_WIDTH-(MAX_WIDTH-SEL_WIDTH))] = + dac_data_i_d3[(MAX_WIDTH-1):SEL_WIDTH]; + assign dac_data_i_d2_1_s[((EXT_WIDTH-(MAX_WIDTH-SEL_WIDTH))-1):0] = 'd0; always @(posedge dac_clk) begin - dac_dmx_valid_d <= dac_dmx_valid; - dac_dsf_valid_d <= dac_dsf_valid; - dac_samples_int_d <= dac_samples_int; - if (dac_dsf_valid_d == 1'b1) begin - dac_data_int <= dac_data_int_0_s[(E_WIDTH-1):(E_WIDTH-M_WIDTH)]; - end else if (dac_dmx_valid_d == 1'b1) begin - dac_data_int <= dac_data_int_1_s[(E_WIDTH-1):(E_WIDTH-M_WIDTH)]; - end + dac_valid_d2 <= dac_valid_d1; + dac_dsf_req_d2 <= dac_dsf_req_d1; + dac_samples_d2 <= dac_samples_d1; end always @(posedge dac_clk) begin - if (dac_dmx_valid_d == 1'b1) begin - case (dac_samples_int_d) - 3'b111: dac_dsf_data_int <= { dac_data_s[((CHANNEL_DATA_WIDTH*1)-1):0], - dac_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*1)]}; - 3'b110: dac_dsf_data_int <= { dac_data_s[((CHANNEL_DATA_WIDTH*2)-1):0], - dac_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*2)]}; - 3'b101: dac_dsf_data_int <= { dac_data_s[((CHANNEL_DATA_WIDTH*3)-1):0], - dac_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*3)]}; - 3'b100: dac_dsf_data_int <= { dac_data_s[((CHANNEL_DATA_WIDTH*4)-1):0], - dac_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*4)]}; - 3'b011: dac_dsf_data_int <= { dac_data_s[((CHANNEL_DATA_WIDTH*5)-1):0], - dac_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*5)]}; - 3'b010: dac_dsf_data_int <= { dac_data_s[((CHANNEL_DATA_WIDTH*6)-1):0], - dac_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*6)]}; - 3'b001: dac_dsf_data_int <= { dac_data_s[((CHANNEL_DATA_WIDTH*7)-1):0], - dac_data_int[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*7)]}; - 3'b000: dac_dsf_data_int <= dac_data_s; - default: dac_dsf_data_int <= 'd0; + dac_valid_d3 <= dac_valid_d2; + if (dac_dsf_req_d2 == 1'b1) begin + dac_data_i_d3 <= dac_data_i_d2_0_s[(EXT_WIDTH-1):(EXT_WIDTH-MAX_WIDTH)]; + end else if (dac_valid_d2 == 1'b1) begin + dac_data_i_d3 <= dac_data_i_d2_1_s[(EXT_WIDTH-1):(EXT_WIDTH-MAX_WIDTH)]; + end + if (dac_valid_d2 == 1'b1) begin + case (dac_samples_d2) + 3'b111: dac_data_d3 <= {dac_data_d2_s[((CHANNEL_DATA_WIDTH*1)-1):0], + dac_data_i_d3[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*1)]}; + 3'b110: dac_data_d3 <= {dac_data_d2_s[((CHANNEL_DATA_WIDTH*2)-1):0], + dac_data_i_d3[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*2)]}; + 3'b101: dac_data_d3 <= {dac_data_d2_s[((CHANNEL_DATA_WIDTH*3)-1):0], + dac_data_i_d3[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*3)]}; + 3'b100: dac_data_d3 <= {dac_data_d2_s[((CHANNEL_DATA_WIDTH*4)-1):0], + dac_data_i_d3[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*4)]}; + 3'b011: dac_data_d3 <= {dac_data_d2_s[((CHANNEL_DATA_WIDTH*5)-1):0], + dac_data_i_d3[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*5)]}; + 3'b010: dac_data_d3 <= {dac_data_d2_s[((CHANNEL_DATA_WIDTH*6)-1):0], + dac_data_i_d3[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*6)]}; + 3'b001: dac_data_d3 <= {dac_data_d2_s[((CHANNEL_DATA_WIDTH*7)-1):0], + dac_data_i_d3[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*7)]}; + 3'b000: dac_data_d3 <= dac_data_d2_s; + default: dac_data_d3 <= 'd0; endcase end end - end - endgenerate - genvar n; - generate - if (NUM_OF_CHANNELS_P > NUM_OF_CHANNELS_O) begin - assign dac_dsf_data_s[M_WIDTH] = 'd0; - for (n = 0; n < CH_SCNT; n = n + 1) begin: g_out - assign dac_dsf_data_s[(((n+1)*NUM_OF_CHANNELS_M*16)-1):(((n*NUM_OF_CHANNELS_M)+NUM_OF_CHANNELS_O)*16)] = 'd0; - assign dac_dsf_data_s[((((n*NUM_OF_CHANNELS_M)+NUM_OF_CHANNELS_O)*16)-1):(n*NUM_OF_CHANNELS_M*16)] = - dac_dsf_data_int[(((n+1)*NUM_OF_CHANNELS_O*16)-1):(n*NUM_OF_CHANNELS_O*16)]; + for (i = 0; i < (CHANNEL_DATA_WIDTH/16); i = i + 1) begin: g_dsf_data_1 + assign dac_data_d3_s[(((i+1)*MAX_CHANNELS*16)-1):(((i*MAX_CHANNELS)+SEL_CHANNELS)*16)] = 'd0; + assign dac_data_d3_s[((((i*MAX_CHANNELS)+SEL_CHANNELS)*16)-1):(i*MAX_CHANNELS*16)] = + dac_data_d3[(((i+1)*SEL_CHANNELS*16)-1):(i*SEL_CHANNELS*16)]; end - end - endgenerate - generate - if (NUM_OF_CHANNELS_P > NUM_OF_CHANNELS_O) begin always @(posedge dac_clk) begin if (dac_dmx_enable == 1'b1) begin - dac_dsf_data <= dac_dsf_data_s[(M_WIDTH-1):0]; + dac_valid_d4 <= dac_valid_d3; + dac_data_d4 <= dac_data_d3_s[(MAX_WIDTH-1):0]; end else begin - dac_dsf_data <= 'd0; + dac_valid_d4 <= 1'd0; + dac_data_d4 <= 'd0; end end + end endgenerate