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projects/fmcomms1: added

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Rejeesh Kutty 2014-03-11 12:16:25 -04:00
parent a76d6c4686
commit f8ab734918
13 changed files with 1328 additions and 0 deletions
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210
projects/fmcomms1/common/fmcomms1_bd.tcl Normal file
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# dac interface
set dac_clk_in_p [create_bd_port -dir I dac_clk_in_p]
set dac_clk_in_n [create_bd_port -dir I dac_clk_in_n]
set dac_clk_out_p [create_bd_port -dir O dac_clk_out_p]
set dac_clk_out_n [create_bd_port -dir O dac_clk_out_n]
set dac_frame_out_p [create_bd_port -dir O dac_frame_out_p]
set dac_frame_out_n [create_bd_port -dir O dac_frame_out_n]
set dac_data_out_p [create_bd_port -dir O -from 15 -to 0 dac_data_out_p]
set dac_data_out_n [create_bd_port -dir O -from 15 -to 0 dac_data_out_n]
# adc interface
set adc_clk_in_p [create_bd_port -dir I adc_clk_in_p]
set adc_clk_in_n [create_bd_port -dir I adc_clk_in_n]
set adc_or_in_p [create_bd_port -dir I adc_or_in_p]
set adc_or_in_n [create_bd_port -dir I adc_or_in_n]
set adc_data_in_p [create_bd_port -dir I -from 13 -to 0 adc_data_in_p]
set adc_data_in_n [create_bd_port -dir I -from 13 -to 0 adc_data_in_n]
# reference clock
set ref_clk [create_bd_port -dir O ref_clk]
# dac peripherals
set axi_ad9122 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9122:1.0 axi_ad9122]
set axi_ad9122_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9122_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9122_dma
set_property -dict [list CONFIG.C_ADDR_ALIGN_BITS {4}] $axi_ad9122_dma
set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9122_dma
set_property -dict [list CONFIG.C_M_DEST_AXI_DATA_WIDTH {64}] $axi_ad9122_dma
set axi_ad9122_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9122_dma_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9122_dma_interconnect
# adc peripherals
set axi_ad9643 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9643:1.0 axi_ad9643]
set sys_ad9643_fifo [create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:11.0 sys_ad9643_fifo]
set_property -dict [list CONFIG.Fifo_Implementation {Independent_Clocks_Block_RAM}] $sys_ad9643_fifo
set_property -dict [list CONFIG.Input_Data_Width {32}] $sys_ad9643_fifo
set_property -dict [list CONFIG.Input_Depth {32}] $sys_ad9643_fifo
set_property -dict [list CONFIG.Output_Data_Width {64}] $sys_ad9643_fifo
set_property -dict [list CONFIG.Overflow_Flag {true}] $sys_ad9643_fifo
set_property -dict [list CONFIG.Reset_Pin {true}] $sys_ad9643_fifo
set sys_ad9643_util_wfifo [ create_bd_cell -type ip -vlnv analog.com:user:util_wfifo:1.0 sys_ad9643_util_wfifo]
set_property -dict [list CONFIG.M_DATA_WIDTH {32}] $sys_ad9643_util_wfifo
set_property -dict [list CONFIG.S_DATA_WIDTH {64}] $sys_ad9643_util_wfifo
set axi_ad9643_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9643_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9643_dma
set_property -dict [list CONFIG.C_M_DEST_AXI_DATA_WIDTH {64}] $axi_ad9643_dma
set axi_ad9643_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9643_dma_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9643_dma_interconnect
# additions to default configuration
set_property -dict [list CONFIG.NUM_MI {11}] $axi_cpu_interconnect
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {125.0}] $sys_ps7
# reference clock shared with audio clock
set_property -dict [list CONFIG.CLKOUT2_USED {true}] $sys_audio_clkgen
set_property -dict [list CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {30}] $sys_audio_clkgen
# connections (dac)
connect_bd_net -net dac_div_clk [get_bd_pins axi_ad9122/dac_div_clk]
connect_bd_net -net dac_div_clk [get_bd_pins axi_ad9122_dma/fifo_rd_clk]
connect_bd_net -net axi_ad9122_dac_clk_in_p [get_bd_ports dac_clk_in_p] [get_bd_pins axi_ad9122/dac_clk_in_p]
connect_bd_net -net axi_ad9122_dac_clk_in_n [get_bd_ports dac_clk_in_n] [get_bd_pins axi_ad9122/dac_clk_in_n]
connect_bd_net -net axi_ad9122_dac_clk_out_p [get_bd_ports dac_clk_out_p] [get_bd_pins axi_ad9122/dac_clk_out_p]
connect_bd_net -net axi_ad9122_dac_clk_out_n [get_bd_ports dac_clk_out_n] [get_bd_pins axi_ad9122/dac_clk_out_n]
connect_bd_net -net axi_ad9122_dac_frame_out_p [get_bd_ports dac_frame_out_p] [get_bd_pins axi_ad9122/dac_frame_out_p]
connect_bd_net -net axi_ad9122_dac_frame_out_n [get_bd_ports dac_frame_out_n] [get_bd_pins axi_ad9122/dac_frame_out_n]
connect_bd_net -net axi_ad9122_dac_data_out_p [get_bd_ports dac_data_out_p] [get_bd_pins axi_ad9122/dac_data_out_p]
connect_bd_net -net axi_ad9122_dac_data_out_n [get_bd_ports dac_data_out_n] [get_bd_pins axi_ad9122/dac_data_out_n]
connect_bd_net -net axi_ad9122_dac_drd [get_bd_pins axi_ad9122/dac_drd] [get_bd_pins axi_ad9122_dma/fifo_rd_en]
connect_bd_net -net axi_ad9122_dac_ddata [get_bd_pins axi_ad9122/dac_ddata_64] [get_bd_pins axi_ad9122_dma/fifo_rd_dout]
connect_bd_net -net axi_ad9122_dac_dunf [get_bd_pins axi_ad9122/dac_dunf] [get_bd_pins axi_ad9122_dma/fifo_rd_underflow]
connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_pins sys_concat_intc/In3]
# connections (adc)
connect_bd_net -net adc_clk [get_bd_pins axi_ad9643/adc_clk]
connect_bd_net -net adc_clk [get_bd_pins axi_ad9643_dma/fifo_wr_clk]
connect_bd_net -net adc_clk [get_bd_pins sys_ad9643_util_wfifo/clk]
connect_bd_net -net adc_clk [get_bd_pins sys_ad9643_fifo/wr_clk]
connect_bd_net -net adc_clk [get_bd_pins sys_ad9643_fifo/rd_clk]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9643/delay_clk]
connect_bd_net -net sys_100m_resetn [get_bd_pins sys_ad9643_util_wfifo/rstn]
connect_bd_net -net axi_ad9643_adc_clk_in_p [get_bd_ports adc_clk_in_p] [get_bd_pins axi_ad9643/adc_clk_in_p]
connect_bd_net -net axi_ad9643_adc_clk_in_n [get_bd_ports adc_clk_in_n] [get_bd_pins axi_ad9643/adc_clk_in_n]
connect_bd_net -net axi_ad9643_adc_or_in_p [get_bd_ports adc_or_in_p] [get_bd_pins axi_ad9643/adc_or_in_p]
connect_bd_net -net axi_ad9643_adc_or_in_n [get_bd_ports adc_or_in_n] [get_bd_pins axi_ad9643/adc_or_in_n]
connect_bd_net -net axi_ad9643_adc_data_in_p [get_bd_ports adc_data_in_p] [get_bd_pins axi_ad9643/adc_data_in_p]
connect_bd_net -net axi_ad9643_adc_data_in_n [get_bd_ports adc_data_in_n] [get_bd_pins axi_ad9643/adc_data_in_n]
connect_bd_net -net axi_ad9643_adc_dsync [get_bd_pins axi_ad9643/adc_dsync] [get_bd_pins axi_ad9643_dma/fifo_wr_sync]
connect_bd_net -net axi_ad9643_adc_dwr [get_bd_pins axi_ad9643/adc_dwr] [get_bd_pins sys_ad9643_util_wfifo/m_wr]
connect_bd_net -net axi_ad9643_adc_ddata [get_bd_pins axi_ad9643/adc_ddata] [get_bd_pins sys_ad9643_util_wfifo/m_wdata]
connect_bd_net -net axi_ad9643_adc_dovf [get_bd_pins axi_ad9643/adc_dovf] [get_bd_pins sys_ad9643_util_wfifo/m_wovf]
connect_bd_net -net axi_ad9643_dma_dwr [get_bd_pins sys_ad9643_util_wfifo/s_wr] [get_bd_pins axi_ad9643_dma/fifo_wr_en]
connect_bd_net -net axi_ad9643_dma_ddata [get_bd_pins sys_ad9643_util_wfifo/s_wdata] [get_bd_pins axi_ad9643_dma/fifo_wr_din]
connect_bd_net -net axi_ad9643_dma_dovf [get_bd_pins sys_ad9643_util_wfifo/s_wovf] [get_bd_pins axi_ad9643_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9643_dma_irq [get_bd_pins axi_ad9643_dma/irq] [get_bd_pins sys_concat_intc/In2]
connect_bd_net -net axi_ad9643_fifo_rst [get_bd_pins sys_ad9643_util_wfifo/fifo_rst] [get_bd_pins sys_ad9643_fifo/rst]
connect_bd_net -net axi_ad9643_fifo_wr [get_bd_pins sys_ad9643_util_wfifo/fifo_wr] [get_bd_pins sys_ad9643_fifo/wr_en]
connect_bd_net -net axi_ad9643_fifo_wdata [get_bd_pins sys_ad9643_util_wfifo/fifo_wdata] [get_bd_pins sys_ad9643_fifo/din]
connect_bd_net -net axi_ad9643_fifo_wfull [get_bd_pins sys_ad9643_util_wfifo/fifo_wfull] [get_bd_pins sys_ad9643_fifo/full]
connect_bd_net -net axi_ad9643_fifo_wovf [get_bd_pins sys_ad9643_util_wfifo/fifo_wovf] [get_bd_pins sys_ad9643_fifo/overflow]
connect_bd_net -net axi_ad9643_fifo_rd [get_bd_pins sys_ad9643_util_wfifo/fifo_rd] [get_bd_pins sys_ad9643_fifo/rd_en]
connect_bd_net -net axi_ad9643_fifo_rdata [get_bd_pins sys_ad9643_util_wfifo/fifo_rdata] [get_bd_pins sys_ad9643_fifo/dout]
connect_bd_net -net axi_ad9643_fifo_rempty [get_bd_pins sys_ad9643_util_wfifo/fifo_rempty] [get_bd_pins sys_ad9643_fifo/empty]
# interconnect (cpu)
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9122/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9643/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9643_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9122_dma/s_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9122/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9122_dma/s_axi_aclk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9122/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9122_dma/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9643/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9643_dma/s_axi_aclk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9643/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9643_dma/s_axi_aresetn]
# memory interconnects share the same clock (fclk2)
set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2]
set sys_fmc_dma_resetn_source [get_bd_pins sys_ps7/FCLK_RESET2_N]
connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source
# interconnect (mem/dac)
connect_bd_intf_net -intf_net axi_ad9122_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9122_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9122_dma/m_src_axi]
connect_bd_intf_net -intf_net axi_ad9122_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9122_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9122_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9122_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9122_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9122_dma/m_src_axi_aclk]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK]
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9122_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9122_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9122_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9122_dma/m_src_axi_aresetn]
# interconnect (mem/adc)
connect_bd_intf_net -intf_net axi_ad9643_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9643_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9643_dma/m_dest_axi]
connect_bd_intf_net -intf_net axi_ad9643_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9643_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9643_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9643_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9643_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9643_dma/m_dest_axi_aclk]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK]
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9643_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9643_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9643_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9643_dma/m_dest_axi_aresetn]
# ila (adc)
set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_adc]
set_property -dict [list CONFIG.C_NUM_OF_PROBES {1}] $ila_adc
set_property -dict [list CONFIG.C_PROBE0_WIDTH {28}] $ila_adc
set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
connect_bd_net -net adc_clk [get_bd_pins ila_adc/clk]
connect_bd_net -net axi_ad9643_adc_mon_data [get_bd_pins axi_ad9643/adc_mon_data] [get_bd_pins ila_adc/probe0]
# reference clock
connect_bd_net -net fmcomms1_ref_clk [get_bd_pins sys_audio_clkgen/clk_out2] [get_bd_ports ref_clk]
# address map
create_bd_addr_seg -range 0x00010000 -offset 0x74200000 [get_bd_addr_spaces sys_ps7/Data] [get_bd_addr_segs axi_ad9122/s_axi/axi_lite] SEG_data_ad9122
create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 [get_bd_addr_spaces sys_ps7/Data] [get_bd_addr_segs axi_ad9643_dma/s_axi/axi_lite] SEG_data_ad9122_dma
create_bd_addr_seg -range 0x00010000 -offset 0x79020000 [get_bd_addr_spaces sys_ps7/Data] [get_bd_addr_segs axi_ad9643/s_axi/axi_lite] SEG_data_ad9643
create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 [get_bd_addr_spaces sys_ps7/Data] [get_bd_addr_segs axi_ad9122_dma/s_axi/axi_lite] SEG_data_ad9643_dma
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9643_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9122_dma/m_src_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm

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projects/fmcomms1/zc702/system_bd.tcl Normal file
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source $ad_hdl_dir/projects/common/zc702/zc702_system_bd.tcl
source ../common/fmcomms1_bd.tcl
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces axi_ad9643_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces axi_ad9122_dma/m_src_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm

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projects/fmcomms1/zc702/system_constr.xdc Normal file
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# reference
set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_p] ; ## FMC1_LPC_LA17_CC_P
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_n] ; ## FMC1_LPC_LA17_CC_N
# dac
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_p] ; ## FMC1_LPC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_n] ; ## FMC1_LPC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVDS_25} [get_ports dac_clk_out_p] ; ## FMC1_LPC_LA21_P
set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVDS_25} [get_ports dac_clk_out_n] ; ## FMC1_LPC_LA21_N
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVDS_25} [get_ports dac_frame_out_p] ; ## FMC1_LPC_LA11_P
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVDS_25} [get_ports dac_frame_out_n] ; ## FMC1_LPC_LA11_N
set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[0]] ; ## FMC1_LPC_LA32_P
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[0]] ; ## FMC1_LPC_LA32_N
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[1]] ; ## FMC1_LPC_LA33_P
set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[1]] ; ## FMC1_LPC_LA33_N
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[2]] ; ## FMC1_LPC_LA30_P
set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[2]] ; ## FMC1_LPC_LA30_N
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[3]] ; ## FMC1_LPC_LA28_P
set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[3]] ; ## FMC1_LPC_LA28_N
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[4]] ; ## FMC1_LPC_LA31_P
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[4]] ; ## FMC1_LPC_LA31_N
set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[5]] ; ## FMC1_LPC_LA29_P
set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[5]] ; ## FMC1_LPC_LA29_N
set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[6]] ; ## FMC1_LPC_LA24_P
set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[6]] ; ## FMC1_LPC_LA24_N
set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[7]] ; ## FMC1_LPC_LA25_P
set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[7]] ; ## FMC1_LPC_LA25_N
set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[8]] ; ## FMC1_LPC_LA22_P
set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[8]] ; ## FMC1_LPC_LA22_N
set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[9]] ; ## FMC1_LPC_LA27_P
set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[9]] ; ## FMC1_LPC_LA27_N
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[10]] ; ## FMC1_LPC_LA26_P
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[10]] ; ## FMC1_LPC_LA26_N
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[11]] ; ## FMC1_LPC_LA23_P
set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[11]] ; ## FMC1_LPC_LA23_N
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[12]] ; ## FMC1_LPC_LA19_P
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[12]] ; ## FMC1_LPC_LA19_N
set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[13]] ; ## FMC1_LPC_LA20_P
set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[13]] ; ## FMC1_LPC_LA20_N
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[14]] ; ## FMC1_LPC_LA15_P
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[14]] ; ## FMC1_LPC_LA15_N
set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[15]] ; ## FMC1_LPC_LA16_P
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[15]] ; ## FMC1_LPC_LA16_N
# adc
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## FMC1_LPC_CLK1_M2C_P
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## FMC1_LPC_CLK1_M2C_N
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_p] ; ## FMC1_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_n] ; ## FMC1_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## FMC1_LPC_LA18_CC_P
set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## FMC1_LPC_LA18_CC_N
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## FMC1_LPC_LA14_P
set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## FMC1_LPC_LA14_N
set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## FMC1_LPC_LA13_P
set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## FMC1_LPC_LA13_N
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## FMC1_LPC_LA03_P
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## FMC1_LPC_LA03_N
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## FMC1_LPC_LA05_P
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## FMC1_LPC_LA05_N
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## FMC1_LPC_LA10_P
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## FMC1_LPC_LA10_N
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## FMC1_LPC_LA12_P
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## FMC1_LPC_LA12_N
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## FMC1_LPC_LA07_P
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## FMC1_LPC_LA07_N
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[8]] ; ## FMC1_LPC_LA02_P
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[8]] ; ## FMC1_LPC_LA02_N
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[9]] ; ## FMC1_LPC_LA04_P
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[9]] ; ## FMC1_LPC_LA04_N
set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[10]] ; ## FMC1_LPC_LA09_P
set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[10]] ; ## FMC1_LPC_LA09_N
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[11]] ; ## FMC1_LPC_LA08_P
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[11]] ; ## FMC1_LPC_LA08_N
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[12]] ; ## FMC1_LPC_LA06_P
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[12]] ; ## FMC1_LPC_LA06_N
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[13]] ; ## FMC1_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[13]] ; ## FMC1_LPC_LA01_CC_N
# clocks
create_clock -name dac_clk_in -period 2.10 [get_ports dac_clk_in_p]
create_clock -name adc_clk_in -period 4.00 [get_ports adc_clk_in_p]
create_clock -name dac_div_clk -period 8.40 [get_pins i_system_wrapper/system_i/axi_ad9122/dac_div_clk]
create_clock -name adc_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9643/adc_clk]
create_clock -name fmc_dma_clk -period 8.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
set_clock_groups -asynchronous -group {dac_div_clk}
set_clock_groups -asynchronous -group {adc_clk}
set_clock_groups -asynchronous -group {fmc_dma_clk}

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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
adi_project_create fmcomms1_zc702
adi_project_files fmcomms1_zc702 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/projects/common/zc702/zc702_system_constr.xdc" ]
adi_project_run fmcomms1_zc702

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_frame_out_p,
dac_frame_out_n,
dac_data_out_p,
dac_data_out_n,
adc_clk_in_p,
adc_clk_in_n,
adc_or_in_p,
adc_or_in_n,
adc_data_in_p,
adc_data_in_n,
ref_clk_out_p,
ref_clk_out_n,
iic_scl,
iic_sda);
inout [14:0] DDR_addr;
inout [ 2:0] DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [ 3:0] DDR_dm;
inout [31:0] DDR_dq;
inout [ 3:0] DDR_dqs_n;
inout [ 3:0] DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0] FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout [15:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [15:0] hdmi_data;
output spdif;
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output dac_frame_out_p;
output dac_frame_out_n;
output [15:0] dac_data_out_p;
output [15:0] dac_data_out_n;
input adc_clk_in_p;
input adc_clk_in_n;
input adc_or_in_n;
input adc_or_in_p;
input [13:0] adc_data_in_n;
input [13:0] adc_data_in_p;
output ref_clk_out_p;
output ref_clk_out_n;
inout iic_scl;
inout iic_sda;
// internal signals
wire [31:0] gpio_i;
wire [31:0] gpio_o;
wire [31:0] gpio_t;
wire ref_clk;
wire oddr_ref_clk;
// instantiations
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
i_oddr_ref_clk (
.S (1'b0),
.CE (1'b1),
.R (1'b0),
.C (ref_clk),
.D1 (1'b1),
.D2 (1'b0),
.Q (oddr_ref_clk));
OBUFDS i_obufds_ref_clk (
.I (oddr_ref_clk),
.O (ref_clk_out_p),
.OB (ref_clk_out_n));
genvar n;
generate
for (n = 0; n <= 15; n = n + 1) begin: g_iobuf_gpio_bd
IOBUF i_iobuf_gpio_bd (
.I (gpio_o[n]),
.O (gpio_i[n]),
.T (gpio_t[n]),
.IO (gpio_bd[n]));
end
endgenerate
system_wrapper i_system_wrapper (
.DDR_addr (DDR_addr),
.DDR_ba (DDR_ba),
.DDR_cas_n (DDR_cas_n),
.DDR_ck_n (DDR_ck_n),
.DDR_ck_p (DDR_ck_p),
.DDR_cke (DDR_cke),
.DDR_cs_n (DDR_cs_n),
.DDR_dm (DDR_dm),
.DDR_dq (DDR_dq),
.DDR_dqs_n (DDR_dqs_n),
.DDR_dqs_p (DDR_dqs_p),
.DDR_odt (DDR_odt),
.DDR_ras_n (DDR_ras_n),
.DDR_reset_n (DDR_reset_n),
.DDR_we_n (DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.GPIO_I (gpio_i),
.GPIO_O (gpio_o),
.GPIO_T (gpio_t),
.adc_clk_in_n (adc_clk_in_n),
.adc_clk_in_p (adc_clk_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_or_in_n (adc_or_in_n),
.adc_or_in_p (adc_or_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_data_out_n (dac_data_out_n),
.dac_data_out_p (dac_data_out_p),
.dac_frame_out_n (dac_frame_out_n),
.dac_frame_out_p (dac_frame_out_p),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ref_clk (ref_clk),
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************

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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source ../common/fmcomms1_bd.tcl

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# reference
set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_p] ; ## FMC1_LPC_LA17_CC_P
set_property -dict {PACKAGE_PIN AC27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_n] ; ## FMC1_LPC_LA17_CC_N
# dac
set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_p] ; ## FMC1_LPC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_n] ; ## FMC1_LPC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVDS_25} [get_ports dac_clk_out_p] ; ## FMC1_LPC_LA21_P
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVDS_25} [get_ports dac_clk_out_n] ; ## FMC1_LPC_LA21_N
set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25} [get_ports dac_frame_out_p] ; ## FMC1_LPC_LA11_P
set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVDS_25} [get_ports dac_frame_out_n] ; ## FMC1_LPC_LA11_N
set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[0]] ; ## FMC1_LPC_LA32_P
set_property -dict {PACKAGE_PIN Y27 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[0]] ; ## FMC1_LPC_LA32_N
set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[1]] ; ## FMC1_LPC_LA33_P
set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[1]] ; ## FMC1_LPC_LA33_N
set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[2]] ; ## FMC1_LPC_LA30_P
set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[2]] ; ## FMC1_LPC_LA30_N
set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[3]] ; ## FMC1_LPC_LA28_P
set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[3]] ; ## FMC1_LPC_LA28_N
set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[4]] ; ## FMC1_LPC_LA31_P
set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[4]] ; ## FMC1_LPC_LA31_N
set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[5]] ; ## FMC1_LPC_LA29_P
set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[5]] ; ## FMC1_LPC_LA29_N
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[6]] ; ## FMC1_LPC_LA24_P
set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[6]] ; ## FMC1_LPC_LA24_N
set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[7]] ; ## FMC1_LPC_LA25_P
set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[7]] ; ## FMC1_LPC_LA25_N
set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[8]] ; ## FMC1_LPC_LA22_P
set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[8]] ; ## FMC1_LPC_LA22_N
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[9]] ; ## FMC1_LPC_LA27_P
set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[9]] ; ## FMC1_LPC_LA27_N
set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[10]] ; ## FMC1_LPC_LA26_P
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[10]] ; ## FMC1_LPC_LA26_N
set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[11]] ; ## FMC1_LPC_LA23_P
set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[11]] ; ## FMC1_LPC_LA23_N
set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[12]] ; ## FMC1_LPC_LA19_P
set_property -dict {PACKAGE_PIN AH27 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[12]] ; ## FMC1_LPC_LA19_N
set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[13]] ; ## FMC1_LPC_LA20_P
set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[13]] ; ## FMC1_LPC_LA20_N
set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[14]] ; ## FMC1_LPC_LA15_P
set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[14]] ; ## FMC1_LPC_LA15_N
set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[15]] ; ## FMC1_LPC_LA16_P
set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[15]] ; ## FMC1_LPC_LA16_N
# adc
set_property -dict {PACKAGE_PIN AC28 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## FMC1_LPC_CLK1_M2C_P
set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## FMC1_LPC_CLK1_M2C_N
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_p] ; ## FMC1_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_n] ; ## FMC1_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN AE27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## FMC1_LPC_LA18_CC_P
set_property -dict {PACKAGE_PIN AF27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## FMC1_LPC_LA18_CC_N
set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## FMC1_LPC_LA14_P
set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## FMC1_LPC_LA14_N
set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## FMC1_LPC_LA13_P
set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## FMC1_LPC_LA13_N
set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## FMC1_LPC_LA03_P
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## FMC1_LPC_LA03_N
set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## FMC1_LPC_LA05_P
set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## FMC1_LPC_LA05_N
set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## FMC1_LPC_LA10_P
set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## FMC1_LPC_LA10_N
set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## FMC1_LPC_LA12_P
set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## FMC1_LPC_LA12_N
set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## FMC1_LPC_LA07_P
set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## FMC1_LPC_LA07_N
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[8]] ; ## FMC1_LPC_LA02_P
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[8]] ; ## FMC1_LPC_LA02_N
set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[9]] ; ## FMC1_LPC_LA04_P
set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[9]] ; ## FMC1_LPC_LA04_N
set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[10]] ; ## FMC1_LPC_LA09_P
set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[10]] ; ## FMC1_LPC_LA09_N
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[11]] ; ## FMC1_LPC_LA08_P
set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[11]] ; ## FMC1_LPC_LA08_N
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[12]] ; ## FMC1_LPC_LA06_P
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[12]] ; ## FMC1_LPC_LA06_N
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[13]] ; ## FMC1_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[13]] ; ## FMC1_LPC_LA01_CC_N
# clocks
create_clock -name dac_clk_in -period 2.00 [get_ports dac_clk_in_p]
create_clock -name adc_clk_in -period 4.00 [get_ports adc_clk_in_p]
create_clock -name dac_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_ad9122/dac_div_clk]
create_clock -name adc_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9643/adc_clk]
set_clock_groups -asynchronous -group {dac_div_clk}
set_clock_groups -asynchronous -group {adc_clk}

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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
adi_project_create fmcomms1_zc706
adi_project_files fmcomms1_zc706 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
adi_project_run fmcomms1_zc706

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_frame_out_p,
dac_frame_out_n,
dac_data_out_p,
dac_data_out_n,
adc_clk_in_p,
adc_clk_in_n,
adc_or_in_p,
adc_or_in_n,
adc_data_in_p,
adc_data_in_n,
ref_clk_out_p,
ref_clk_out_n,
iic_scl,
iic_sda);
inout [14:0] DDR_addr;
inout [ 2:0] DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [ 3:0] DDR_dm;
inout [31:0] DDR_dq;
inout [ 3:0] DDR_dqs_n;
inout [ 3:0] DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0] FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout [14:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [23:0] hdmi_data;
output spdif;
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output dac_frame_out_p;
output dac_frame_out_n;
output [15:0] dac_data_out_p;
output [15:0] dac_data_out_n;
input adc_clk_in_p;
input adc_clk_in_n;
input adc_or_in_p;
input adc_or_in_n;
input [13:0] adc_data_in_p;
input [13:0] adc_data_in_n;
output ref_clk_out_p;
output ref_clk_out_n;
inout iic_scl;
inout iic_sda;
// internal signals
wire [31:0] gpio_i;
wire [31:0] gpio_o;
wire [31:0] gpio_t;
wire ref_clk;
wire oddr_ref_clk;
// instantiations
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
i_oddr_ref_clk (
.S (1'b0),
.CE (1'b1),
.R (1'b0),
.C (ref_clk),
.D1 (1'b1),
.D2 (1'b0),
.Q (oddr_ref_clk));
OBUFDS i_obufds_ref_clk (
.I (oddr_ref_clk),
.O (ref_clk_out_p),
.OB (ref_clk_out_n));
genvar n;
generate
for (n = 0; n <= 14; n = n + 1) begin: g_iobuf_gpio_bd
IOBUF i_iobuf_gpio_bd (
.I (gpio_o[n]),
.O (gpio_i[n]),
.T (gpio_t[n]),
.IO (gpio_bd[n]));
end
endgenerate
system_wrapper i_system_wrapper (
.DDR_addr (DDR_addr),
.DDR_ba (DDR_ba),
.DDR_cas_n (DDR_cas_n),
.DDR_ck_n (DDR_ck_n),
.DDR_ck_p (DDR_ck_p),
.DDR_cke (DDR_cke),
.DDR_cs_n (DDR_cs_n),
.DDR_dm (DDR_dm),
.DDR_dq (DDR_dq),
.DDR_dqs_n (DDR_dqs_n),
.DDR_dqs_p (DDR_dqs_p),
.DDR_odt (DDR_odt),
.DDR_ras_n (DDR_ras_n),
.DDR_reset_n (DDR_reset_n),
.DDR_we_n (DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.GPIO_I (gpio_i),
.GPIO_O (gpio_o),
.GPIO_T (gpio_t),
.adc_clk_in_n (adc_clk_in_n),
.adc_clk_in_p (adc_clk_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_or_in_n (adc_or_in_n),
.adc_or_in_p (adc_or_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_data_out_n (dac_data_out_n),
.dac_data_out_p (dac_data_out_p),
.dac_frame_out_n (dac_frame_out_n),
.dac_frame_out_p (dac_frame_out_p),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ref_clk (ref_clk),
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************

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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
source ../common/fmcomms1_bd.tcl

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# reference
set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_p] ; ## FMC1_LPC_LA17_CC_P
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_out_n] ; ## FMC1_LPC_LA17_CC_N
# dac
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_p] ; ## FMC1_LPC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_n] ; ## FMC1_LPC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVDS_25} [get_ports dac_clk_out_p] ; ## FMC1_LPC_LA21_P
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVDS_25} [get_ports dac_clk_out_n] ; ## FMC1_LPC_LA21_N
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVDS_25} [get_ports dac_frame_out_p] ; ## FMC1_LPC_LA11_P
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVDS_25} [get_ports dac_frame_out_n] ; ## FMC1_LPC_LA11_N
set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[0]] ; ## FMC1_LPC_LA32_P
set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[0]] ; ## FMC1_LPC_LA32_N
set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[1]] ; ## FMC1_LPC_LA33_P
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[1]] ; ## FMC1_LPC_LA33_N
set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[2]] ; ## FMC1_LPC_LA30_P
set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[2]] ; ## FMC1_LPC_LA30_N
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[3]] ; ## FMC1_LPC_LA28_P
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[3]] ; ## FMC1_LPC_LA28_N
set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[4]] ; ## FMC1_LPC_LA31_P
set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[4]] ; ## FMC1_LPC_LA31_N
set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[5]] ; ## FMC1_LPC_LA29_P
set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[5]] ; ## FMC1_LPC_LA29_N
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[6]] ; ## FMC1_LPC_LA24_P
set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[6]] ; ## FMC1_LPC_LA24_N
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[7]] ; ## FMC1_LPC_LA25_P
set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[7]] ; ## FMC1_LPC_LA25_N
set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[8]] ; ## FMC1_LPC_LA22_P
set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[8]] ; ## FMC1_LPC_LA22_N
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[9]] ; ## FMC1_LPC_LA27_P
set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[9]] ; ## FMC1_LPC_LA27_N
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[10]] ; ## FMC1_LPC_LA26_P
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[10]] ; ## FMC1_LPC_LA26_N
set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[11]] ; ## FMC1_LPC_LA23_P
set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[11]] ; ## FMC1_LPC_LA23_N
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[12]] ; ## FMC1_LPC_LA19_P
set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[12]] ; ## FMC1_LPC_LA19_N
set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[13]] ; ## FMC1_LPC_LA20_P
set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[13]] ; ## FMC1_LPC_LA20_N
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[14]] ; ## FMC1_LPC_LA15_P
set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[14]] ; ## FMC1_LPC_LA15_N
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVDS_25} [get_ports dac_data_out_p[15]] ; ## FMC1_LPC_LA16_P
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVDS_25} [get_ports dac_data_out_n[15]] ; ## FMC1_LPC_LA16_N
# adc
set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## FMC1_LPC_CLK1_M2C_P
set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## FMC1_LPC_CLK1_M2C_N
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_p] ; ## FMC1_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_in_n] ; ## FMC1_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## FMC1_LPC_LA18_CC_P
set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## FMC1_LPC_LA18_CC_N
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## FMC1_LPC_LA14_P
set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## FMC1_LPC_LA14_N
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## FMC1_LPC_LA13_P
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## FMC1_LPC_LA13_N
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## FMC1_LPC_LA03_P
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## FMC1_LPC_LA03_N
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## FMC1_LPC_LA05_P
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## FMC1_LPC_LA05_N
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## FMC1_LPC_LA10_P
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## FMC1_LPC_LA10_N
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## FMC1_LPC_LA12_P
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## FMC1_LPC_LA12_N
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## FMC1_LPC_LA07_P
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## FMC1_LPC_LA07_N
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[8]] ; ## FMC1_LPC_LA02_P
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[8]] ; ## FMC1_LPC_LA02_N
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[9]] ; ## FMC1_LPC_LA04_P
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[9]] ; ## FMC1_LPC_LA04_N
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[10]] ; ## FMC1_LPC_LA09_P
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[10]] ; ## FMC1_LPC_LA09_N
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[11]] ; ## FMC1_LPC_LA08_P
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[11]] ; ## FMC1_LPC_LA08_N
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[12]] ; ## FMC1_LPC_LA06_P
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[12]] ; ## FMC1_LPC_LA06_N
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[13]] ; ## FMC1_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[13]] ; ## FMC1_LPC_LA01_CC_N
# clocks
create_clock -name dac_clk_in -period 2.10 [get_ports dac_clk_in_p]
create_clock -name adc_clk_in -period 4.00 [get_ports adc_clk_in_p]
create_clock -name dac_div_clk -period 8.40 [get_pins i_system_wrapper/system_i/axi_ad9122/dac_div_clk]
create_clock -name adc_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9643/adc_clk]
set_clock_groups -asynchronous -group {dac_div_clk}
set_clock_groups -asynchronous -group {adc_clk}

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projects/fmcomms1/zed/system_project.tcl Normal file
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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
adi_project_create fmcomms1_zed
adi_project_files fmcomms1_zed [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ]
adi_project_run fmcomms1_zed

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projects/fmcomms1/zed/system_top.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
i2s_mclk,
i2s_bclk,
i2s_lrclk,
i2s_sdata_out,
i2s_sdata_in,
spdif,
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_frame_out_p,
dac_frame_out_n,
dac_data_out_p,
dac_data_out_n,
adc_clk_in_p,
adc_clk_in_n,
adc_or_in_p,
adc_or_in_n,
adc_data_in_p,
adc_data_in_n,
ref_clk_out_p,
ref_clk_out_n,
iic_scl,
iic_sda,
iic_mux_scl,
iic_mux_sda,
otg_vbusoc);
inout [14:0] DDR_addr;
inout [ 2:0] DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [ 3:0] DDR_dm;
inout [31:0] DDR_dq;
inout [ 3:0] DDR_dqs_n;
inout [ 3:0] DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0] FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout [31:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [15:0] hdmi_data;
output spdif;
output i2s_mclk;
output i2s_bclk;
output i2s_lrclk;
output i2s_sdata_out;
input i2s_sdata_in;
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output dac_frame_out_p;
output dac_frame_out_n;
output [15:0] dac_data_out_p;
output [15:0] dac_data_out_n;
input adc_clk_in_p;
input adc_clk_in_n;
input adc_or_in_p;
input adc_or_in_n;
input [13:0] adc_data_in_p;
input [13:0] adc_data_in_n;
output ref_clk_out_p;
output ref_clk_out_n;
inout iic_scl;
inout iic_sda;
inout [ 1:0] iic_mux_scl;
inout [ 1:0] iic_mux_sda;
input otg_vbusoc;
// internal signals
wire [31:0] gpio_i;
wire [31:0] gpio_o;
wire [31:0] gpio_t;
wire ref_clk;
wire oddr_ref_clk;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
// instantiations
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
i_oddr_ref_clk (
.S (1'b0),
.CE (1'b1),
.R (1'b0),
.C (ref_clk),
.D1 (1'b1),
.D2 (1'b0),
.Q (oddr_ref_clk));
OBUFDS i_obufds_ref_clk (
.I (oddr_ref_clk),
.O (ref_clk_out_p),
.OB (ref_clk_out_n));
genvar n;
generate
for (n = 0; n <= 31; n = n + 1) begin: g_iobuf_gpio_bd
IOBUF i_iobuf_gpio_bd (
.I (gpio_o[n]),
.O (gpio_i[n]),
.T (gpio_t[n]),
.IO (gpio_bd[n]));
end
endgenerate
IOBUF i_iic_mux_scl_0 (.I(iic_mux_scl_o_s[0]), .O(iic_mux_scl_i_s[0]), .T(iic_mux_scl_t_s), .IO(iic_mux_scl[0]));
IOBUF i_iic_mux_scl_1 (.I(iic_mux_scl_o_s[1]), .O(iic_mux_scl_i_s[1]), .T(iic_mux_scl_t_s), .IO(iic_mux_scl[1]));
IOBUF i_iic_mux_sda_0 (.I(iic_mux_sda_o_s[0]), .O(iic_mux_sda_i_s[0]), .T(iic_mux_sda_t_s), .IO(iic_mux_sda[0]));
IOBUF i_iic_mux_sda_1 (.I(iic_mux_sda_o_s[1]), .O(iic_mux_sda_i_s[1]), .T(iic_mux_sda_t_s), .IO(iic_mux_sda[1]));
system_wrapper i_system_wrapper (
.DDR_addr (DDR_addr),
.DDR_ba (DDR_ba),
.DDR_cas_n (DDR_cas_n),
.DDR_ck_n (DDR_ck_n),
.DDR_ck_p (DDR_ck_p),
.DDR_cke (DDR_cke),
.DDR_cs_n (DDR_cs_n),
.DDR_dm (DDR_dm),
.DDR_dq (DDR_dq),
.DDR_dqs_n (DDR_dqs_n),
.DDR_dqs_p (DDR_dqs_p),
.DDR_odt (DDR_odt),
.DDR_ras_n (DDR_ras_n),
.DDR_reset_n (DDR_reset_n),
.DDR_we_n (DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.GPIO_I (gpio_i),
.GPIO_O (gpio_o),
.GPIO_T (gpio_t),
.adc_clk_in_n (adc_clk_in_n),
.adc_clk_in_p (adc_clk_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_or_in_n (adc_or_in_n),
.adc_or_in_p (adc_or_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_data_out_n (dac_data_out_n),
.dac_data_out_p (dac_data_out_p),
.dac_frame_out_n (dac_frame_out_n),
.dac_frame_out_p (dac_frame_out_p),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_I (iic_mux_scl_i_s),
.iic_mux_scl_O (iic_mux_scl_o_s),
.iic_mux_scl_T (iic_mux_scl_t_s),
.iic_mux_sda_I (iic_mux_sda_i_s),
.iic_mux_sda_O (iic_mux_sda_o_s),
.iic_mux_sda_T (iic_mux_sda_t_s),
.ref_clk (ref_clk),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************