ad738x_fmc: Initial commit
Istvan Csomortani
parent
5c252783e7
commit
f933a4cbcd
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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 spi
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# create a SPI Engine architecture
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create_bd_cell -type hier spi
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current_bd_instance /spi
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create_bd_pin -dir I -type clk clk
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create_bd_pin -dir I -type rst resetn
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create_bd_pin -dir O irq
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create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE
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ad_ip_instance spi_engine_execution execution
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ad_ip_instance axi_spi_engine axi
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ad_ip_instance spi_engine_offload offload
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ad_ip_instance spi_engine_interconnect interconnect
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ad_ip_instance util_pulse_gen trigger_gen
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ad_ip_parameter offload CONFIG.DATA_WIDTH 16
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ad_ip_parameter axi CONFIG.DATA_WIDTH 16
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ad_ip_parameter interconnect CONFIG.DATA_WIDTH 16
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ad_ip_parameter execution CONFIG.DATA_WIDTH 16
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## to setup the sample rate of the system change the PULSE_PERIOD value
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## the acutal sample rate will be PULSE_PERIOD * (1/sys_cpu_clk)
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ad_ip_parameter trigger_gen CONFIG.PULSE_PERIOD 100
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ad_ip_parameter trigger_gen CONFIG.PULSE_WIDTH 1
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ad_ip_parameter execution CONFIG.NUM_OF_CS 1
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ad_ip_parameter axi CONFIG.NUM_OFFLOAD 1
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ad_connect axi/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl
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ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl
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ad_connect axi/spi_engine_ctrl interconnect/s1_ctrl
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ad_connect interconnect/m_ctrl execution/ctrl
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ad_connect offload/offload_sdi M_AXIS_SAMPLE
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ad_connect execution/spi m_spi
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ad_connect clk offload/spi_clk
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ad_connect clk offload/ctrl_clk
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ad_connect clk execution/clk
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ad_connect clk axi/s_axi_aclk
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ad_connect clk axi/spi_clk
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ad_connect clk interconnect/clk
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ad_connect clk trigger_gen/clk
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ad_connect axi/spi_resetn offload/spi_resetn
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ad_connect axi/spi_resetn execution/resetn
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ad_connect axi/spi_resetn interconnect/resetn
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ad_connect axi/spi_resetn trigger_gen/rstn
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ad_connect trigger_gen/pulse_period_en GND
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ad_connect trigger_gen/pulse_period GND
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ad_connect trigger_gen/pulse offload/trigger
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ad_connect resetn axi/s_axi_aresetn
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ad_connect irq axi/irq
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current_bd_instance /
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ad_ip_instance axi_dmac axi_ad738x_dma
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ad_ip_parameter axi_ad738x_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_ad738x_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_ad738x_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_ad738x_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_ad738x_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_ad738x_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_ad738x_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad738x_dma CONFIG.DMA_DATA_WIDTH_SRC 16
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ad_ip_parameter axi_ad738x_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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ad_connect sys_cpu_clk spi/clk
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ad_connect sys_cpu_resetn spi/resetn
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ad_connect sys_cpu_resetn axi_ad738x_dma/m_dest_axi_aresetn
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ad_connect spi/m_spi spi
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ad_connect axi_ad738x_dma/s_axis spi/M_AXIS_SAMPLE
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ad_cpu_interconnect 0x44a00000 spi/axi
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ad_cpu_interconnect 0x44a30000 axi_ad738x_dma
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ad_connect sys_cpu_clk axi_ad738x_dma/s_axis_aclk
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ad_cpu_interrupt "ps-13" "mb-13" axi_ad738x_dma/irq
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ad_cpu_interrupt "ps-12" "mb-12" spi/irq
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ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect sys_cpu_clk axi_ad738x_dma/m_dest_axi
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@ -0,0 +1,90 @@
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####################################################################################
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####################################################################################
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## Copyright 2011(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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####################################################################################
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M_DEPS += system_top.v
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M_DEPS += system_project.tcl
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M_DEPS += system_constr.xdc
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M_DEPS += system_bd.tcl
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M_DEPS += ../common/ad738x_bd.tcl
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M_DEPS += ../../scripts/adi_project.tcl
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M_DEPS += ../../scripts/adi_env.tcl
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M_DEPS += ../../scripts/adi_board.tcl
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M_DEPS += ../../common/zed/zed_system_constr.xdc
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M_DEPS += ../../common/zed/zed_system_bd.tcl
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M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
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M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
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M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
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M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
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M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
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M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
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M_DEPS += ../../../library/spi_engine/axi_spi_engine/axi_spi_engine.xpr
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M_DEPS += ../../../library/spi_engine/spi_engine_execution/spi_engine_execution.xpr
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M_DEPS += ../../../library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr
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M_DEPS += ../../../library/spi_engine/spi_engine_offload/spi_engine_offload.xpr
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M_DEPS += ../../../library/util_i2c_mixer/util_i2c_mixer.xpr
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M_DEPS += ../../../library/util_pulse_gen/util_pulse_gen.xpr
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M_VIVADO := vivado -mode batch -source
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M_FLIST := *.cache
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M_FLIST += *.data
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M_FLIST += *.xpr
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M_FLIST += *.log
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M_FLIST += *.jou
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M_FLIST += xgui
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M_FLIST += *.runs
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M_FLIST += *.srcs
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M_FLIST += *.sdk
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M_FLIST += *.hw
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M_FLIST += *.sim
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M_FLIST += .Xil
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M_FLIST += *.ip_user_files
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.PHONY: all lib clean clean-all
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all: lib ad738x_fmc_zed.sdk/system_top.hdf
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clean:
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rm -rf $(M_FLIST)
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clean-all:clean
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make -C ../../../library/axi_clkgen clean
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make -C ../../../library/axi_dmac clean
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make -C ../../../library/axi_hdmi_tx clean
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make -C ../../../library/axi_i2s_adi clean
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make -C ../../../library/axi_spdif_tx clean
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make -C ../../../library/spi_engine/axi_spi_engine clean
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make -C ../../../library/spi_engine/spi_engine_execution clean
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make -C ../../../library/spi_engine/spi_engine_interconnect clean
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make -C ../../../library/spi_engine/spi_engine_offload clean
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make -C ../../../library/util_i2c_mixer clean
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make -C ../../../library/util_pulse_gen clean
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ad738x_fmc_zed.sdk/system_top.hdf: $(M_DEPS)
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-rm -rf $(M_FLIST)
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$(M_VIVADO) system_project.tcl >> ad738x_fmc_zed_vivado.log 2>&1
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lib:
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make -C ../../../library/axi_clkgen
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make -C ../../../library/axi_dmac
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make -C ../../../library/axi_hdmi_tx
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make -C ../../../library/axi_i2s_adi
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make -C ../../../library/axi_spdif_tx
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make -C ../../../library/spi_engine/axi_spi_engine
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make -C ../../../library/spi_engine/spi_engine_execution
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make -C ../../../library/spi_engine/spi_engine_interconnect
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make -C ../../../library/spi_engine/spi_engine_offload
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make -C ../../../library/util_i2c_mixer
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make -C ../../../library/util_pulse_gen
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####################################################################################
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####################################################################################
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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
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source ../common/ad738x_bd.tcl
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# SPI interface
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set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS25} [get_ports spi_sclk] ; ## FMC_LPC_LA15_N
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set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports spi_sdia] ; ## FMC_LPC_LA01_CC_P
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set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports spi_sdib] ; ## FMC_LPC_LA01_CC_N
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set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports spi_sdo] ; ## FMC_LPC_LA02_P
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set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports spi_cs] ; ## FMC_LPC_LA00_CC_N
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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adi_project_xilinx ad738x_fmc_zed
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adi_project_files ad738x_fmc_zed [list \
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"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
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"system_top.v" \
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"system_constr.xdc" \
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"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
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adi_project_run ad738x_fmc_zed
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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inout [14:0] ddr_addr,
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inout [ 2:0] ddr_ba,
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inout ddr_cas_n,
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inout ddr_ck_n,
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inout ddr_ck_p,
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inout ddr_cke,
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inout ddr_cs_n,
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inout [ 3:0] ddr_dm,
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inout [31:0] ddr_dq,
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inout [ 3:0] ddr_dqs_n,
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inout [ 3:0] ddr_dqs_p,
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inout ddr_odt,
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inout ddr_ras_n,
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inout ddr_reset_n,
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inout ddr_we_n,
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inout fixed_io_ddr_vrn,
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inout fixed_io_ddr_vrp,
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inout [53:0] fixed_io_mio,
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inout fixed_io_ps_clk,
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inout fixed_io_ps_porb,
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inout fixed_io_ps_srstb,
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inout [31:0] gpio_bd,
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output hdmi_out_clk,
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output hdmi_vsync,
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output hdmi_hsync,
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output hdmi_data_e,
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output [15:0] hdmi_data,
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output spdif,
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output i2s_mclk,
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output i2s_bclk,
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output i2s_lrclk,
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output i2s_sdata_out,
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input i2s_sdata_in,
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inout iic_scl,
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inout iic_sda,
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inout [ 1:0] iic_mux_scl,
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inout [ 1:0] iic_mux_sda,
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input otg_vbusoc,
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input spi_sdia,
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input spi_sdib,
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output spi_sdo,
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output spi_sclk,
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output spi_cs);
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// internal signals
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire [ 1:0] iic_mux_scl_i_s;
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wire [ 1:0] iic_mux_scl_o_s;
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wire iic_mux_scl_t_s;
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wire [ 1:0] iic_mux_sda_i_s;
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wire [ 1:0] iic_mux_sda_o_s;
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wire iic_mux_sda_t_s;
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// instantiations
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assign gpio_i[63:32] = 32'b0;
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ad_iobuf #(
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.DATA_WIDTH(32)
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) i_iobuf (
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.dio_t(gpio_t[31:0]),
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.dio_i(gpio_o[31:0]),
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.dio_o(gpio_i[31:0]),
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.dio_p(gpio_bd));
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ad_iobuf #(
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.DATA_WIDTH(2)
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) i_iic_mux_scl (
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.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
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.dio_i(iic_mux_scl_o_s),
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.dio_o(iic_mux_scl_i_s),
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.dio_p(iic_mux_scl));
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ad_iobuf #(
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.DATA_WIDTH(2)
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) i_iic_mux_sda (
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.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
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.dio_i(iic_mux_sda_o_s),
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.dio_o(iic_mux_sda_i_s),
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.dio_p(iic_mux_sda));
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system_wrapper i_system_wrapper (
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dqs_p (ddr_dqs_p),
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.ddr_odt (ddr_odt),
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.ddr_ras_n (ddr_ras_n),
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.ddr_reset_n (ddr_reset_n),
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.ddr_we_n (ddr_we_n),
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
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.fixed_io_mio (fixed_io_mio),
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.fixed_io_ps_clk (fixed_io_ps_clk),
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.fixed_io_ps_porb (fixed_io_ps_porb),
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.fixed_io_ps_srstb (fixed_io_ps_srstb),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.hdmi_data (hdmi_data),
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.hdmi_data_e (hdmi_data_e),
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.hdmi_hsync (hdmi_hsync),
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.hdmi_out_clk (hdmi_out_clk),
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.hdmi_vsync (hdmi_vsync),
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.i2s_bclk (i2s_bclk),
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.i2s_lrclk (i2s_lrclk),
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.i2s_mclk (i2s_mclk),
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.i2s_sdata_in (i2s_sdata_in),
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.i2s_sdata_out (i2s_sdata_out),
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.iic_fmc_scl_io (iic_scl),
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.iic_fmc_sda_io (iic_sda),
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.iic_mux_scl_i (iic_mux_scl_i_s),
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.iic_mux_scl_o (iic_mux_scl_o_s),
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.iic_mux_scl_t (iic_mux_scl_t_s),
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.iic_mux_sda_i (iic_mux_sda_i_s),
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.iic_mux_sda_o (iic_mux_sda_o_s),
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.iic_mux_sda_t (iic_mux_sda_t_s),
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.ps_intr_00 (1'b0),
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.ps_intr_01 (1'b0),
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.ps_intr_02 (1'b0),
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.ps_intr_03 (1'b0),
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.ps_intr_04 (1'b0),
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.ps_intr_05 (1'b0),
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.ps_intr_06 (1'b0),
|
||||
.ps_intr_07 (1'b0),
|
||||
.ps_intr_08 (1'b0),
|
||||
.ps_intr_09 (1'b0),
|
||||
.ps_intr_10 (1'b0),
|
||||
.spi_sdo (spi_sdo),
|
||||
.spi_sdo_t (),
|
||||
.spi_sdi (spi_sdia),
|
||||
.spi_sdi_1 (spi_sdib),
|
||||
.spi_sdi_2 (1'b0),
|
||||
.spi_sdi_3 (1'b0),
|
||||
.spi_cs (spi_cs),
|
||||
.spi_sclk (spi_sclk),
|
||||
.otg_vbusoc (otg_vbusoc),
|
||||
.spdif (spdif));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
Loading…
Reference in New Issue