jesd204: Add names for generate for-blocks

Be more standard compliant and assign names to generate for-blocks. This is
required for Altera/Intel support.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v

@@ -70,7 +70,7 @@ sync_bits i_sync_ilas_ready (
 
 generate
 genvar i;
-for (i = 0; i < 32; i = i + 1) begin: ilas_mem
+for (i = 0; i < 32; i = i + 1) begin: gen_ilas_mem
   assign up_rdata[i] = mem[i][~up_raddr];
 
   always @(posedge core_clk) begin

library/jesd204/axi_jesd204_rx/jesd204_up_rx.v

@@ -143,7 +143,7 @@ always @(posedge up_clk) begin
 end
 
 genvar i;
-generate for (i = 0; i < NUM_LANES; i = i + 1) begin
+generate for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
     jesd204_up_rx_lane i_up_rx_lane (
       .up_clk(up_clk),
       .up_reset_synchronizer(up_reset_synchronizer),

library/jesd204/axi_jesd204_tx/jesd204_up_tx.v

@@ -291,7 +291,7 @@ end
 
 genvar j;
 generate
-for (j = 0; j < NUM_LANES; j = j + 1) begin
+for (j = 0; j < NUM_LANES; j = j + 1) begin: gen_lane
   always @(posedge core_clk) begin
     if (core_ilas_config_rd == 1'b1) begin
       core_ilas_config_data[j*32+31:j*32] <= up_cfg_ilas_data[core_ilas_config_addr+4*j];

library/jesd204/jesd204_common/scrambler.v

@@ -63,7 +63,7 @@ wire [WIDTH-1+15:0] full_state;
 
 generate
 genvar i;
-for (i = 0; i < WIDTH / 8; i = i + 1) begin
+for (i = 0; i < WIDTH / 8; i = i + 1) begin: gen_swizzle
   assign swizzle_in[WIDTH-1-i*8:WIDTH-i*8-8] = data_in[i*8+7:i*8];
   assign data_out[WIDTH-1-i*8:WIDTH-i*8-8] = swizzle_out[i*8+7:i*8];
 end

library/jesd204/jesd204_rx/lane_latency_monitor.v

@@ -71,7 +71,7 @@ end
 generate
 genvar i;
 
-for (i = 0; i < NUM_LANES; i = i + 1) begin
+for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
   always @(posedge clk) begin
     if (reset == 1'b1) begin
       lane_latency_mem[i] <= 'h00;

library/jesd204/jesd204_rx/rx.v

@@ -267,7 +267,7 @@ jesd204_eof_generator  #(
 
 genvar i;
 generate
-for (i = 0; i < NUM_LANES; i = i + 1) begin
+for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
 
   localparam D_START = i * DATA_PATH_WIDTH*8;
   localparam D_STOP = D_START + DATA_PATH_WIDTH*8-1;

library/jesd204/jesd204_rx/rx_lane.v

@@ -109,7 +109,7 @@ assign status_frame_align = frame_align;
 genvar i;
 generate
 
-for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin
+for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_char
   assign char[i] = phy_data[i*8+7:i*8];
   assign char_is_valid[i] = ~(phy_notintable[i] | phy_disperr[i]);
 

library/jesd204/jesd204_tx/ilas_cfg_static.v

@@ -80,7 +80,7 @@ assign ilas_mem[3][31:24] = ilas_mem[0][23:16] + ilas_mem[0][31:24] +
 generate
 genvar i;
 
-for (i = 0; i < NUM_LANES; i = i + 1) begin
+for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
 	always @(posedge clk) begin
 		if (ilas_config_rd == 1'b1) begin
 			ilas_config_data[i*32+31:i*32] <= ilas_mem[ilas_config_addr];

library/jesd204/jesd204_tx/tx.v

@@ -188,7 +188,7 @@ jesd204_eof_generator #(
 
 generate
 genvar i;
-for (i = 0; i < NUM_LANES; i = i + 1) begin
+for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
 
   localparam D_START = i * DATA_PATH_WIDTH*8;
   localparam D_STOP = D_START + DATA_PATH_WIDTH*8-1;

library/jesd204/jesd204_tx/tx_lane.v

@@ -82,7 +82,7 @@ jesd204_scrambler #(
 generate
 genvar i;
 
-for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin
+for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_char
   assign scrambled_char[i] = scrambled_data[i*8+7:i*8];
 
   always @(*) begin

library/jesd204/jesd204_tx_static_config/ilas_cfg_static.v

@@ -105,7 +105,7 @@ assign ilas_mem[3][31:24] = ilas_mem[0][23:16] + ilas_mem[0][31:24] +
 generate
 genvar i;
 
-for (i = 0; i < NUM_LANES; i = i + 1) begin
+for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
   always @(posedge clk) begin
     if (ilas_config_rd == 1'b1) begin
       ilas_config_data[i*32+31:i*32] <= ilas_mem[ilas_config_addr];