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fmcadc2: Parameterize JESD204 configuration values 

Add the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
main
Dan Hotoleanu 2021-12-07 16:33:27 +00:00 committed by hotoleanudan
parent 13a282d9c4
commit fb17147eb4
5 changed files with 115 additions and 49 deletions
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28
projects/fmcadc2/common/fmcadc2_bd.tcl
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@ -1,14 +1,21 @@
#
# Parameter description:
# RX_JESD_M : Number of converters per link
# RX_JESD_L : Number of lanes per link
# RX_JESD_S : Number of samples per frame
# RX_JESD_NP : Number of bits per sample
#
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
# JESD204B interface configuration parameters # JESD204B interface configuration parameters
set RX_NUM_OF_LANES 8 set RX_NUM_OF_LANES $ad_project_params(RX_JESD_L)
set RX_NUM_OF_CONVERTERS 1 set RX_NUM_OF_CONVERTERS $ad_project_params(RX_JESD_M)
set RX_SAMPLES_PER_FRAME 4 set RX_SAMPLES_PER_FRAME $ad_project_params(RX_JESD_S)
set RX_SAMPLE_WIDTH 16 set RX_SAMPLE_WIDTH $ad_project_params(RX_JESD_NP)
set adc_fifo_name axi_ad9625_fifo set adc_fifo_name axi_ad9625_fifo
set adc_data_width 256 set adc_data_width [expr 32*$RX_NUM_OF_LANES]
set adc_dma_data_width 64 set adc_dma_data_width 64
# adc peripherals # adc peripherals
@ -18,10 +25,10 @@ adi_tpl_jesd204_rx_create axi_ad9625_core $RX_NUM_OF_LANES \
$RX_SAMPLES_PER_FRAME \ $RX_SAMPLES_PER_FRAME \
$RX_SAMPLE_WIDTH \ $RX_SAMPLE_WIDTH \
adi_axi_jesd204_rx_create axi_ad9625_jesd 8 adi_axi_jesd204_rx_create axi_ad9625_jesd $RX_NUM_OF_LANES
ad_ip_instance axi_adxcvr axi_ad9625_xcvr ad_ip_instance axi_adxcvr axi_ad9625_xcvr
ad_ip_parameter axi_ad9625_xcvr CONFIG.NUM_OF_LANES 8 ad_ip_parameter axi_ad9625_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
ad_ip_parameter axi_ad9625_xcvr CONFIG.QPLL_ENABLE 0 ad_ip_parameter axi_ad9625_xcvr CONFIG.QPLL_ENABLE 0
ad_ip_parameter axi_ad9625_xcvr CONFIG.TX_OR_RX_N 0 ad_ip_parameter axi_ad9625_xcvr CONFIG.TX_OR_RX_N 0
ad_ip_parameter axi_ad9625_xcvr CONFIG.LPM_OR_DFE_N 1 ad_ip_parameter axi_ad9625_xcvr CONFIG.LPM_OR_DFE_N 1
@ -47,7 +54,7 @@ ad_ip_instance util_adxcvr util_fmcadc2_xcvr
ad_ip_parameter util_fmcadc2_xcvr CONFIG.QPLL_FBDIV 0x80 ;# N = 40 ad_ip_parameter util_fmcadc2_xcvr CONFIG.QPLL_FBDIV 0x80 ;# N = 40
ad_ip_parameter util_fmcadc2_xcvr CONFIG.CPLL_FBDIV 1 ad_ip_parameter util_fmcadc2_xcvr CONFIG.CPLL_FBDIV 1
ad_ip_parameter util_fmcadc2_xcvr CONFIG.TX_NUM_OF_LANES 0 ad_ip_parameter util_fmcadc2_xcvr CONFIG.TX_NUM_OF_LANES 0
ad_ip_parameter util_fmcadc2_xcvr CONFIG.RX_NUM_OF_LANES 8 ad_ip_parameter util_fmcadc2_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES
ad_ip_parameter util_fmcadc2_xcvr CONFIG.RX_OUT_DIV 1 ad_ip_parameter util_fmcadc2_xcvr CONFIG.RX_OUT_DIV 1
ad_ip_parameter util_fmcadc2_xcvr CONFIG.RX_CLK25_DIV 25 ad_ip_parameter util_fmcadc2_xcvr CONFIG.RX_CLK25_DIV 25
ad_ip_parameter util_fmcadc2_xcvr CONFIG.RX_DFE_LPM_CFG 0x0904 ad_ip_parameter util_fmcadc2_xcvr CONFIG.RX_DFE_LPM_CFG 0x0904
@ -108,3 +115,8 @@ ad_mem_hp2_interconnect $sys_cpu_clk axi_ad9625_dma/m_dest_axi
ad_cpu_interrupt ps-12 mb-13 axi_ad9625_jesd/irq ad_cpu_interrupt ps-12 mb-13 axi_ad9625_jesd/irq
ad_cpu_interrupt ps-13 mb-12 axi_ad9625_dma/irq ad_cpu_interrupt ps-13 mb-12 axi_ad9625_dma/irq
# Create dummy outputs for unused Rx lanes
for {set i $RX_NUM_OF_LANES} {$i < 8} {incr i} {
create_bd_port -dir I rx_data_${i}_n
create_bd_port -dir I rx_data_${i}_p
}

22
projects/fmcadc2/vc707/system_project.tcl
View File

@ -5,7 +5,27 @@ source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project fmcadc2_vc707 # get_env_param retrieves parameter value from the environment if exists,
# other case use the default value
#
# Use over-writable parameters from the environment.
#
# e.g.
# make RX_JESD_L=8
# Parameter description:
# RX_JESD_M : Number of converters per link
# RX_JESD_L : Number of lanes per link
# RX_JESD_S : Number of samples per frame
# RX_JESD_NP : Number of bits per sample
adi_project fmcadc2_vc707 0 [list \
RX_JESD_M [get_env_param RX_JESD_M 1 ] \
RX_JESD_L [get_env_param RX_JESD_L 8 ] \
RX_JESD_S [get_env_param RX_JESD_S 4 ] \
RX_JESD_NP [get_env_param RX_JESD_NP 16] \
]
adi_project_files fmcadc2_vc707 [list \ adi_project_files fmcadc2_vc707 [list \
"../common/fmcadc2_spi.v" \ "../common/fmcadc2_spi.v" \
"system_top.v" \ "system_top.v" \

45
projects/fmcadc2/vc707/system_top.v
View File

@ -35,7 +35,9 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module system_top ( module system_top #(
parameter RX_JESD_L = 8
) (
input sys_rst, input sys_rst,
input sys_clk_p, input sys_clk_p,
@ -93,8 +95,8 @@ module system_top (
output rx_sysref_n, output rx_sysref_n,
output rx_sync_p, output rx_sync_p,
output rx_sync_n, output rx_sync_n,
input [ 7:0] rx_data_p, input [RX_JESD_L-1:0] rx_data_p,
input [ 7:0] rx_data_n, input [RX_JESD_L-1:0] rx_data_n,
inout adc_irq, inout adc_irq,
inout adc_fd, inout adc_fd,
@ -120,6 +122,8 @@ module system_top (
wire rx_sync; wire rx_sync;
wire rx_sysref; wire rx_sysref;
wire rx_clk; wire rx_clk;
wire [ 7:0] rx_data_p_loc;
wire [ 7:0] rx_data_n_loc;
// default logic // default logic
@ -217,22 +221,22 @@ module system_top (
.mgt_clk_clk_p (mgt_clk_p), .mgt_clk_clk_p (mgt_clk_p),
.phy_rstn (phy_rstn), .phy_rstn (phy_rstn),
.phy_sd (1'b1), .phy_sd (1'b1),
.rx_data_0_n (rx_data_n[0]), .rx_data_0_n (rx_data_n_loc[0]),
.rx_data_0_p (rx_data_p[0]), .rx_data_0_p (rx_data_p_loc[0]),
.rx_data_1_n (rx_data_n[1]), .rx_data_1_n (rx_data_n_loc[1]),
.rx_data_1_p (rx_data_p[1]), .rx_data_1_p (rx_data_p_loc[1]),
.rx_data_2_n (rx_data_n[2]), .rx_data_2_n (rx_data_n_loc[2]),
.rx_data_2_p (rx_data_p[2]), .rx_data_2_p (rx_data_p_loc[2]),
.rx_data_3_n (rx_data_n[3]), .rx_data_3_n (rx_data_n_loc[3]),
.rx_data_3_p (rx_data_p[3]), .rx_data_3_p (rx_data_p_loc[3]),
.rx_data_4_n (rx_data_n[4]), .rx_data_4_n (rx_data_n_loc[4]),
.rx_data_4_p (rx_data_p[4]), .rx_data_4_p (rx_data_p_loc[4]),
.rx_data_5_n (rx_data_n[5]), .rx_data_5_n (rx_data_n_loc[5]),
.rx_data_5_p (rx_data_p[5]), .rx_data_5_p (rx_data_p_loc[5]),
.rx_data_6_n (rx_data_n[6]), .rx_data_6_n (rx_data_n_loc[6]),
.rx_data_6_p (rx_data_p[6]), .rx_data_6_p (rx_data_p_loc[6]),
.rx_data_7_n (rx_data_n[7]), .rx_data_7_n (rx_data_n_loc[7]),
.rx_data_7_p (rx_data_p[7]), .rx_data_7_p (rx_data_p_loc[7]),
.rx_ref_clk_0 (rx_ref_clk), .rx_ref_clk_0 (rx_ref_clk),
.rx_sync_0 (rx_sync), .rx_sync_0 (rx_sync),
.rx_sysref_0 (rx_sysref), .rx_sysref_0 (rx_sysref),
@ -254,6 +258,9 @@ module system_top (
.uart_sin (uart_sin), .uart_sin (uart_sin),
.uart_sout (uart_sout)); .uart_sout (uart_sout));
assign rx_data_p_loc[RX_JESD_L-1:0] = rx_data_p[RX_JESD_L-1:0];
assign rx_data_n_loc[RX_JESD_L-1:0] = rx_data_n[RX_JESD_L-1:0];
endmodule endmodule
// *************************************************************************** // ***************************************************************************

24
projects/fmcadc2/zc706/system_project.tcl
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@ -3,7 +3,27 @@ source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project fmcadc2_zc706 # get_env_param retrieves parameter value from the environment if exists,
# other case use the default value
#
# Use over-writable parameters from the environment.
#
# e.g.
# make RX_JESD_L=8
# Parameter description:
# RX_JESD_M : Number of converters per link
# RX_JESD_L : Number of lanes per link
# RX_JESD_S : Number of samples per frame
# RX_JESD_NP : Number of bits per sample
adi_project fmcadc2_zc706 0 [list \
RX_JESD_M [get_env_param RX_JESD_M 1 ] \
RX_JESD_L [get_env_param RX_JESD_L 8 ] \
RX_JESD_S [get_env_param RX_JESD_S 4 ] \
RX_JESD_NP [get_env_param RX_JESD_NP 16] \
]
adi_project_files fmcadc2_zc706 [list \ adi_project_files fmcadc2_zc706 [list \
"../common/fmcadc2_spi.v" \ "../common/fmcadc2_spi.v" \
"system_top.v" \ "system_top.v" \
@ -13,4 +33,4 @@ adi_project_files fmcadc2_zc706 [list \
"$ad_hdl_dir/projects/common/zc706/zc706_plddr3_constr.xdc" \ "$ad_hdl_dir/projects/common/zc706/zc706_plddr3_constr.xdc" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
adi_project_run fmcadc2_zc706 adi_project_run fmcadc2_zc706

45
projects/fmcadc2/zc706/system_top.v
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@ -35,7 +35,9 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module system_top ( module system_top #(
parameter RX_JESD_L = 8
) (
inout [14:0] ddr_addr, inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba, inout [ 2:0] ddr_ba,
@ -99,8 +101,8 @@ module system_top (
output rx_sysref_n, output rx_sysref_n,
output rx_sync_p, output rx_sync_p,
output rx_sync_n, output rx_sync_n,
input [ 7:0] rx_data_p, input [RX_JESD_L-1:0] rx_data_p,
input [ 7:0] rx_data_n, input [RX_JESD_L-1:0] rx_data_n,
inout adc_irq, inout adc_irq,
inout adc_fd, inout adc_fd,
@ -131,6 +133,8 @@ module system_top (
wire rx_sync; wire rx_sync;
wire rx_clk; wire rx_clk;
wire rx_sysref; wire rx_sysref;
wire [7:0] rx_data_p_loc;
wire [7:0] rx_data_n_loc;
// instantiations // instantiations
@ -235,22 +239,22 @@ module system_top (
.hdmi_vsync (hdmi_vsync), .hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl), .iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda), .iic_main_sda_io (iic_sda),
.rx_data_0_n (rx_data_n[0]), .rx_data_0_n (rx_data_n_loc[0]),
.rx_data_0_p (rx_data_p[0]), .rx_data_0_p (rx_data_p_loc[0]),
.rx_data_1_n (rx_data_n[1]), .rx_data_1_n (rx_data_n_loc[1]),
.rx_data_1_p (rx_data_p[1]), .rx_data_1_p (rx_data_p_loc[1]),
.rx_data_2_n (rx_data_n[2]), .rx_data_2_n (rx_data_n_loc[2]),
.rx_data_2_p (rx_data_p[2]), .rx_data_2_p (rx_data_p_loc[2]),
.rx_data_3_n (rx_data_n[3]), .rx_data_3_n (rx_data_n_loc[3]),
.rx_data_3_p (rx_data_p[3]), .rx_data_3_p (rx_data_p_loc[3]),
.rx_data_4_n (rx_data_n[4]), .rx_data_4_n (rx_data_n_loc[4]),
.rx_data_4_p (rx_data_p[4]), .rx_data_4_p (rx_data_p_loc[4]),
.rx_data_5_n (rx_data_n[5]), .rx_data_5_n (rx_data_n_loc[5]),
.rx_data_5_p (rx_data_p[5]), .rx_data_5_p (rx_data_p_loc[5]),
.rx_data_6_n (rx_data_n[6]), .rx_data_6_n (rx_data_n_loc[6]),
.rx_data_6_p (rx_data_p[6]), .rx_data_6_p (rx_data_p_loc[6]),
.rx_data_7_n (rx_data_n[7]), .rx_data_7_n (rx_data_n_loc[7]),
.rx_data_7_p (rx_data_p[7]), .rx_data_7_p (rx_data_p_loc[7]),
.rx_ref_clk_0 (rx_ref_clk), .rx_ref_clk_0 (rx_ref_clk),
.rx_sync_0 (rx_sync), .rx_sync_0 (rx_sync),
.rx_sysref_0 (rx_sysref), .rx_sysref_0 (rx_sysref),
@ -278,6 +282,9 @@ module system_top (
.sys_clk_clk_p (sys_clk_p), .sys_clk_clk_p (sys_clk_p),
.sys_rst (sys_rst)); .sys_rst (sys_rst));
assign rx_data_p_loc[RX_JESD_L-1:0] = rx_data_p[RX_JESD_L-1:0];
assign rx_data_n_loc[RX_JESD_L-1:0] = rx_data_n[RX_JESD_L-1:0];
endmodule endmodule
// *************************************************************************** // ***************************************************************************