diff --git a/projects/adrv9371x/zc706/system_bd.tcl b/projects/adrv9371x/zc706/system_bd.tcl index 434317333..f754d0409 100644 --- a/projects/adrv9371x/zc706/system_bd.tcl +++ b/projects/adrv9371x/zc706/system_bd.tcl @@ -1,23 +1,10 @@ +set dac_fifo_name axi_ad9371_dacfifo +set dac_fifo_address_width 10 +set dac_data_width 128 +set dac_dma_data_width 128 + source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_dacfifo_bd.tcl - -p_plddr3_dacfifo [current_bd_instance .] axi_ad9371_dacfifo 128 128 - -create_bd_port -dir I -type rst sys_rst -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 -create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk - -set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst] - -ad_connect sys_rst axi_ad9371_dacfifo/sys_rst -ad_connect sys_clk axi_ad9371_dacfifo/sys_clk -ad_connect ddr3 axi_ad9371_dacfifo/ddr3 - -create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \ - [get_bd_addr_spaces axi_ad9371_dacfifo/axi_dacfifo/axi] \ - [get_bd_addr_segs axi_ad9371_dacfifo/axi_ddr_cntrl/memmap/memaddr] \ - SEG_axi_ddr_cntrl_memaddr - source ../common/adrv9371x_bd.tcl diff --git a/projects/daq1/zc706/system_bd.tcl b/projects/daq1/zc706/system_bd.tcl index c0ff4740f..40db91795 100644 --- a/projects/daq1/zc706/system_bd.tcl +++ b/projects/daq1/zc706/system_bd.tcl @@ -1,23 +1,10 @@ +set adc_fifo_name axi_ad9684_fifo +set adc_fifo_address_width 18 +set adc_data_width 64 +set adc_dma_data_width 64 + source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl - -p_plddr3_adcfifo [current_bd_instance .] axi_ad9684_fifo 64 - -create_bd_port -dir I -type rst sys_rst -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 -create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk - -set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst] - -ad_connect sys_rst axi_ad9684_fifo/sys_rst -ad_connect sys_clk axi_ad9684_fifo/sys_clk -ad_connect ddr3 axi_ad9684_fifo/ddr3 - -create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \ - [get_bd_addr_spaces axi_ad9684_fifo/axi_adcfifo/axi] \ - [get_bd_addr_segs axi_ad9684_fifo/axi_ddr_cntrl/memmap/memaddr] \ - SEG_axi_ddr_cntrl_memaddr - source ../common/daq1_bd.tcl diff --git a/projects/daq2/kc705/system_bd.tcl b/projects/daq2/kc705/system_bd.tcl index e454e9122..5b193a650 100644 --- a/projects/daq2/kc705/system_bd.tcl +++ b/projects/daq2/kc705/system_bd.tcl @@ -1,11 +1,17 @@ +set adc_fifo_name axi_ad9680_fifo +set adc_fifo_address_width 16 +set adc_data_width 128 +set adc_dma_data_width 64 + +set dac_fifo_name axi_ad9144_fifo +set dac_fifo_address_width 10 +set dac_data_width 128 +set dac_dma_data_width 128 + source $ad_hdl_dir/projects/common/kc705/kc705_system_bd.tcl source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl - -p_sys_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 16 -p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10 - source ../common/daq2_bd.tcl diff --git a/projects/daq2/kcu105/system_bd.tcl b/projects/daq2/kcu105/system_bd.tcl index f0a039dce..a3952945a 100644 --- a/projects/daq2/kcu105/system_bd.tcl +++ b/projects/daq2/kcu105/system_bd.tcl @@ -1,11 +1,17 @@ +set adc_fifo_name axi_ad9680_fifo +set adc_fifo_address_width 16 +set adc_data_width 128 +set adc_dma_data_width 64 + +set dac_fifo_name axi_ad9144_fifo +set dac_fifo_address_width 10 +set dac_data_width 128 +set dac_dma_data_width 128 + source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl - -p_sys_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 16 -p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10 - source ../common/daq2_bd.tcl set_property -dict [list CONFIG.XCVR_TYPE {1}] $util_daq2_xcvr diff --git a/projects/daq2/vc707/system_bd.tcl b/projects/daq2/vc707/system_bd.tcl index 5b2dd9eca..cb11a53f8 100644 --- a/projects/daq2/vc707/system_bd.tcl +++ b/projects/daq2/vc707/system_bd.tcl @@ -1,11 +1,16 @@ +set adc_fifo_name axi_ad9680_fifo +set adc_fifo_address_width 16 +set adc_data_width 128 +set adc_dma_data_width 64 + +set dac_fifo_name axi_ad9144_fifo +set dac_fifo_address_width 10 +set dac_data_width 128 +set dac_dma_data_width 128 + source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl - -p_sys_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 16 -p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10 - source ../common/daq2_bd.tcl - diff --git a/projects/daq2/zc706/system_bd.tcl b/projects/daq2/zc706/system_bd.tcl index ac9dbdac5..1efd3a4df 100644 --- a/projects/daq2/zc706/system_bd.tcl +++ b/projects/daq2/zc706/system_bd.tcl @@ -1,25 +1,16 @@ +set adc_fifo_name axi_ad9680_fifo +set adc_fifo_address_width 16 +set adc_data_width 128 +set adc_dma_data_width 64 + +set dac_fifo_name axi_ad9144_fifo +set dac_fifo_address_width 10 +set dac_data_width 128 +set dac_dma_data_width 128 + source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl - -p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10 -p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 - -create_bd_port -dir I -type rst sys_rst -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 -create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk - -set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst] - -ad_connect sys_rst axi_ad9680_fifo/sys_rst -ad_connect sys_clk axi_ad9680_fifo/sys_clk -ad_connect ddr3 axi_ad9680_fifo/ddr3 - -create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \ - [get_bd_addr_spaces axi_ad9680_fifo/axi_adcfifo/axi] \ - [get_bd_addr_segs axi_ad9680_fifo/axi_ddr_cntrl/memmap/memaddr] \ - SEG_axi_ddr_cntrl_memaddr - source ../common/daq2_bd.tcl diff --git a/projects/daq2/zcu102/system_bd.tcl b/projects/daq2/zcu102/system_bd.tcl index 53c3cd353..f0681afa0 100644 --- a/projects/daq2/zcu102/system_bd.tcl +++ b/projects/daq2/zcu102/system_bd.tcl @@ -1,11 +1,17 @@ +set adc_fifo_name axi_ad9680_fifo +set adc_fifo_address_width 16 +set adc_data_width 128 +set adc_dma_data_width 64 + +set dac_fifo_name axi_ad9144_fifo +set dac_fifo_address_width 10 +set dac_data_width 128 +set dac_dma_data_width 128 + source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl - -p_sys_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 16 -p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10 - source ../common/daq2_bd.tcl set_property -dict [list CONFIG.XCVR_TYPE {2}] $util_daq2_xcvr diff --git a/projects/daq3/kcu105/system_bd.tcl b/projects/daq3/kcu105/system_bd.tcl index abebbf607..ea37c7e74 100644 --- a/projects/daq3/kcu105/system_bd.tcl +++ b/projects/daq3/kcu105/system_bd.tcl @@ -1,11 +1,17 @@ +set adc_fifo_name axi_ad9680_fifo +set adc_fifo_address_width 16 +set adc_data_width 128 +set adc_dma_data_width 64 + +set dac_fifo_name axi_ad9152_fifo +set dac_fifo_address_width 10 +set dac_data_width 128 +set dac_dma_data_width 128 + source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl - -p_sys_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 16 -p_sys_dacfifo [current_bd_instance .] axi_ad9152_fifo 128 10 - source ../common/daq3_bd.tcl set_property -dict [list CONFIG.XCVR_TYPE {1}] $util_daq3_xcvr diff --git a/projects/daq3/zc706/system_bd.tcl b/projects/daq3/zc706/system_bd.tcl index a41aee3d9..80326e07e 100644 --- a/projects/daq3/zc706/system_bd.tcl +++ b/projects/daq3/zc706/system_bd.tcl @@ -1,25 +1,16 @@ +set adc_fifo_name axi_ad9680_fifo +set adc_fifo_address_width 16 +set adc_data_width 128 +set adc_dma_data_width 64 + +set dac_fifo_name axi_ad9152_fifo +set dac_fifo_address_width 10 +set dac_data_width 128 +set dac_dma_data_width 128 + source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl - -p_sys_dacfifo [current_bd_instance .] axi_ad9152_fifo 128 10 -p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 - -create_bd_port -dir I -type rst sys_rst -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 -create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk - -set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst] - -ad_connect sys_rst axi_ad9680_fifo/sys_rst -ad_connect sys_clk axi_ad9680_fifo/sys_clk -ad_connect ddr3 axi_ad9680_fifo/ddr3 - -create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \ - [get_bd_addr_spaces axi_ad9680_fifo/axi_adcfifo/axi] \ - [get_bd_addr_segs axi_ad9680_fifo/axi_ddr_cntrl/memmap/memaddr] \ - SEG_axi_ddr_cntrl_memaddr - source ../common/daq3_bd.tcl diff --git a/projects/fmcadc2/vc707/system_bd.tcl b/projects/fmcadc2/vc707/system_bd.tcl index f65141c9e..9ed834ed3 100644 --- a/projects/fmcadc2/vc707/system_bd.tcl +++ b/projects/fmcadc2/vc707/system_bd.tcl @@ -1,8 +1,10 @@ +set adc_fifo_name axi_ad9625_fifo +set adc_fifo_address_width 18 +set adc_data_width 256 +set adc_dma_data_width 64 + source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl - -p_sys_adcfifo [current_bd_instance .] axi_ad9625_fifo 256 18 - source ../common/fmcadc2_bd.tcl diff --git a/projects/fmcadc2/zc706/system_bd.tcl b/projects/fmcadc2/zc706/system_bd.tcl index 3320942af..9678b203e 100644 --- a/projects/fmcadc2/zc706/system_bd.tcl +++ b/projects/fmcadc2/zc706/system_bd.tcl @@ -1,23 +1,10 @@ +set adc_fifo_name axi_ad9625_fifo +set adc_fifo_address_width 18 +set adc_data_width 256 +set adc_dma_data_width 64 + source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl - -p_plddr3_adcfifo [current_bd_instance .] axi_ad9625_fifo 256 - -create_bd_port -dir I -type rst sys_rst -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 -create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk - -set_property CONFIG.POLARITY {ACTIVE_HIGH} [get_bd_ports sys_rst] - -ad_connect sys_rst axi_ad9625_fifo/sys_rst -ad_connect sys_clk axi_ad9625_fifo/sys_clk -ad_connect ddr3 axi_ad9625_fifo/ddr3 - -create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \ - [get_bd_addr_spaces axi_ad9625_fifo/axi_adcfifo/axi] \ - [get_bd_addr_segs axi_ad9625_fifo/axi_ddr_cntrl/memmap/memaddr] \ - SEG_axi_ddr_cntrl_memaddr - source ../common/fmcadc2_bd.tcl diff --git a/projects/fmcadc4/zc706/system_bd.tcl b/projects/fmcadc4/zc706/system_bd.tcl index 1021811e5..2a66c09c5 100644 --- a/projects/fmcadc4/zc706/system_bd.tcl +++ b/projects/fmcadc4/zc706/system_bd.tcl @@ -1,22 +1,10 @@ +set adc_fifo_name axi_ad9680_fifo +set adc_fifo_address_width 18 +set adc_data_width 256 +set adc_dma_data_width 64 + source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl - -p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 256 - -create_bd_port -dir I -type rst sys_rst -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 -create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk - -set_property CONFIG.POLARITY {ACTIVE_HIGH} [get_bd_ports sys_rst] - -ad_connect sys_rst axi_ad9680_fifo/sys_rst -ad_connect sys_clk axi_ad9680_fifo/sys_clk -ad_connect ddr3 axi_ad9680_fifo/ddr3 - -create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \ - [get_bd_addr_spaces axi_ad9680_fifo/axi_adcfifo/axi] \ - [get_bd_addr_segs axi_ad9680_fifo/axi_ddr_cntrl/memmap/memaddr] \ - SEG_axi_ddr_cntrl_memaddr - source ../common/fmcadc4_bd.tcl + diff --git a/projects/fmcadc5/vc707/system_bd.tcl b/projects/fmcadc5/vc707/system_bd.tcl index 9c5a48ffe..e4718c626 100644 --- a/projects/fmcadc5/vc707/system_bd.tcl +++ b/projects/fmcadc5/vc707/system_bd.tcl @@ -1,4 +1,9 @@ +set adc_fifo_name axi_ad9625_fifo +set adc_fifo_address_width 18 +set adc_data_width 512 +set adc_dma_data_width 64 + source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl source ../common/fmcadc5_bd.tcl diff --git a/projects/fmcomms11/zc706/system_bd.tcl b/projects/fmcomms11/zc706/system_bd.tcl index 3c332f8dd..6052018b7 100644 --- a/projects/fmcomms11/zc706/system_bd.tcl +++ b/projects/fmcomms11/zc706/system_bd.tcl @@ -1,25 +1,16 @@ +set adc_fifo_name axi_ad9625_fifo +set adc_fifo_address_width 18 +set adc_data_width 256 +set adc_dma_data_width 64 + +set dac_fifo_name axi_ad9162_fifo +set dac_fifo_address_width 10 +set dac_data_width 256 +set dac_dma_data_width 256 + source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl - -p_sys_dacfifo [current_bd_instance .] axi_ad9162_fifo 256 10 -p_plddr3_adcfifo [current_bd_instance .] axi_ad9625_fifo 256 - -create_bd_port -dir I -type rst sys_rst -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 -create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk - -set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst] - -ad_connect sys_rst axi_ad9625_fifo/sys_rst -ad_connect sys_clk axi_ad9625_fifo/sys_clk -ad_connect ddr3 axi_ad9625_fifo/ddr3 - -create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \ - [get_bd_addr_spaces axi_ad9625_fifo/axi_adcfifo/axi] \ - [get_bd_addr_segs axi_ad9625_fifo/axi_ddr_cntrl/memmap/memaddr] \ - SEG_axi_ddr_cntrl_memaddr - source ../common/fmcomms11_bd.tcl diff --git a/projects/fmcomms7/zc706/system_bd.tcl b/projects/fmcomms7/zc706/system_bd.tcl index 67b944078..29a658978 100644 --- a/projects/fmcomms7/zc706/system_bd.tcl +++ b/projects/fmcomms7/zc706/system_bd.tcl @@ -1,24 +1,16 @@ +set adc_fifo_name axi_ad9680_fifo +set adc_fifo_address_width 16 +set adc_data_width 128 +set adc_dma_data_width 64 + +set dac_fifo_name axi_ad9144_fifo +set dac_fifo_address_width 10 +set dac_data_width 256 +set dac_dma_data_width 256 + source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl - -p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 -p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 256 10 - -create_bd_port -dir I -type rst sys_rst -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 -create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk - -set_property CONFIG.POLARITY {ACTIVE_HIGH} [get_bd_ports sys_rst] - -ad_connect sys_rst axi_ad9680_fifo/sys_rst -ad_connect sys_clk axi_ad9680_fifo/sys_clk -ad_connect ddr3 axi_ad9680_fifo/ddr3 - -create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \ - [get_bd_addr_spaces axi_ad9680_fifo/axi_adcfifo/axi] \ - [get_bd_addr_segs axi_ad9680_fifo/axi_ddr_cntrl/memmap/memaddr] \ - SEG_axi_ddr_cntrl_memaddr - source ../common/fmcomms7_bd.tcl + diff --git a/projects/usdrx1/zc706/system_bd.tcl b/projects/usdrx1/zc706/system_bd.tcl index a8ce6b623..8502a7fa2 100644 --- a/projects/usdrx1/zc706/system_bd.tcl +++ b/projects/usdrx1/zc706/system_bd.tcl @@ -1,23 +1,10 @@ +set adc_fifo_name usdrx1_fifo +set adc_fifo_address_width 18 +set adc_data_width 512 +set adc_dma_data_width 64 source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl - -p_plddr3_adcfifo [current_bd_instance .] usdrx1_fifo 512 - -create_bd_port -dir I -type rst sys_rst -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 -create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk - -set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst] - -ad_connect sys_rst usdrx1_fifo/sys_rst -ad_connect sys_clk usdrx1_fifo/sys_clk -ad_connect ddr3 usdrx1_fifo/ddr3 - -create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \ - [get_bd_addr_spaces usdrx1_fifo/axi_adcfifo/axi] \ - [get_bd_addr_segs usdrx1_fifo/axi_ddr_cntrl/memmap/memaddr] \ - SEG_axi_ddr_cntrl_memaddr - source ../common/usdrx1_bd.tcl +