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projects/system_bd- adc/dac fifo board designs

main
Rejeesh Kutty 2017-02-27 16:05:21 -05:00
parent 6b1a8852a9
commit fb4a583613
16 changed files with 127 additions and 190 deletions
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23
projects/adrv9371x/zc706/system_bd.tcl
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@ -1,23 +1,10 @@
set dac_fifo_name axi_ad9371_dacfifo
set dac_fifo_address_width 10
set dac_data_width 128
set dac_dma_data_width 128
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_dacfifo_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_dacfifo_bd.tcl
p_plddr3_dacfifo [current_bd_instance .] axi_ad9371_dacfifo 128 128
create_bd_port -dir I -type rst sys_rst
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst]
ad_connect sys_rst axi_ad9371_dacfifo/sys_rst
ad_connect sys_clk axi_ad9371_dacfifo/sys_clk
ad_connect ddr3 axi_ad9371_dacfifo/ddr3
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
[get_bd_addr_spaces axi_ad9371_dacfifo/axi_dacfifo/axi] \
[get_bd_addr_segs axi_ad9371_dacfifo/axi_ddr_cntrl/memmap/memaddr] \
SEG_axi_ddr_cntrl_memaddr
source ../common/adrv9371x_bd.tcl source ../common/adrv9371x_bd.tcl

23
projects/daq1/zc706/system_bd.tcl
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set adc_fifo_name axi_ad9684_fifo
set adc_fifo_address_width 18
set adc_data_width 64
set adc_dma_data_width 64
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl
p_plddr3_adcfifo [current_bd_instance .] axi_ad9684_fifo 64
create_bd_port -dir I -type rst sys_rst
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst]
ad_connect sys_rst axi_ad9684_fifo/sys_rst
ad_connect sys_clk axi_ad9684_fifo/sys_clk
ad_connect ddr3 axi_ad9684_fifo/ddr3
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
[get_bd_addr_spaces axi_ad9684_fifo/axi_adcfifo/axi] \
[get_bd_addr_segs axi_ad9684_fifo/axi_ddr_cntrl/memmap/memaddr] \
SEG_axi_ddr_cntrl_memaddr
source ../common/daq1_bd.tcl source ../common/daq1_bd.tcl

14
projects/daq2/kc705/system_bd.tcl
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set adc_fifo_name axi_ad9680_fifo
set adc_fifo_address_width 16
set adc_data_width 128
set adc_dma_data_width 64
set dac_fifo_name axi_ad9144_fifo
set dac_fifo_address_width 10
set dac_data_width 128
set dac_dma_data_width 128
source $ad_hdl_dir/projects/common/kc705/kc705_system_bd.tcl source $ad_hdl_dir/projects/common/kc705/kc705_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
p_sys_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 16
p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
source ../common/daq2_bd.tcl source ../common/daq2_bd.tcl

14
projects/daq2/kcu105/system_bd.tcl
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set adc_fifo_name axi_ad9680_fifo
set adc_fifo_address_width 16
set adc_data_width 128
set adc_dma_data_width 64
set dac_fifo_name axi_ad9144_fifo
set dac_fifo_address_width 10
set dac_data_width 128
set dac_dma_data_width 128
source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
p_sys_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 16
p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
source ../common/daq2_bd.tcl source ../common/daq2_bd.tcl
set_property -dict [list CONFIG.XCVR_TYPE {1}] $util_daq2_xcvr set_property -dict [list CONFIG.XCVR_TYPE {1}] $util_daq2_xcvr

15
projects/daq2/vc707/system_bd.tcl
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set adc_fifo_name axi_ad9680_fifo
set adc_fifo_address_width 16
set adc_data_width 128
set adc_dma_data_width 64
set dac_fifo_name axi_ad9144_fifo
set dac_fifo_address_width 10
set dac_data_width 128
set dac_dma_data_width 128
source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
p_sys_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 16
p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
source ../common/daq2_bd.tcl source ../common/daq2_bd.tcl

29
projects/daq2/zc706/system_bd.tcl
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set adc_fifo_name axi_ad9680_fifo
set adc_fifo_address_width 16
set adc_data_width 128
set adc_dma_data_width 64
set dac_fifo_name axi_ad9144_fifo
set dac_fifo_address_width 10
set dac_data_width 128
set dac_dma_data_width 128
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128
create_bd_port -dir I -type rst sys_rst
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst]
ad_connect sys_rst axi_ad9680_fifo/sys_rst
ad_connect sys_clk axi_ad9680_fifo/sys_clk
ad_connect ddr3 axi_ad9680_fifo/ddr3
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
[get_bd_addr_spaces axi_ad9680_fifo/axi_adcfifo/axi] \
[get_bd_addr_segs axi_ad9680_fifo/axi_ddr_cntrl/memmap/memaddr] \
SEG_axi_ddr_cntrl_memaddr
source ../common/daq2_bd.tcl source ../common/daq2_bd.tcl

14
projects/daq2/zcu102/system_bd.tcl
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set adc_fifo_name axi_ad9680_fifo
set adc_fifo_address_width 16
set adc_data_width 128
set adc_dma_data_width 64
set dac_fifo_name axi_ad9144_fifo
set dac_fifo_address_width 10
set dac_data_width 128
set dac_dma_data_width 128
source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
p_sys_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 16
p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
source ../common/daq2_bd.tcl source ../common/daq2_bd.tcl
set_property -dict [list CONFIG.XCVR_TYPE {2}] $util_daq2_xcvr set_property -dict [list CONFIG.XCVR_TYPE {2}] $util_daq2_xcvr

14
projects/daq3/kcu105/system_bd.tcl
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set adc_fifo_name axi_ad9680_fifo
set adc_fifo_address_width 16
set adc_data_width 128
set adc_dma_data_width 64
set dac_fifo_name axi_ad9152_fifo
set dac_fifo_address_width 10
set dac_data_width 128
set dac_dma_data_width 128
source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
p_sys_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 16
p_sys_dacfifo [current_bd_instance .] axi_ad9152_fifo 128 10
source ../common/daq3_bd.tcl source ../common/daq3_bd.tcl
set_property -dict [list CONFIG.XCVR_TYPE {1}] $util_daq3_xcvr set_property -dict [list CONFIG.XCVR_TYPE {1}] $util_daq3_xcvr

29
projects/daq3/zc706/system_bd.tcl
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set adc_fifo_name axi_ad9680_fifo
set adc_fifo_address_width 16
set adc_data_width 128
set adc_dma_data_width 64
set dac_fifo_name axi_ad9152_fifo
set dac_fifo_address_width 10
set dac_data_width 128
set dac_dma_data_width 128
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
p_sys_dacfifo [current_bd_instance .] axi_ad9152_fifo 128 10
p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128
create_bd_port -dir I -type rst sys_rst
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst]
ad_connect sys_rst axi_ad9680_fifo/sys_rst
ad_connect sys_clk axi_ad9680_fifo/sys_clk
ad_connect ddr3 axi_ad9680_fifo/ddr3
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
[get_bd_addr_spaces axi_ad9680_fifo/axi_adcfifo/axi] \
[get_bd_addr_segs axi_ad9680_fifo/axi_ddr_cntrl/memmap/memaddr] \
SEG_axi_ddr_cntrl_memaddr
source ../common/daq3_bd.tcl source ../common/daq3_bd.tcl

8
projects/fmcadc2/vc707/system_bd.tcl
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set adc_fifo_name axi_ad9625_fifo
set adc_fifo_address_width 18
set adc_data_width 256
set adc_dma_data_width 64
source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
p_sys_adcfifo [current_bd_instance .] axi_ad9625_fifo 256 18
source ../common/fmcadc2_bd.tcl source ../common/fmcadc2_bd.tcl

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projects/fmcadc2/zc706/system_bd.tcl
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set adc_fifo_name axi_ad9625_fifo
set adc_fifo_address_width 18
set adc_data_width 256
set adc_dma_data_width 64
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl
p_plddr3_adcfifo [current_bd_instance .] axi_ad9625_fifo 256
create_bd_port -dir I -type rst sys_rst
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
set_property CONFIG.POLARITY {ACTIVE_HIGH} [get_bd_ports sys_rst]
ad_connect sys_rst axi_ad9625_fifo/sys_rst
ad_connect sys_clk axi_ad9625_fifo/sys_clk
ad_connect ddr3 axi_ad9625_fifo/ddr3
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
[get_bd_addr_spaces axi_ad9625_fifo/axi_adcfifo/axi] \
[get_bd_addr_segs axi_ad9625_fifo/axi_ddr_cntrl/memmap/memaddr] \
SEG_axi_ddr_cntrl_memaddr
source ../common/fmcadc2_bd.tcl source ../common/fmcadc2_bd.tcl

24
projects/fmcadc4/zc706/system_bd.tcl
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set adc_fifo_name axi_ad9680_fifo
set adc_fifo_address_width 18
set adc_data_width 256
set adc_dma_data_width 64
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl
p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 256
create_bd_port -dir I -type rst sys_rst
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
set_property CONFIG.POLARITY {ACTIVE_HIGH} [get_bd_ports sys_rst]
ad_connect sys_rst axi_ad9680_fifo/sys_rst
ad_connect sys_clk axi_ad9680_fifo/sys_clk
ad_connect ddr3 axi_ad9680_fifo/ddr3
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
[get_bd_addr_spaces axi_ad9680_fifo/axi_adcfifo/axi] \
[get_bd_addr_segs axi_ad9680_fifo/axi_ddr_cntrl/memmap/memaddr] \
SEG_axi_ddr_cntrl_memaddr
source ../common/fmcadc4_bd.tcl source ../common/fmcadc4_bd.tcl

5
projects/fmcadc5/vc707/system_bd.tcl
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set adc_fifo_name axi_ad9625_fifo
set adc_fifo_address_width 18
set adc_data_width 512
set adc_dma_data_width 64
source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
source ../common/fmcadc5_bd.tcl source ../common/fmcadc5_bd.tcl

29
projects/fmcomms11/zc706/system_bd.tcl
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set adc_fifo_name axi_ad9625_fifo
set adc_fifo_address_width 18
set adc_data_width 256
set adc_dma_data_width 64
set dac_fifo_name axi_ad9162_fifo
set dac_fifo_address_width 10
set dac_data_width 256
set dac_dma_data_width 256
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
p_sys_dacfifo [current_bd_instance .] axi_ad9162_fifo 256 10
p_plddr3_adcfifo [current_bd_instance .] axi_ad9625_fifo 256
create_bd_port -dir I -type rst sys_rst
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst]
ad_connect sys_rst axi_ad9625_fifo/sys_rst
ad_connect sys_clk axi_ad9625_fifo/sys_clk
ad_connect ddr3 axi_ad9625_fifo/ddr3
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
[get_bd_addr_spaces axi_ad9625_fifo/axi_adcfifo/axi] \
[get_bd_addr_segs axi_ad9625_fifo/axi_ddr_cntrl/memmap/memaddr] \
SEG_axi_ddr_cntrl_memaddr
source ../common/fmcomms11_bd.tcl source ../common/fmcomms11_bd.tcl

30
projects/fmcomms7/zc706/system_bd.tcl
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set adc_fifo_name axi_ad9680_fifo
set adc_fifo_address_width 16
set adc_data_width 128
set adc_dma_data_width 64
set dac_fifo_name axi_ad9144_fifo
set dac_fifo_address_width 10
set dac_data_width 256
set dac_dma_data_width 256
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128
p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 256 10
create_bd_port -dir I -type rst sys_rst
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
set_property CONFIG.POLARITY {ACTIVE_HIGH} [get_bd_ports sys_rst]
ad_connect sys_rst axi_ad9680_fifo/sys_rst
ad_connect sys_clk axi_ad9680_fifo/sys_clk
ad_connect ddr3 axi_ad9680_fifo/ddr3
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
[get_bd_addr_spaces axi_ad9680_fifo/axi_adcfifo/axi] \
[get_bd_addr_segs axi_ad9680_fifo/axi_ddr_cntrl/memmap/memaddr] \
SEG_axi_ddr_cntrl_memaddr
source ../common/fmcomms7_bd.tcl source ../common/fmcomms7_bd.tcl

23
projects/usdrx1/zc706/system_bd.tcl
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set adc_fifo_name usdrx1_fifo
set adc_fifo_address_width 18
set adc_data_width 512
set adc_dma_data_width 64
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl
p_plddr3_adcfifo [current_bd_instance .] usdrx1_fifo 512
create_bd_port -dir I -type rst sys_rst
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst]
ad_connect sys_rst usdrx1_fifo/sys_rst
ad_connect sys_clk usdrx1_fifo/sys_clk
ad_connect ddr3 usdrx1_fifo/ddr3
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
[get_bd_addr_spaces usdrx1_fifo/axi_adcfifo/axi] \
[get_bd_addr_segs usdrx1_fifo/axi_ddr_cntrl/memmap/memaddr] \
SEG_axi_ddr_cntrl_memaddr
source ../common/usdrx1_bd.tcl source ../common/usdrx1_bd.tcl