From fb945ac51c601a3a7b0673b4a946c1f1c7d520dc Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Tue, 31 Jan 2017 16:18:58 +0200 Subject: [PATCH] axi_ad9963: Initial commit --- library/axi_ad9963/Makefile | 73 ++++ library/axi_ad9963/axi_ad9963.v | 322 ++++++++++++++++ library/axi_ad9963/axi_ad9963_if.v | 297 +++++++++++++++ library/axi_ad9963/axi_ad9963_ip.tcl | 57 +++ library/axi_ad9963/axi_ad9963_rx.v | 252 +++++++++++++ library/axi_ad9963/axi_ad9963_rx_channel.v | 214 +++++++++++ library/axi_ad9963/axi_ad9963_rx_pnmon.v | 121 ++++++ library/axi_ad9963/axi_ad9963_tx.v | 272 ++++++++++++++ library/axi_ad9963/axi_ad9963_tx_channel.v | 415 +++++++++++++++++++++ 9 files changed, 2023 insertions(+) create mode 100644 library/axi_ad9963/Makefile create mode 100644 library/axi_ad9963/axi_ad9963.v create mode 100644 library/axi_ad9963/axi_ad9963_if.v create mode 100644 library/axi_ad9963/axi_ad9963_ip.tcl create mode 100644 library/axi_ad9963/axi_ad9963_rx.v create mode 100644 library/axi_ad9963/axi_ad9963_rx_channel.v create mode 100644 library/axi_ad9963/axi_ad9963_rx_pnmon.v create mode 100644 library/axi_ad9963/axi_ad9963_tx.v create mode 100644 library/axi_ad9963/axi_ad9963_tx_channel.v diff --git a/library/axi_ad9963/Makefile b/library/axi_ad9963/Makefile new file mode 100644 index 000000000..4c5b88c2a --- /dev/null +++ b/library/axi_ad9963/Makefile @@ -0,0 +1,73 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += ../common/ad_axi_ip_constr.xdc +M_DEPS += ../common/ad_datafmt.v +M_DEPS += ../common/ad_dcfilter.v +M_DEPS += ../common/ad_dds.v +M_DEPS += ../common/ad_dds_1.v +M_DEPS += ../common/ad_dds_sine.v +M_DEPS += ../common/ad_iqcor.v +M_DEPS += ../common/ad_pnmon.v +M_DEPS += ../common/ad_rst.v +M_DEPS += ../common/up_adc_channel.v +M_DEPS += ../common/up_adc_common.v +M_DEPS += ../common/up_axi.v +M_DEPS += ../common/up_clock_mon.v +M_DEPS += ../common/up_dac_channel.v +M_DEPS += ../common/up_dac_common.v +M_DEPS += ../common/up_delay_cntrl.v +M_DEPS += ../common/up_xfer_cntrl.v +M_DEPS += ../common/up_xfer_status.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += ../xilinx/common/ad_lvds_in.v +M_DEPS += ../xilinx/common/ad_lvds_out.v +M_DEPS += ../xilinx/common/ad_mul.v +M_DEPS += axi_ad9963.v +M_DEPS += axi_ad9963_if.v +M_DEPS += axi_ad9963_ip.tcl +M_DEPS += axi_ad9963_rx.v +M_DEPS += axi_ad9963_rx_channel.v +M_DEPS += axi_ad9963_rx_pnmon.v +M_DEPS += axi_ad9963_tx.v +M_DEPS += axi_ad9963_tx_channel.v + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all clean clean-all +all: axi_ad9963.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +axi_ad9963.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) axi_ad9963_ip.tcl >> axi_ad9963_ip.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/library/axi_ad9963/axi_ad9963.v b/library/axi_ad9963/axi_ad9963.v new file mode 100644 index 000000000..1bed35e21 --- /dev/null +++ b/library/axi_ad9963/axi_ad9963.v @@ -0,0 +1,322 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9963 #( + + // parameters + + parameter ID = 0, + parameter DEVICE_TYPE = 0, + parameter DAC_IODELAY_ENABLE = 0, + parameter IO_DELAY_GROUP = "dev_if_delay_group", + parameter DAC_DATAPATH_DISABLE = 0, + parameter ADC_DATAPATH_DISABLE = 0 ) ( + + // physical interface (receive) + + input trx_clk, + input trx_iq, + input [11:0] trx_data, + + // physical interface (transmit) + + output tx_clk, + output tx_iq, + output [11:0] tx_data, + + // transmit master/slave + + input dac_sync_in, + output dac_sync_out, + + // delay clock + + input delay_clk, + + // master interface + + output l_clk, + output dac_clk, + output rst, + + // dma interface + + output adc_enable_i, + output adc_valid_i, + output [15:0] adc_data_i, + output adc_enable_q, + output adc_valid_q, + output [15:0] adc_data_q, + input adc_dovf, + input adc_dunf, + + output dac_enable_i, + output dac_valid_i, + input [15:0] dac_data_i, + output dac_enable_q, + output dac_valid_q, + input [15:0] dac_data_q, + input dac_dovf, + input dac_dunf, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready); + + // internal registers + + reg up_wack = 'd0; + reg up_rack = 'd0; + reg [31:0] up_rdata = 'd0; + + // internal clocks and resets + + wire up_clk; + wire up_rstn; + wire delay_rst; + + // internal signals + + wire adc_valid_s; + wire [23:0] adc_data_s; + wire adc_status_s; + wire dac_valid_s; + wire [23:0] dac_data_s; + wire dac_valid_i0_s; + wire dac_valid_q0_s; + wire dac_valid_i1_s; + wire dac_valid_q1_s; + wire [12:0] up_adc_dld_s; + wire [64:0] up_adc_dwdata_s; + wire [64:0] up_adc_drdata_s; + wire [13:0] up_dac_dld_s; + wire [69:0] up_dac_dwdata_s; + wire [69:0] up_dac_drdata_s; + wire delay_locked_s; + wire up_wreq_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire up_wack_rx_s; + wire up_wack_tx_s; + wire up_rreq_s; + wire [13:0] up_raddr_s; + wire [31:0] up_rdata_rx_s; + wire up_rack_rx_s; + wire [31:0] up_rdata_tx_s; + wire up_rack_tx_s; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_wack <= up_wack_rx_s | up_wack_tx_s ; + up_rack <= up_rack_rx_s | up_rack_tx_s ; + up_rdata <= up_rdata_rx_s | up_rdata_tx_s ; + end + end + + // device interface + + axi_ad9963_if #( + .DEVICE_TYPE (DEVICE_TYPE), + .DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IO_DELAY_GROUP (IO_DELAY_GROUP)) + i_dev_if ( + .trx_clk (trx_clk), + .trx_iq (trx_iq), + .trx_data (trx_data), + .tx_clk (tx_clk), + .tx_iq (tx_iq), + .tx_data (tx_data), + .rst (rst), + .l_clk (l_clk), + .dac_clk (dac_clk), + .adc_valid (adc_valid_s), + .adc_data (adc_data_s), + .adc_status (adc_status_s), + .dac_valid (dac_valid_s), + .dac_data (dac_data_s), + .up_clk (up_clk), + .up_adc_dld (up_adc_dld_s), + .up_adc_dwdata (up_adc_dwdata_s), + .up_adc_drdata (up_adc_drdata_s), + .up_dac_dld (up_dac_dld_s), + .up_dac_dwdata (up_dac_dwdata_s), + .up_dac_drdata (up_dac_drdata_s), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s)); + + // receive + + axi_ad9963_rx #( + .ID (ID), + .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE)) + i_rx ( + .adc_rst (rst), + .adc_clk (l_clk), + .adc_valid (adc_valid_s), + .adc_data (adc_data_s), + .adc_status (adc_status_s), + .up_dld (up_adc_dld_s), + .up_dwdata (up_adc_dwdata_s), + .up_drdata (up_adc_drdata_s), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s), + .adc_enable_i (adc_enable_i), + .adc_valid_i (adc_valid_i), + .adc_data_i (adc_data_i), + .adc_enable_q (adc_enable_q), + .adc_valid_q (adc_valid_q), + .adc_data_q (adc_data_q), + .adc_dovf (adc_dovf), + .adc_dunf (adc_dunf), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_rx_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_rx_s), + .up_rack (up_rack_rx_s)); + + // transmit + + axi_ad9963_tx #( + .ID (ID), + .DATAPATH_DISABLE (DAC_DATAPATH_DISABLE)) + i_tx ( + .dac_clk (dac_clk), + .dac_valid (dac_valid_s), + .dac_data (dac_data_s), + .adc_data (adc_data_s), + .up_dld (up_dac_dld_s), + .up_dwdata (up_dac_dwdata_s), + .up_drdata (up_dac_drdata_s), + .delay_clk (delay_clk), + .delay_rst (), + .delay_locked (delay_locked_s), + .dac_sync_in (dac_sync_in), + .dac_sync_out (dac_sync_out), + .dac_enable_i (dac_enable_i), + .dac_valid_i (dac_valid_i), + .dac_data_i (dac_data_i), + .dac_enable_q (dac_enable_q), + .dac_valid_q (dac_valid_q), + .dac_data_q (dac_data_q), + .dac_dovf(dac_dovf), + .dac_dunf(dac_dunf), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_tx_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_tx_s), + .up_rack (up_rack_tx_s)); + + // axi interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9963/axi_ad9963_if.v b/library/axi_ad9963/axi_ad9963_if.v new file mode 100644 index 000000000..d87467530 --- /dev/null +++ b/library/axi_ad9963/axi_ad9963_if.v @@ -0,0 +1,297 @@ +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// This interface includes both the transmit and receive components - +// They both uses the same clock (sourced from the receiving side). +// assumes RX_IQ is 1 for I and 0 for Q (RX_IFIRST = 1 , RXIQ_HILO = 1) + +`timescale 1ns/100ps + +module axi_ad9963_if #( + + // this parameter controls the buffer type based on the target device. + + parameter DEVICE_TYPE = 0, + parameter DAC_IODELAY_ENABLE = 0, + parameter IO_DELAY_GROUP = "dev_if_delay_group") ( + + // physical interface (receive) + + input trx_clk, + input trx_iq, + input [11:0] trx_data, + + // physical interface (transmit) + + output tx_clk, + output tx_iq, + output [11:0] tx_data, + + // clock (common to both receive and transmit) + + input rst, + output l_clk, + output dac_clk, + + // receive data path interface + + output reg adc_valid, + output reg [23:0] adc_data, + output reg adc_status, + + // transmit data path interface + + input dac_valid, + input [23:0] dac_data, + + // delay interface + + input up_clk, + input [12:0] up_adc_dld, + input [64:0] up_adc_dwdata, + output [64:0] up_adc_drdata, + input [13:0] up_dac_dld, + input [69:0] up_dac_dwdata, + output [69:0] up_dac_drdata, + input delay_clk, + input delay_rst, + output delay_locked); + + // internal registers + + reg [11:0] rx_data_p = 0; + reg [11:0] tx_data_p = 'd0; + reg [11:0] tx_data_n = 'd0; + reg tx_n_iq = 'd0; + reg tx_p_iq = 'd0; + + // internal signals + + wire [11:0] rx_data_p_s; + wire [11:0] rx_data_n_s; + wire rx_iq_p_s; + wire rx_iq_n_s; + + wire feedback_clk; + wire tx_clk_pll; + + genvar l_inst; + + always @(posedge l_clk) begin + if( rx_iq_p_s == 1'b1) begin + adc_data <= {rx_data_n_s, rx_data_p_s} ; // data[11:00] I + adc_valid <= 1'b1; // data[23:12] Q + end else begin + rx_data_p <= rx_data_p_s; // if this happens it means that risedge data is sampled on falledge + adc_data <= {rx_data_p, rx_data_n_s} ; // so we take current N data with previous P data + adc_valid <= 1'b1; // in order to have data sampled at the same instance sent to the DMA + end + end + + always @(posedge dac_clk) begin + if(dac_valid == 1'b1) begin + tx_data_p <= dac_data[11:0] ; + tx_data_n <= dac_data[23:12]; + tx_p_iq <= 1'b1; + tx_n_iq <= 1'b0; + end + end + + always @(posedge l_clk) begin + if (rst == 1'b1) begin + adc_status <= 1'b0; + end else begin + adc_status <= 1'b1; + end + end + + // device clock interface (receive clock) + + BUFG i_clk_gbuf ( + .I (trx_clk), + .O (l_clk)); + + // receive data interface, ibuf -> idelay -> iddr + + generate + for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_rx_data + ad_lvds_in #( + .SINGLE_ENDED (1), + .DEVICE_TYPE (DEVICE_TYPE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_rx_data ( + .rx_clk (l_clk), + .rx_data_in_p (trx_data[l_inst]), + .rx_data_in_n (1'b0), + .rx_data_p (rx_data_p_s[l_inst]), + .rx_data_n (rx_data_n_s[l_inst]), + .up_clk (up_clk), + .up_dld (up_adc_dld[l_inst]), + .up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]), + .up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + end + endgenerate + + // receive iq interface, ibuf -> idelay -> iddr + + ad_lvds_in #( + .SINGLE_ENDED (1), + .DEVICE_TYPE (DEVICE_TYPE), + .IODELAY_CTRL (1), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_rx_iq ( + .rx_clk (l_clk), + .rx_data_in_p (trx_iq), + .rx_data_in_n (1'b0), + .rx_data_p (rx_iq_p_s), + .rx_data_n (rx_iq_n_s), + .up_clk (up_clk), + .up_dld (up_adc_dld[12]), + .up_dwdata (up_adc_dwdata[64:60]), + .up_drdata (up_adc_drdata[64:60]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked)); + + // transmit data interface, oddr -> obuf + + generate + for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_tx_data + ad_lvds_out #( + .DEVICE_TYPE (DEVICE_TYPE), + .SINGLE_ENDED (1), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_tx_data ( + .tx_clk (dac_clk), + .tx_data_p (tx_data_p[l_inst]), + .tx_data_n (tx_data_n[l_inst]), + .tx_data_out_p (tx_data[l_inst]), + .tx_data_out_n (), + .up_clk (up_clk), + .up_dld (up_dac_dld[l_inst]), + .up_dwdata (up_dac_dwdata[((l_inst*5)+4):(l_inst*5)]), + .up_drdata (up_dac_drdata[((l_inst*5)+4):(l_inst*5)]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + end + endgenerate + + // transmit iq interface, oddr -> obuf + + ad_lvds_out #( + .DEVICE_TYPE (DEVICE_TYPE), + .SINGLE_ENDED (1), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP)) + i_tx_iq ( + .tx_clk (dac_clk), + .tx_data_p (tx_p_iq), + .tx_data_n (tx_n_iq), + .tx_data_out_p (tx_iq), + .tx_data_out_n (), + .up_clk (up_clk), + .up_dld (up_dac_dld[12]), + .up_dwdata (up_dac_dwdata[64:60]), + .up_drdata (up_dac_drdata[64:60]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + + // transmit clock interface, oddr -> obuf + PLLE2_BASE #( + .BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW + .CLKFBOUT_MULT(15), // Multiply value for all CLKOUT, (2-64) + .CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000). + .CLKIN1_PERIOD(10.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz). + // CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128) + .CLKOUT0_DIVIDE(20), + .CLKOUT1_DIVIDE(20), + .CLKOUT2_DIVIDE(1), + .CLKOUT3_DIVIDE(1), + .CLKOUT4_DIVIDE(1), + .CLKOUT5_DIVIDE(1), + // CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999). + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT5_DUTY_CYCLE(0.5), + // CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000). + .CLKOUT0_PHASE(90.0), + .CLKOUT1_PHASE(0.0), + .CLKOUT2_PHASE(0.0), + .CLKOUT3_PHASE(0.0), + .CLKOUT4_PHASE(0.0), + .CLKOUT5_PHASE(0.0), + .DIVCLK_DIVIDE(1), // Master division value, (1-56) + .REF_JITTER1(0.0), // Reference input jitter in UI, (0.000-0.999). + .STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE") + ) + PLLE2_BASE_inst ( + // Clock Outputs: 1-bit (each) output: User configurable clock outputs + .CLKOUT0(tx_clk_pll), // 1-bit output: CLKOUT0 + .CLKOUT1(dac_clk), // 1-bit output: CLKOUT1 + .CLKOUT2(), // 1-bit output: CLKOUT2 + .CLKOUT3(), // 1-bit output: CLKOUT3 + .CLKOUT4(), // 1-bit output: CLKOUT4 + .CLKOUT5(), // 1-bit output: CLKOUT5 + // Feedback Clocks: 1-bit (each) output: Clock feedback ports + .CLKFBOUT(feedback_clk), // 1-bit output: Feedback clock + .LOCKED(), // 1-bit output: LOCK + .CLKIN1(l_clk), // 1-bit input: Input clock + // Control Ports: 1-bit (each) input: PLL control ports + .PWRDWN(1'b0), // 1-bit input: Power-down + .RST(rst), // 1-bit input: Reset + // Feedback Clocks: 1-bit (each) input: Clock feedback ports + .CLKFBIN(feedback_clk) // 1-bit input: Feedback clock + ); + + ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE"), + .INIT (1'b0), + .SRTYPE ("ASYNC")) + i_tx_clk_oddr( + .CE (1'b1), + .R (1'b0), + .S (1'b0), + .C (tx_clk_pll), + .D1 (1'b1), + .D2 (1'b0), + .Q (tx_clk)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9963/axi_ad9963_ip.tcl b/library/axi_ad9963/axi_ad9963_ip.tcl new file mode 100644 index 000000000..860878395 --- /dev/null +++ b/library/axi_ad9963/axi_ad9963_ip.tcl @@ -0,0 +1,57 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_ad9963 +adi_ip_files axi_ad9963 [list \ + "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_lvds_in.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_lvds_out.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ + "$ad_hdl_dir/library/common/ad_pnmon.v" \ + "$ad_hdl_dir/library/common/ad_dds_sine.v" \ + "$ad_hdl_dir/library/common/ad_dds_1.v" \ + "$ad_hdl_dir/library/common/ad_dds.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/ad_dcfilter.v" \ + "$ad_hdl_dir/library/common/ad_iqcor.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/up_dac_common.v" \ + "$ad_hdl_dir/library/common/up_dac_channel.v" \ + "axi_ad9963_if.v" \ + "axi_ad9963_rx_pnmon.v" \ + "axi_ad9963_rx_channel.v" \ + "axi_ad9963_rx.v" \ + "axi_ad9963_tx_channel.v" \ + "axi_ad9963_tx.v" \ + "axi_ad9963.v" ] + +adi_ip_properties axi_ad9963 +adi_ip_constraints axi_ad9963 [list \ + "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ] + +set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] + +ipx::remove_bus_interface rst [ipx::current_core] +ipx::remove_bus_interface clk [ipx::current_core] +ipx::remove_bus_interface l_clk [ipx::current_core] +ipx::remove_bus_interface delay_clk [ipx::current_core] + +ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \ + -of_objects [ipx::current_core]] +set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ + -of_objects [ipx::get_bus_interfaces s_axi_aclk \ + -of_objects [ipx::current_core]]] + +ipx::save_core [ipx::current_core] + diff --git a/library/axi_ad9963/axi_ad9963_rx.v b/library/axi_ad9963/axi_ad9963_rx.v new file mode 100644 index 000000000..29fea5f15 --- /dev/null +++ b/library/axi_ad9963/axi_ad9963_rx.v @@ -0,0 +1,252 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9963_rx #( + + // parameters + + parameter DATAPATH_DISABLE = 0, + parameter ID = 0) ( + + // adc interface + + output adc_rst, + input adc_clk, + input adc_valid, + input [23:0] adc_data, + input adc_status, + + // delay interface + + output [12:0] up_dld, + output [64:0] up_dwdata, + input [64:0] up_drdata, + input delay_clk, + output delay_rst, + input delay_locked, + + // dma interface + + output adc_enable_i, + output adc_valid_i, + output [15:0] adc_data_i, + output adc_enable_q, + output adc_valid_q, + output [15:0] adc_data_q, + input adc_dovf, + input adc_dunf, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack); + + // internal registers + + reg up_status_pn_err = 'd0; + reg up_status_pn_oos = 'd0; + reg up_status_or = 'd0; + + // internal signals + + wire [15:0] adc_dcfilter_data_out_0_s; + wire [15:0] adc_dcfilter_data_out_1_s; + wire [ 1:0] up_adc_pn_err_s; + wire [ 1:0] up_adc_pn_oos_s; + wire [ 1:0] up_adc_or_s; + wire [31:0] up_rdata_s[0:3]; + wire up_rack_s[0:3]; + wire up_wack_s[0:3]; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_status_pn_err <= 'd0; + up_status_pn_oos <= 'd0; + up_status_or <= 'd0; + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_status_pn_err <= | up_adc_pn_err_s; + up_status_pn_oos <= | up_adc_pn_oos_s; + up_status_or <= | up_adc_or_s; + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3]; + up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3]; + up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3]; + end + end + + // channel 0 (i) + + axi_ad9963_rx_channel #( + .Q_OR_I_N(0), + .CHANNEL_ID(0), + .DATAPATH_DISABLE (DATAPATH_DISABLE)) + i_rx_channel_0 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_valid (adc_valid), + .adc_data (adc_data[11:0]), + .adc_or (1'b0), + .adc_dcfilter_data_out (adc_dcfilter_data_out_0_s), + .adc_dcfilter_data_in (adc_dcfilter_data_out_1_s), + .adc_iqcor_valid (adc_valid_i), + .adc_iqcor_data (adc_data_i), + .adc_enable (adc_enable_i), + .up_adc_pn_err (up_adc_pn_err_s[0]), + .up_adc_pn_oos (up_adc_pn_oos_s[0]), + .up_adc_or (up_adc_or_s[0]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + // channel 1 (q) + + axi_ad9963_rx_channel #( + .Q_OR_I_N(1), + .CHANNEL_ID(1), + .DATAPATH_DISABLE (DATAPATH_DISABLE)) + i_rx_channel_1 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_valid (adc_valid), + .adc_data (adc_data[23:12]), + .adc_or (1'b0), + .adc_dcfilter_data_out (adc_dcfilter_data_out_1_s), + .adc_dcfilter_data_in (adc_dcfilter_data_out_0_s), + .adc_iqcor_valid (adc_valid_q), + .adc_iqcor_data (adc_data_q), + .adc_enable (adc_enable_q), + .up_adc_pn_err (up_adc_pn_err_s[1]), + .up_adc_pn_oos (up_adc_pn_oos_s[1]), + .up_adc_or (up_adc_or_s[1]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + // common processor control + + up_adc_common #(.ID (ID)) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status (adc_status), + .adc_sync_status (1'd0), + .adc_status_ovf (adc_dovf), + .adc_status_unf (adc_dunf), + .adc_clk_ratio (32'd1), + .adc_start_code (), + .adc_sync (), + .up_status_pn_err (up_status_pn_err), + .up_status_pn_oos (up_status_pn_oos), + .up_status_or (up_status_or), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (16'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .up_usr_chanmax (), + .adc_usr_chanmax (8'd1), + .up_adc_gpio_in (32'h0), + .up_adc_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + + // adc delay control + + up_delay_cntrl #(.DATA_WIDTH(13), .BASE_ADDRESS(6'h02)) i_delay_cntrl ( + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked), + .up_dld (up_dld), + .up_dwdata (up_dwdata), + .up_drdata (up_drdata), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[3]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[3]), + .up_rack (up_rack_s[3])); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad9963/axi_ad9963_rx_channel.v b/library/axi_ad9963/axi_ad9963_rx_channel.v new file mode 100644 index 000000000..9c26e04fe --- /dev/null +++ b/library/axi_ad9963/axi_ad9963_rx_channel.v @@ -0,0 +1,214 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9963_rx_channel #( + + // parameters + + parameter Q_OR_I_N = 0, + parameter CHANNEL_ID = 0, + parameter DATAPATH_DISABLE = 0) ( + + // adc interface + + input adc_clk, + input adc_rst, + input adc_valid, + input [11:0] adc_data, + input adc_or, + + // channel interface + + output [15:0] adc_dcfilter_data_out, + input [15:0] adc_dcfilter_data_in, + output adc_iqcor_valid, + output [15:0] adc_iqcor_data, + output adc_enable, + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); + + // internal signals + + wire adc_dfmt_valid_s; + wire [15:0] adc_dfmt_data_s; + wire adc_dcfilter_valid_s; + wire [15:0] adc_dcfilter_data_s; + wire adc_iqcor_enb_s; + wire adc_dcfilt_enb_s; + wire adc_dfmt_se_s; + wire adc_dfmt_type_s; + wire adc_dfmt_enable_s; + wire [15:0] adc_dcfilt_offset_s; + wire [15:0] adc_dcfilt_coeff_s; + wire [15:0] adc_iqcor_coeff_1_s; + wire [15:0] adc_iqcor_coeff_2_s; + wire [ 3:0] adc_pnseq_sel_s; + wire [ 3:0] adc_data_sel_s; + wire adc_pn_err_s; + wire adc_pn_oos_s; + + // iq correction inputs + + assign adc_dcfilter_data_out = adc_dcfilter_data_s; + + axi_ad9963_rx_pnmon i_rx_pnmon ( + .adc_clk (adc_clk), + .adc_valid (adc_valid), + .adc_data (adc_data), + .adc_pnseq_sel (adc_pnseq_sel_s), + .adc_pn_oos (adc_pn_oos_s), + .adc_pn_err (adc_pn_err_s)); + + generate + if (DATAPATH_DISABLE == 1) begin + assign adc_dfmt_valid_s = adc_valid; + assign adc_dfmt_data_s = {4'd0, adc_data}; + end else begin + ad_datafmt #(.DATA_WIDTH (12)) i_ad_datafmt ( + .clk (adc_clk), + .valid (adc_valid), + .data (adc_data), + .valid_out (adc_dfmt_valid_s), + .data_out (adc_dfmt_data_s), + .dfmt_enable (adc_dfmt_enable_s), + .dfmt_type (adc_dfmt_type_s), + .dfmt_se (adc_dfmt_se_s)); + end + endgenerate + + generate + if (DATAPATH_DISABLE == 1) begin + assign adc_dcfilter_valid_s = adc_dfmt_valid_s; + assign adc_dcfilter_data_s = adc_dfmt_data_s; + end else begin + ad_dcfilter i_ad_dcfilter ( + .clk (adc_clk), + .valid (adc_dfmt_valid_s), + .data (adc_dfmt_data_s), + .valid_out (adc_dcfilter_valid_s), + .data_out (adc_dcfilter_data_s), + .dcfilt_enb (adc_dcfilt_enb_s), + .dcfilt_coeff (adc_dcfilt_coeff_s), + .dcfilt_offset (adc_dcfilt_offset_s)); + end + endgenerate + + generate + if (DATAPATH_DISABLE == 1) begin + assign adc_iqcor_valid = adc_dcfilter_valid_s; + assign adc_iqcor_data = adc_dcfilter_data_s; + end else begin + ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor ( + .clk (adc_clk), + .valid (adc_dcfilter_valid_s), + .data_in (adc_dcfilter_data_s), + .data_iq (adc_dcfilter_data_in), + .valid_out (adc_iqcor_valid), + .data_out (adc_iqcor_data), + .iqcor_enable (adc_iqcor_enb_s), + .iqcor_coeff_1 (adc_iqcor_coeff_1_s), + .iqcor_coeff_2 (adc_iqcor_coeff_2_s)); + end + endgenerate + + up_adc_channel #(.CHANNEL_ID (CHANNEL_ID)) i_up_adc_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable), + .adc_iqcor_enb (adc_iqcor_enb_s), + .adc_dcfilt_enb (adc_dcfilt_enb_s), + .adc_dfmt_se (adc_dfmt_se_s), + .adc_dfmt_type (adc_dfmt_type_s), + .adc_dfmt_enable (adc_dfmt_enable_s), + .adc_dcfilt_offset (adc_dcfilt_offset_s), + .adc_dcfilt_coeff (adc_dcfilt_coeff_s), + .adc_iqcor_coeff_1 (adc_iqcor_coeff_1_s), + .adc_iqcor_coeff_2 (adc_iqcor_coeff_2_s), + .adc_pnseq_sel (adc_pnseq_sel_s), + .adc_data_sel (adc_data_sel_s), + .adc_pn_err (adc_pn_err_s), + .adc_pn_oos (adc_pn_oos_s), + .adc_or (adc_or), + .up_adc_pn_err (up_adc_pn_err), + .up_adc_pn_oos (up_adc_pn_oos), + .up_adc_or (up_adc_or), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd16), + .adc_usr_datatype_bits (8'd16), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad9963/axi_ad9963_rx_pnmon.v b/library/axi_ad9963/axi_ad9963_rx_pnmon.v new file mode 100644 index 000000000..6a38eb0f4 --- /dev/null +++ b/library/axi_ad9963/axi_ad9963_rx_pnmon.v @@ -0,0 +1,121 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// PN monitors + +`timescale 1ns/100ps + +module axi_ad9963_rx_pnmon ( + + // adc interface + + input adc_clk, + input adc_valid, + input [11:0] adc_data, + + // pn out of sync and error + + input [ 3:0] adc_pnseq_sel, + output adc_pn_oos, + output adc_pn_err); + + // internal registers + + reg [23:0] adc_pn_data_in = 'd0; + reg [23:0] adc_pn_data_pn = 'd0; + + // internal signals + + wire [31:0] adc_pn_data_pn_s; + + // bit reversal function + + function [11:0] brfn; + input [11:0] din; + reg [11:0] dout; + begin + dout[11] = din[ 0]; + dout[10] = din[ 1]; + dout[ 9] = din[ 2]; + dout[ 8] = din[ 3]; + dout[ 7] = din[ 4]; + dout[ 6] = din[ 5]; + dout[ 5] = din[ 6]; + dout[ 4] = din[ 7]; + dout[ 3] = din[ 8]; + dout[ 2] = din[ 9]; + dout[ 1] = din[10]; + dout[ 0] = din[11]; + brfn = dout; + end + endfunction + + // standard prbs functions + + function [23:0] pn23; + input [23:0] din; + reg [23:0] dout; + begin + dout = {din[22:0], din[22] ^ din[17]}; + pn23 = dout; + end + endfunction + + // standard, runs on 24bit + + assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn; + + always @(posedge adc_clk) begin + if(adc_valid == 1'b1) begin + adc_pn_data_in <= {adc_pn_data_in[22:11], adc_data}; + adc_pn_data_pn <= pn23(adc_pn_data_pn_s); + end + end + + // pn oos & pn err + + ad_pnmon #(.DATA_WIDTH(24)) i_pnmon ( + .adc_clk (adc_clk), + .adc_valid_in (adc_valid), + .adc_data_in (adc_pn_data_in), + .adc_data_pn (adc_pn_data_pn), + .adc_pn_oos (adc_pn_oos), + .adc_pn_err (adc_pn_err)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9963/axi_ad9963_tx.v b/library/axi_ad9963/axi_ad9963_tx.v new file mode 100644 index 000000000..f8ab3eb25 --- /dev/null +++ b/library/axi_ad9963/axi_ad9963_tx.v @@ -0,0 +1,272 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9963_tx #( + + // parameters + + parameter DATAPATH_DISABLE = 0, + parameter ID = 0) ( + + // dac interface + + input dac_clk, + output reg dac_valid, + output [23:0] dac_data, + input [23:0] adc_data, + + // delay interface + + output [13:0] up_dld, + output [69:0] up_dwdata, + input [69:0] up_drdata, + input delay_clk, + output delay_rst, + input delay_locked, + + // master/slave + + input dac_sync_in, + output dac_sync_out, + + // dma interface + + output dac_enable_i, + output reg dac_valid_i, + input [15:0] dac_data_i, + output dac_enable_q, + output reg dac_valid_q, + input [15:0] dac_data_q, + input dac_dovf, + input dac_dunf, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack); + + // internal registers + + reg dac_data_sync = 'd0; + reg [ 7:0] dac_rate_cnt = 'd0; + + // internal clock and resets + + wire dac_rst; + + // internal signals + + wire dac_data_sync_s; + wire dac_dds_format_s; + wire [ 7:0] dac_datarate_s; + wire [23:0] dac_data_int_s; + wire [31:0] up_rdata_s[0:3]; + wire up_rack_s[0:3]; + wire up_wack_s[0:3]; + + // master/slave + + assign dac_data_sync_s = (ID == 0) ? dac_sync_out : dac_sync_in; + + always @(posedge dac_clk) begin + dac_data_sync <= dac_data_sync_s; + end + + // rate counters and data sync signals + + always @(posedge dac_clk) begin + if ((dac_data_sync == 1'b1) || (dac_rate_cnt == 8'd0)) begin + dac_rate_cnt <= dac_datarate_s; + end else begin + dac_rate_cnt <= dac_rate_cnt - 1'b1; + end + end + + // dma interface + + always @(posedge dac_clk) begin + dac_valid <= (dac_rate_cnt == 8'd0) ? 1'b1 : 1'b0; + dac_valid_i <= dac_valid; + dac_valid_q <= dac_valid; + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3]; + up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3]; + up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3]; + end + end + + // dac channel + + axi_ad9963_tx_channel #( + .CHANNEL_ID (0), + .Q_OR_I_N (0), + .DATAPATH_DISABLE (DATAPATH_DISABLE)) + i_tx_channel_0 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_valid (dac_valid), + .dma_data (dac_data_i), + .adc_data (adc_data[11:0]), + .dac_data (dac_data[11:0]), + .dac_data_out (dac_data_int_s[11:0]), + .dac_data_in (dac_data_int_s[23:12]), + .dac_enable (dac_enable_i), + .dac_data_sync (dac_data_sync), + .dac_dds_format (dac_dds_format_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + // dac channel + + axi_ad9963_tx_channel #( + .CHANNEL_ID (1), + .Q_OR_I_N (1), + .DATAPATH_DISABLE (DATAPATH_DISABLE)) + i_tx_channel_1 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_valid (dac_valid), + .dma_data (dac_data_q), + .adc_data (adc_data[23:12]), + .dac_data (dac_data[23:12]), + .dac_data_out (dac_data_int_s[23:12]), + .dac_data_in (dac_data_int_s[11:0]), + .dac_enable (dac_enable_q), + .dac_data_sync (dac_data_sync), + .dac_dds_format (dac_dds_format_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + // dac common processor interface + + up_dac_common #(.ID (ID)) i_up_dac_common ( + .mmcm_rst (), + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_sync (dac_sync_out), + .dac_frame (), + .dac_clksel(), + .dac_par_type (), + .dac_par_enb (), + .dac_r1_mode (), + .dac_datafmt (dac_dds_format_s), + .dac_datarate (dac_datarate_s), + .dac_status (1'b1), + .dac_status_ovf (dac_dovf), + .dac_status_unf (dac_dunf), + .dac_clk_ratio (32'd1), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (16'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .up_usr_chanmax (), + .dac_usr_chanmax (8'd2), + .up_dac_gpio_in (32'h0), + .up_dac_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + + // dac delay control + + up_delay_cntrl #(.DATA_WIDTH(14), .BASE_ADDRESS(6'h12)) i_delay_cntrl ( + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked), + .up_dld (up_dld), + .up_dwdata (up_dwdata), + .up_drdata (up_drdata), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[3]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[3]), + .up_rack (up_rack_s[3])); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_ad9963/axi_ad9963_tx_channel.v b/library/axi_ad9963/axi_ad9963_tx_channel.v new file mode 100644 index 000000000..707843659 --- /dev/null +++ b/library/axi_ad9963/axi_ad9963_tx_channel.v @@ -0,0 +1,415 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9963_tx_channel #( + + // parameters + + parameter CHANNEL_ID = 32'h0, + parameter Q_OR_I_N = 0, + parameter DATAPATH_DISABLE = 0, + localparam PRBS_SEL = CHANNEL_ID, + localparam PRBS_P09 = 0, + localparam PRBS_P11 = 1, + localparam PRBS_P15 = 2, + localparam PRBS_P20 = 3) ( + + // dac interface + + input dac_clk, + input dac_rst, + input dac_valid, + input [15:0] dma_data, + input [11:0] adc_data, + output reg [11:0] dac_data, + output reg [11:0] dac_data_out, + input [11:0] dac_data_in, + + // processor interface + + output reg dac_enable, + input dac_data_sync, + input dac_dds_format, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack); + + // internal registers + + reg dac_valid_sel = 'd0; + reg [23:0] dac_test_data = 'd0; + reg [15:0] dac_test_counter = 'd0; + reg [23:0] dac_pn_seq = 'd0; + reg [11:0] dac_pn_data = 'd0; + reg [15:0] dac_pat_data = 'd0; + reg [15:0] dac_dds_phase_0 = 'd0; + reg [15:0] dac_dds_phase_1 = 'd0; + reg [15:0] dac_dds_incr_0 = 'd0; + reg [15:0] dac_dds_incr_1 = 'd0; + reg [15:0] dac_dds_data = 'd0; + + // internal signals + + wire dac_iqcor_valid_s; + wire [15:0] dac_iqcor_data_s; + wire [15:0] dac_dds_data_s; + wire [15:0] dac_dds_scale_1_s; + wire [15:0] dac_dds_init_1_s; + wire [15:0] dac_dds_incr_1_s; + wire [15:0] dac_dds_scale_2_s; + wire [15:0] dac_dds_init_2_s; + wire [15:0] dac_dds_incr_2_s; + wire [15:0] dac_pat_data_1_s; + wire [15:0] dac_pat_data_2_s; + wire [ 3:0] dac_data_sel_s; + wire dac_iqcor_enb_s; + wire [15:0] dac_iqcor_coeff_1_s; + wire [15:0] dac_iqcor_coeff_2_s; + + // standard prbs functions + + function [23:0] pn1fn; + input [23:0] din; + reg [23:0] dout; + begin + case (PRBS_SEL) + PRBS_P09: begin + dout[23] = din[ 8] ^ din[ 4]; + dout[22] = din[ 7] ^ din[ 3]; + dout[21] = din[ 6] ^ din[ 2]; + dout[20] = din[ 5] ^ din[ 1]; + dout[19] = din[ 4] ^ din[ 0]; + dout[18] = din[ 3] ^ din[ 8] ^ din[ 4]; + dout[17] = din[ 2] ^ din[ 7] ^ din[ 3]; + dout[16] = din[ 1] ^ din[ 6] ^ din[ 2]; + dout[15] = din[ 0] ^ din[ 5] ^ din[ 1]; + dout[14] = din[ 8] ^ din[ 0]; + dout[13] = din[ 7] ^ din[ 8] ^ din[ 4]; + dout[12] = din[ 6] ^ din[ 7] ^ din[ 3]; + dout[11] = din[ 5] ^ din[ 6] ^ din[ 2]; + dout[10] = din[ 4] ^ din[ 5] ^ din[ 1]; + dout[ 9] = din[ 3] ^ din[ 4] ^ din[ 0]; + dout[ 8] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; + dout[ 7] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3]; + dout[ 6] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[ 5] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[ 4] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0]; + dout[ 3] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4]; + dout[ 2] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[ 1] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[ 0] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1]; + end + PRBS_P11: begin + dout[23] = din[10] ^ din[ 8]; + dout[22] = din[ 9] ^ din[ 7]; + dout[21] = din[ 8] ^ din[ 6]; + dout[20] = din[ 7] ^ din[ 5]; + dout[19] = din[ 6] ^ din[ 4]; + dout[18] = din[ 5] ^ din[ 3]; + dout[17] = din[ 4] ^ din[ 2]; + dout[16] = din[ 3] ^ din[ 1]; + dout[15] = din[ 2] ^ din[ 0]; + dout[14] = din[ 1] ^ din[10] ^ din[ 8]; + dout[13] = din[ 0] ^ din[ 9] ^ din[ 7]; + dout[12] = din[10] ^ din[ 6]; + dout[11] = din[ 9] ^ din[ 5]; + dout[10] = din[ 8] ^ din[ 4]; + dout[ 9] = din[ 7] ^ din[ 3]; + dout[ 8] = din[ 6] ^ din[ 2]; + dout[ 7] = din[ 5] ^ din[ 1]; + dout[ 6] = din[ 4] ^ din[ 0]; + dout[ 5] = din[ 3] ^ din[10] ^ din[ 8]; + dout[ 4] = din[ 2] ^ din[ 9] ^ din[ 7]; + dout[ 3] = din[ 1] ^ din[ 8] ^ din[ 6]; + dout[ 2] = din[ 0] ^ din[ 7] ^ din[ 5]; + dout[ 1] = din[10] ^ din[ 6] ^ din[ 8] ^ din[ 4]; + dout[ 0] = din[ 9] ^ din[ 5] ^ din[ 7] ^ din[ 3]; + end + PRBS_P15: begin + dout[23] = din[14] ^ din[13]; + dout[22] = din[13] ^ din[12]; + dout[21] = din[12] ^ din[11]; + dout[20] = din[11] ^ din[10]; + dout[19] = din[10] ^ din[ 9]; + dout[18] = din[ 9] ^ din[ 8]; + dout[17] = din[ 8] ^ din[ 7]; + dout[16] = din[ 7] ^ din[ 6]; + dout[15] = din[ 6] ^ din[ 5]; + dout[14] = din[ 5] ^ din[ 4]; + dout[13] = din[ 4] ^ din[ 3]; + dout[12] = din[ 3] ^ din[ 2]; + dout[11] = din[ 2] ^ din[ 1]; + dout[10] = din[ 1] ^ din[ 0]; + dout[ 9] = din[ 0] ^ din[14] ^ din[13]; + dout[ 8] = din[14] ^ din[12]; + dout[ 7] = din[13] ^ din[11]; + dout[ 6] = din[12] ^ din[10]; + dout[ 5] = din[11] ^ din[ 9]; + dout[ 4] = din[10] ^ din[ 8]; + dout[ 3] = din[ 9] ^ din[ 7]; + dout[ 2] = din[ 8] ^ din[ 6]; + dout[ 1] = din[ 7] ^ din[ 5]; + dout[ 0] = din[ 6] ^ din[ 4]; + end + PRBS_P20: begin + dout[23] = din[19] ^ din[ 2]; + dout[22] = din[18] ^ din[ 1]; + dout[21] = din[17] ^ din[ 0]; + dout[20] = din[16] ^ din[19] ^ din[ 2]; + dout[19] = din[15] ^ din[18] ^ din[ 1]; + dout[18] = din[14] ^ din[17] ^ din[ 0]; + dout[17] = din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[16] = din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[15] = din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[14] = din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[13] = din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[12] = din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[11] = din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[10] = din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[ 9] = din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[ 8] = din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[ 7] = din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[ 6] = din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[ 5] = din[ 1] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[ 4] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[ 3] = din[19] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[ 2] = din[18] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[ 1] = din[17] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[ 0] = din[16] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + end + endcase + pn1fn = dout; + end + endfunction + + // global toggle + + always @(posedge dac_clk) begin + if (dac_data_sync == 1'b1) begin + dac_valid_sel <= 1'b0; + end else if (dac_valid == 1'b1) begin + dac_valid_sel <= ~dac_valid_sel; + end + end + + // dac iq correction + + always @(posedge dac_clk) begin + dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0; + if (dac_iqcor_valid_s == 1'b1) begin + dac_data <= dac_iqcor_data_s[15:4]; + end + end + + generate + if (DATAPATH_DISABLE == 1) begin + assign dac_iqcor_valid_s = dac_valid; + assign dac_iqcor_data_s = {dac_data_out, 4'd0}; + end else begin + ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor ( + .clk (dac_clk), + .valid (dac_valid), + .data_in ({dac_data_out, 4'd0}), + .data_iq ({dac_data_in, 4'd0}), + .valid_out (dac_iqcor_valid_s), + .data_out (dac_iqcor_data_s), + .iqcor_enable (dac_iqcor_enb_s), + .iqcor_coeff_1 (dac_iqcor_coeff_1_s), + .iqcor_coeff_2 (dac_iqcor_coeff_2_s)); + end + endgenerate + + // dac mux + + always @(posedge dac_clk) begin + case (dac_data_sel_s) + 4'h9: dac_data_out <= dac_pn_data; + 4'h8: dac_data_out <= 16'h0; + 4'h6: dac_data_out <= dac_test_data[11:0]; + 4'h5: dac_data_out <= dac_data_out-1; + 4'h4: dac_data_out <= dac_data_out+1; + 4'h3: dac_data_out <= 12'd0; + 4'h2: dac_data_out <= dma_data[15:4]; + 4'h1: dac_data_out <= dac_pat_data[15:4]; + default: dac_data_out <= dac_dds_data[15:4]; + endcase + end + + function [23:0] pn23; + input [23:0] din; + reg [23:0] dout; + begin + dout = {din[22:0], din[22] ^ din[17]}; + pn23 = dout; + end + endfunction + + always @(posedge dac_clk) begin + if(dac_data_sel_s != 6) begin + dac_test_data <= 24'hffffff; + dac_test_counter <= 16'h0; + end else if (dac_test_counter == 1024) begin + dac_test_data <= 24'h0; + end else begin + dac_test_data <= pn23(dac_test_data); + dac_test_counter <= dac_test_counter + 1; + end + end + + // prbs sequences + + always @(posedge dac_clk) begin + if (dac_data_sync == 1'b1) begin + dac_pn_seq <= 24'hffffff; + dac_pn_data <= 12'd0; + end else if (dac_valid == 1'b1) begin + if (dac_valid_sel == 1'b1) begin + dac_pn_seq <= pn1fn(dac_pn_seq); + dac_pn_data <= dac_pn_seq[11: 0]; + end else begin + dac_pn_seq <= dac_pn_seq; + dac_pn_data <= dac_pn_seq[23:12]; + end + end + end + + // pattern + + always @(posedge dac_clk) begin + if (dac_valid == 1'b1) begin + if (dac_valid_sel == 1'b0) begin + dac_pat_data <= dac_pat_data_1_s; + end else begin + dac_pat_data <= dac_pat_data_2_s; + end + end + end + + // dds + + always @(posedge dac_clk) begin + if (dac_data_sync == 1'b1) begin + dac_dds_phase_0 <= dac_dds_init_1_s; + dac_dds_phase_1 <= dac_dds_init_2_s; + dac_dds_incr_0 <= dac_dds_incr_1_s; + dac_dds_incr_1 <= dac_dds_incr_2_s; + dac_dds_data <= 16'd0; + end else if (dac_valid == 1'b1) begin + dac_dds_phase_0 <= dac_dds_phase_0 + dac_dds_incr_0; + dac_dds_phase_1 <= dac_dds_phase_1 + dac_dds_incr_1; + dac_dds_incr_0 <= dac_dds_incr_0; + dac_dds_incr_1 <= dac_dds_incr_1; + dac_dds_data <= dac_dds_data_s; + end + end + + // dds + + generate + if (DATAPATH_DISABLE == 1) begin + assign dac_dds_data_s = 16'd0; + end else begin + ad_dds i_dds ( + .clk (dac_clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_0), + .dds_scale_0 (dac_dds_scale_1_s), + .dds_phase_1 (dac_dds_phase_1), + .dds_scale_1 (dac_dds_scale_2_s), + .dds_data (dac_dds_data_s)); + end + endgenerate + + // single channel processor + + up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_dds_scale_1 (dac_dds_scale_1_s), + .dac_dds_init_1 (dac_dds_init_1_s), + .dac_dds_incr_1 (dac_dds_incr_1_s), + .dac_dds_scale_2 (dac_dds_scale_2_s), + .dac_dds_init_2 (dac_dds_init_2_s), + .dac_dds_incr_2 (dac_dds_incr_2_s), + .dac_pat_data_1 (dac_pat_data_1_s), + .dac_pat_data_2 (dac_pat_data_2_s), + .dac_iq_mode(), + .dac_data_sel (dac_data_sel_s), + .dac_iqcor_enb (dac_iqcor_enb_s), + .dac_iqcor_coeff_1 (dac_iqcor_coeff_1_s), + .dac_iqcor_coeff_2 (dac_iqcor_coeff_2_s), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_interpolation_m (), + .up_usr_interpolation_n (), + .dac_usr_datatype_be (1'b0), + .dac_usr_datatype_signed (1'b1), + .dac_usr_datatype_shift (8'd0), + .dac_usr_datatype_total_bits (8'd16), + .dac_usr_datatype_bits (8'd16), + .dac_usr_interpolation_m (16'd1), + .dac_usr_interpolation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + +// *************************************************************************** +// ***************************************************************************