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motcon2_fmc: Updated to the latest framework

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Adrian Costina 2015-04-01 11:45:01 +03:00
parent de12184038
commit fbfbfdaf87
4 changed files with 931 additions and 440 deletions
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projects/motcon2_fmc/common/motcon2_fmc_bd.tcl
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@ -1,275 +1,558 @@
# motor control
# port definition
# position detection interface
create_bd_port -dir I -from 2 -to 0 position_m1_i
create_bd_port -dir I -from 2 -to 0 position_m2_i
set position_i [ create_bd_port -dir I -from 2 -to 0 position_i ]
# current monitor 1 interface
set adc_clk_o [ create_bd_port -dir O adc_clk_o ]
set adc_m1_ia_dat_i [ create_bd_port -dir I adc_m1_ia_dat_i ]
set adc_m1_ib_dat_i [ create_bd_port -dir I adc_m1_ib_dat_i ]
set adc_m1_vbus_dat_i [ create_bd_port -dir I adc_m1_vbus_dat_i ]
# current monitor 2 interface
set adc_m2_ia_dat_i [ create_bd_port -dir I adc_m2_ia_dat_i ]
set adc_m2_ib_dat_i [ create_bd_port -dir I adc_m2_ib_dat_i ]
set adc_m2_vbus_dat_i [ create_bd_port -dir I adc_m2_vbus_dat_i ]
# current monitor interface
# clock
create_bd_port -dir O adc_clk_o
# data motor 1
create_bd_port -dir I adc_m1_ia_dat_i
create_bd_port -dir I adc_m1_ib_dat_i
create_bd_port -dir I adc_m1_vbus_dat_i
# data motor 2
create_bd_port -dir I adc_m2_ia_dat_i
create_bd_port -dir I adc_m2_ib_dat_i
create_bd_port -dir I adc_m2_vbus_dat_i
# motor control interface
set fmc_m1_en_o [ create_bd_port -dir O fmc_m1_en_o ]
set fmc_m2_en_o [ create_bd_port -dir O fmc_m2_en_o ]
# gpo interface
set gpo_o [ create_bd_port -dir O -from 3 -to 0 gpo_o ]
# interrupts
set motcon2_c_m_1_irq [create_bd_port -dir O motcon2_c_m_1_irq]
set motcon2_c_m_2_irq [create_bd_port -dir O motcon2_c_m_2_irq]
set motcon2_s_d_irq [create_bd_port -dir O motcon2_s_d_irq]
create_bd_port -dir o -from 3 -to 0 gpo_o
# motor 1
create_bd_port -dir O fmc_m1_en_o
create_bd_port -dir O pwm_m1_al_o
create_bd_port -dir O pwm_m1_ah_o
create_bd_port -dir O pwm_m1_cl_o
create_bd_port -dir O pwm_m1_ch_o
create_bd_port -dir O pwm_m1_bl_o
create_bd_port -dir O pwm_m1_bh_o
# motor 2
create_bd_port -dir O fmc_m2_en_o
create_bd_port -dir O pwm_m2_al_o
create_bd_port -dir O pwm_m2_ah_o
create_bd_port -dir O pwm_m2_cl_o
create_bd_port -dir O pwm_m2_ch_o
create_bd_port -dir O pwm_m2_bl_o
create_bd_port -dir O pwm_m2_bh_o
# Ethernet
# phy 1
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rgmii_rtl:1.0 eth1_rgmii
# phy 2
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rgmii_rtl:1.0 eth2_rgmii
#common mdio interface
create_bd_port -dir O eth_mdio_mdc
create_bd_port -dir O eth_mdio_o
create_bd_port -dir O eth_mdio_t
create_bd_port -dir I eth_mdio_i
#common reset
create_bd_port -dir O eth_phy_rst_n
# reference clock for the delay interface used for the gmii to rgmii conversion
create_bd_port -dir o -type clk refclk
create_bd_port -dir o -from 0 -to 0 -type rst refclk_rst
set eth2_mdio [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 eth2_mdio ]
set eth2_rgmii [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rgmii_rtl:1.0 eth2_rgmii ]
set eth2_phy_rst_n [ create_bd_port -dir O eth2_phy_rst_n ]
# iic
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_ee2
# xadc interface
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vaux0
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 vaux8
create_bd_port -dir O -from 4 -to 0 muxaddr_out
# core instantiation and configuration
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn
# additions to default configuration
set_property -dict [list CONFIG.NUM_MI {14}] $axi_cpu_interconnect
# Enable additional peripherals from the PS7 block
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1} ] $sys_ps7
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1} ] $sys_ps7
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1} ] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1} ] $sys_ps7
set_property -dict [list CONFIG.PCW_ENET0_ENET0_IO {EMIO} ] $sys_ps7
set_property -dict [list CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {1} ] $sys_ps7
# current monitor 1 peripherals
# Add additional clocks to be used by gmii to rgmii modules and current monitoring modules
set_property -dict [ list CONFIG.CLKOUT2_USED {true} ] $sys_audio_clkgen
set_property -dict [ list CONFIG.CLKOUT3_USED {true} ] $sys_audio_clkgen
set_property -dict [ list CONFIG.CLKOUT4_USED {true} ] $sys_audio_clkgen
set_property -dict [ list CONFIG.CLKOUT5_USED {true} ] $sys_audio_clkgen
set_property -dict [ list CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {125} ] $sys_audio_clkgen
set_property -dict [ list CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {25} ] $sys_audio_clkgen
set_property -dict [ list CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {20} ] $sys_audio_clkgen
set_property -dict [ list CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {20} ] $sys_audio_clkgen
set_property -dict [ list CONFIG.CLKOUT2_DRIVES {No_buffer} ] $sys_audio_clkgen
set_property -dict [ list CONFIG.CLKOUT3_DRIVES {No_buffer} ] $sys_audio_clkgen
set_property -dict [ list CONFIG.CLKOUT4_DRIVES {No_buffer} ] $sys_audio_clkgen
set axi_mc_current_monitor_1 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_current_monitor:1.0 axi_mc_current_monitor_1 ]
# speed detectors
# speed detector core motor 1
set speed_detector_m1 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_speed:1.0 speed_detector_m1 ]
# dma motor 1
set speed_detector_m1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 speed_detector_m1_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $speed_detector_m1_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $speed_detector_m1_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $speed_detector_m1_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $speed_detector_m1_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $speed_detector_m1_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {32}] $speed_detector_m1_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $speed_detector_m1_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {0}] $speed_detector_m1_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $speed_detector_m1_dma
# speed detector core motor 2
set speed_detector_m2 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_speed:1.0 speed_detector_m2 ]
# dma motor 2
set speed_detector_m2_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 speed_detector_m2_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $speed_detector_m2_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $speed_detector_m2_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $speed_detector_m2_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $speed_detector_m2_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $speed_detector_m2_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {32}] $speed_detector_m2_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $speed_detector_m2_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {0}] $speed_detector_m2_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $speed_detector_m2_dma
set axi_current_monitor_1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_current_monitor_1_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_current_monitor_1_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_current_monitor_1_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_current_monitor_1_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_current_monitor_1_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_current_monitor_1_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_current_monitor_1_dma
set_property -dict [list CONFIG.C_DMA_AXI_PROTOCOL_DEST {1}] $axi_current_monitor_1_dma
# current monitor peripherals
# current monitor core motor 1
set current_monitor_m1 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_current_monitor:1.0 current_monitor_m1 ]
# dma motor 1
set current_monitor_m1_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 current_monitor_m1_dma ]
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $current_monitor_m1_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $current_monitor_m1_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $current_monitor_m1_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $current_monitor_m1_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {0}] $current_monitor_m1_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $current_monitor_m1_dma
# data packer motor 1
#
set current_monitor_m1_apack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 current_monitor_m1_apack]
set_property -dict [list CONFIG.CHANNELS {4}] $current_monitor_m1_apack
# set current_monitor_m1_pack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 current_monitor_m1_pack ]
# set_property -dict [ list CONFIG.CH_CNT {4} ] $current_monitor_m1_pack
# set_property -dict [ list CONFIG.CH_DW {16} ] $current_monitor_m1_pack
# current monitor 2 peripherals
# current monitor core motor 2
set current_monitor_m2 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_current_monitor:1.0 current_monitor_m2 ]
# dma motor 2
set current_monitor_m2_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 current_monitor_m2_dma ]
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $current_monitor_m2_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $current_monitor_m2_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $current_monitor_m2_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $current_monitor_m2_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {0}] $current_monitor_m2_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $current_monitor_m2_dma
# data packer motor 2
set current_monitor_m2_apack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 current_monitor_m2_apack]
set_property -dict [list CONFIG.CHANNELS {4}] $current_monitor_m2_apack
#set current_monitor_m2_pack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 current_monitor_m2_pack ]
#set_property -dict [ list CONFIG.CH_CNT {4} ] $current_monitor_m2_pack
#set_property -dict [ list CONFIG.CH_DW {16} ] $current_monitor_m2_pack
set axi_mc_current_monitor_2 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_current_monitor:1.0 axi_mc_current_monitor_2 ]
#controller
# controller core motor 1
set controller_m1 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_controller:1.0 controller_m1 ]
# dma motor 1
set controller_m1_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 controller_m1_dma ]
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $controller_m1_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $controller_m1_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {256}] $controller_m1_dma
# data packer motor 1
set controller_m1_apack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 controller_m1_apack]
set_property -dict [list CONFIG.CHANNELS {8}] $controller_m1_apack
set_property -dict [list CONFIG.DATA_WIDTH {32}] $controller_m1_apack
set axi_current_monitor_2_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_current_monitor_2_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_current_monitor_2_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_current_monitor_2_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_current_monitor_2_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_current_monitor_2_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_current_monitor_2_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_current_monitor_2_dma
set_property -dict [list CONFIG.C_DMA_AXI_PROTOCOL_DEST {1}] $axi_current_monitor_2_dma
#set controller_m1_pack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 controller_m1_pack ]
#set_property -dict [ list CONFIG.CH_CNT {8} ] $controller_m1_pack
#set_property -dict [ list CONFIG.CH_DW {32} ] $controller_m1_pack
# controller core motor 2
set controller_m2 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_controller:1.0 controller_m2 ]
# dma motor 2
set controller_m2_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 controller_m2_dma ]
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $controller_m2_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $controller_m2_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {256}] $controller_m2_dma
# data packer motor 2
#set controller_m2_pack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 controller_m2_pack ]
#set_property -dict [ list CONFIG.CH_CNT {8} ] $controller_m2_pack
set controller_m2_apack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 controller_m2_apack]
set_property -dict [list CONFIG.CHANNELS {8}] $controller_m2_apack
set_property -dict [list CONFIG.DATA_WIDTH {32}] $controller_m2_apack
# speed detector
#ethernet gmii to rgmii converters
# phy 1
set gmii_to_rgmii_eth1 [ create_bd_cell -type ip -vlnv analog.com:user:util_gmii_to_rgmii:1.0 gmii_to_rgmii_eth1 ]
set_property -dict [list CONFIG.PHY_AD {"00000"}] [get_bd_cells gmii_to_rgmii_eth1]
# phy 2
set gmii_to_rgmii_eth2 [ create_bd_cell -type ip -vlnv analog.com:user:util_gmii_to_rgmii:1.0 gmii_to_rgmii_eth2 ]
set_property -dict [list CONFIG.PHY_AD {"00001"}] [get_bd_cells gmii_to_rgmii_eth2]
# set axi_mc_speed_1 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_speed:1.0 axi_mc_speed_1 ]
# set axi_speed_detector_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_speed_detector_dma]
# set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_speed_detector_dma
# set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_speed_detector_dma
# set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_speed_detector_dma
# set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_speed_detector_dma
# set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_speed_detector_dma
# set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {32}] $axi_speed_detector_dma
# set_property -dict [list CONFIG.C_DMA_AXI_PROTOCOL_DEST {1}] $axi_speed_detector_dma
# iic
set iic_ee2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 iic_ee2 ]
# xadc
set xadc_wiz_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.0 xadc_wiz_1 ]
set_property -dict [ list CONFIG.CHANNEL_ENABLE_VAUXP0_VAUXN0 {true} ] $xadc_wiz_1
set_property -dict [ list CONFIG.ENABLE_EXTERNAL_MUX {false} ] $xadc_wiz_1
set_property -dict [ list CONFIG.OT_ALARM {false} ] $xadc_wiz_1
set_property -dict [ list CONFIG.USER_TEMP_ALARM {false} ] $xadc_wiz_1
set_property -dict [ list CONFIG.VCCAUX_ALARM {false} ] $xadc_wiz_1
set_property -dict [ list CONFIG.VCCINT_ALARM {false} ] $xadc_wiz_1
set_property -dict [ list CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} ] $xadc_wiz_1
#ethernet
set gmii_to_rgmii_eth2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:gmii_to_rgmii:3.0 gmii_to_rgmii_eth2 ]
set_property -dict [ list CONFIG.C_PHYADDR {1} CONFIG.SupportLevel {Include_Shared_Logic_in_Core} ] $gmii_to_rgmii_eth2
set xadc_core [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.0 xadc_core ]
set_property -dict [ list CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} ] $xadc_core
set_property -dict [ list CONFIG.ENABLE_EXTERNAL_MUX {false} ] $xadc_core
set_property -dict [ list CONFIG.CHANNEL_ENABLE_VAUXP0_VAUXN0 {true} ] $xadc_core
set_property -dict [ list CONFIG.OT_ALARM {false} ] $xadc_core
set_property -dict [ list CONFIG.USER_TEMP_ALARM {false} ] $xadc_core
set_property -dict [ list CONFIG.VCCAUX_ALARM {false} ] $xadc_core
set_property -dict [ list CONFIG.VCCINT_ALARM {false} ] $xadc_core
# connections
# position
# connect_bd_net -net position_i_1 [get_bd_ports position_i] [get_bd_pins axi_mc_speed_1/position_i]
# connect_bd_net -net position_i_1 [get_bd_pins axi_mc_speed_1/bemf_i]
# current monitor 1
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_current_monitor_1/ref_clk] $sys_100m_clk_source
connect_bd_net -net adc_m1_ia_dat_i_1 [get_bd_ports adc_m1_ia_dat_i] [get_bd_pins axi_mc_current_monitor_1/adc_ia_dat_i]
connect_bd_net -net adc_m1_ib_dat_i_1 [get_bd_ports adc_m1_ib_dat_i] [get_bd_pins axi_mc_current_monitor_1/adc_ib_dat_i]
connect_bd_net -net adc_m1_vbus_dat_i_1 [get_bd_ports adc_m1_vbus_dat_i] [get_bd_pins axi_mc_current_monitor_1/adc_vbus_dat_i]
connect_bd_net -net axi_mc_current_monitor_1_adc_ia_clk_o [get_bd_ports adc_clk_o] [get_bd_pins axi_mc_current_monitor_1/adc_ia_clk_o]
connect_bd_net -net axi_mc_current_monitor_1_adc_clk [get_bd_pins axi_mc_current_monitor_1/adc_clk_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_clk]
connect_bd_net -net axi_mc_current_monitor_1_adc_dwr [get_bd_pins axi_mc_current_monitor_1/adc_dwr_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_en]
connect_bd_net -net axi_mc_current_monitor_1_adc_ddata [get_bd_pins axi_mc_current_monitor_1/adc_ddata_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_din]
connect_bd_net -net axi_mc_current_monitor_1_adc_dsync [get_bd_pins axi_mc_current_monitor_1/adc_dsync_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_sync]
connect_bd_net -net axi_mc_current_monitor_1_adc_dovf [get_bd_pins axi_mc_current_monitor_1/adc_dovf_i] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_overflow]
# interrupt
connect_bd_net -net axi_current_monitor_1_dma_irq [get_bd_pins axi_current_monitor_1_dma/irq] [get_bd_ports motcon2_c_m_1_irq]
# current monitor 2
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_current_monitor_2/ref_clk] $sys_100m_clk_source
connect_bd_net -net adc_m2_ia_dat_i [get_bd_ports adc_m2_ia_dat_i] [get_bd_pins axi_mc_current_monitor_2/adc_ia_dat_i]
connect_bd_net -net adc_m2_ib_dat_i [get_bd_ports adc_m2_ib_dat_i] [get_bd_pins axi_mc_current_monitor_2/adc_ib_dat_i]
connect_bd_net -net adc_m2_vbus_dat_i_1 [get_bd_ports adc_m2_vbus_dat_i] [get_bd_pins axi_mc_current_monitor_2/adc_vbus_dat_i]
connect_bd_net -net axi_mc_current_monitor_2_adc_clk [get_bd_pins axi_mc_current_monitor_2/adc_clk_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_clk]
connect_bd_net -net axi_mc_current_monitor_2_adc_dwr [get_bd_pins axi_mc_current_monitor_2/adc_dwr_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_en]
connect_bd_net -net axi_mc_current_monitor_2_adc_ddata [get_bd_pins axi_mc_current_monitor_2/adc_ddata_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_din]
connect_bd_net -net axi_mc_current_monitor_2_adc_dsync [get_bd_pins axi_mc_current_monitor_2/adc_dsync_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_sync]
connect_bd_net -net axi_mc_current_monitor_2_adc_dovf [get_bd_pins axi_mc_current_monitor_2/adc_dovf_i] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_overflow]
#interrupt
connect_bd_net -net axi_current_monitor_2_dma_irq [get_bd_pins axi_current_monitor_2_dma/irq] [get_bd_ports motcon2_c_m_2_irq]
# speed detector
# motor 1
ad_connect sys_cpu_clk speed_detector_m1/ref_clk
# connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_speed_1/ref_clk] $sys_100m_clk_source
ad_connect sys_cpu_clk speed_detector_m1_dma/fifo_wr_clk
ad_connect position_m1_i speed_detector_m1/position_i
ad_connect speed_detector_m1/new_speed_o speed_detector_m1_dma/fifo_wr_en
ad_connect speed_detector_m1/speed_o speed_detector_m1_dma/fifo_wr_din
# motor 2
ad_connect sys_cpu_clk speed_detector_m2/ref_clk
ad_connect sys_cpu_clk speed_detector_m2_dma/fifo_wr_clk
ad_connect position_m2_i speed_detector_m2/position_i
ad_connect speed_detector_m2/new_speed_o speed_detector_m2_dma/fifo_wr_en
ad_connect speed_detector_m2/speed_o speed_detector_m2_dma/fifo_wr_din
# current monitor
ad_connect adc_clk_o current_monitor_m1/adc_clk_o
# motor 1
ad_connect sys_cpu_clk current_monitor_m1/ref_clk
ad_connect sys_cpu_clk current_monitor_m1_dma/fifo_wr_clk
ad_connect current_monitor_m1/adc_clk_i sys_audio_clkgen/clk_out5
ad_connect adc_m1_ia_dat_i current_monitor_m1/adc_ia_dat_i
ad_connect adc_m1_ib_dat_i current_monitor_m1/adc_ib_dat_i
ad_connect adc_m1_vbus_dat_i current_monitor_m1/adc_vbus_dat_i
ad_connect sys_cpu_clk current_monitor_m1_apack/clk
ad_connect current_monitor_m1/adc_enable_ia current_monitor_m1_apack/chan_enable_0
ad_connect current_monitor_m1/adc_enable_ib current_monitor_m1_apack/chan_enable_1
ad_connect current_monitor_m1/adc_enable_vbus current_monitor_m1_apack/chan_enable_2
ad_connect current_monitor_m1/adc_enable_stub current_monitor_m1_apack/chan_enable_3
ad_connect current_monitor_m1_apack/chan_valid_0 current_monitor_m1/i_ready_o
ad_connect current_monitor_m1_apack/chan_valid_1 current_monitor_m1/i_ready_o
ad_connect current_monitor_m1_apack/chan_valid_2 current_monitor_m1/i_ready_o
ad_connect current_monitor_m1_apack/chan_valid_3 current_monitor_m1/i_ready_o
ad_connect current_monitor_m1/ia_o current_monitor_m1_apack/chan_data_0
ad_connect current_monitor_m1/ib_o current_monitor_m1_apack/chan_data_1
ad_connect current_monitor_m1/vbus_o current_monitor_m1_apack/chan_data_2
ad_connect current_monitor_m1/vbus_o current_monitor_m1_apack/chan_data_3
ad_connect current_monitor_m1_apack/ddata current_monitor_m1_dma/fifo_wr_din
ad_connect current_monitor_m1_apack/dvalid current_monitor_m1_dma/fifo_wr_en
# connect_bd_net -net [get_bd_nets sys_100m_clk] [get_bd_pins current_monitor_m1_pack/adc_clk] [get_bd_pins sys_ps7/FCLK_CLK0]
# connect_bd_net -net [get_bd_nets sys_rstgen_peripheral_reset] [get_bd_pins current_monitor_m1_pack/adc_rst] [get_bd_pins sys_rstgen/peripheral_reset]
# connect_bd_net -net current_monitor_m1_adc_enable_ia [get_bd_pins current_monitor_m1/adc_enable_ia] [get_bd_pins current_monitor_m1_pack/adc_enable_0]
# connect_bd_net -net current_monitor_m1_adc_enable_ib [get_bd_pins current_monitor_m1/adc_enable_ib] [get_bd_pins current_monitor_m1_pack/adc_enable_1]
# connect_bd_net -net current_monitor_m1_adc_enable_vbus [get_bd_pins current_monitor_m1/adc_enable_vbus] [get_bd_pins current_monitor_m1_pack/adc_enable_2]
# connect_bd_net -net current_monitor_m1_adc_enable_stub [get_bd_pins current_monitor_m1/adc_enable_stub] [get_bd_pins current_monitor_m1_pack/adc_enable_3]
# connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_pack/adc_valid_0] [get_bd_pins current_monitor_m1/i_ready_o]
# connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_pack/adc_valid_1] [get_bd_pins current_monitor_m1/i_ready_o]
# connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_pack/adc_valid_2] [get_bd_pins current_monitor_m1/i_ready_o]
# connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_pack/adc_valid_3] [get_bd_pins current_monitor_m1/i_ready_o]
# connect_bd_net [get_bd_pins current_monitor_m1/ia_o] [get_bd_pins current_monitor_m1_pack/adc_data_0]
# connect_bd_net [get_bd_pins current_monitor_m1/ib_o] [get_bd_pins current_monitor_m1_pack/adc_data_1]
# connect_bd_net [get_bd_pins current_monitor_m1/vbus_o] [get_bd_pins current_monitor_m1_pack/adc_data_2]
# connect_bd_net [get_bd_pins current_monitor_m1/vbus_o] [get_bd_pins current_monitor_m1_pack/adc_data_3]
# connect_bd_net [get_bd_pins current_monitor_m1_pack/adc_data] [get_bd_pins current_monitor_m1_dma/fifo_wr_din]
# connect_bd_net [get_bd_pins current_monitor_m1_pack/adc_valid] [get_bd_pins current_monitor_m1_dma/fifo_wr_en]
# motor 2
ad_connect sys_cpu_clk current_monitor_m2/ref_clk
ad_connect sys_cpu_clk current_monitor_m2_dma/fifo_wr_clk
ad_connect current_monitor_m2/adc_clk_i sys_audio_clkgen/clk_out5
ad_connect adc_m2_ia_dat_i current_monitor_m2/adc_ia_dat_i
ad_connect adc_m2_ib_dat_i current_monitor_m2/adc_ib_dat_i
ad_connect adc_m2_vbus_dat_i current_monitor_m2/adc_vbus_dat_i
ad_connect sys_cpu_clk current_monitor_m2_apack/clk
ad_connect current_monitor_m2/adc_enable_ia current_monitor_m2_apack/chan_enable_0
ad_connect current_monitor_m2/adc_enable_ib current_monitor_m2_apack/chan_enable_1
ad_connect current_monitor_m2/adc_enable_vbus current_monitor_m2_apack/chan_enable_2
ad_connect current_monitor_m2/adc_enable_stub current_monitor_m2_apack/chan_enable_3
ad_connect current_monitor_m2_apack/chan_valid_0 current_monitor_m2/i_ready_o
ad_connect current_monitor_m2_apack/chan_valid_1 current_monitor_m2/i_ready_o
ad_connect current_monitor_m2_apack/chan_valid_2 current_monitor_m2/i_ready_o
ad_connect current_monitor_m2_apack/chan_valid_3 current_monitor_m2/i_ready_o
ad_connect current_monitor_m2/ia_o current_monitor_m2_apack/chan_data_0
ad_connect current_monitor_m2/ib_o current_monitor_m2_apack/chan_data_1
ad_connect current_monitor_m2/vbus_o current_monitor_m2_apack/chan_data_2
ad_connect current_monitor_m2/vbus_o current_monitor_m2_apack/chan_data_3
ad_connect current_monitor_m2_apack/ddata current_monitor_m2_dma/fifo_wr_din
ad_connect current_monitor_m2_apack/dvalid current_monitor_m2_dma/fifo_wr_en
# connect_bd_net -net [get_bd_nets sys_100m_clk] [get_bd_pins current_monitor_m2_pack/adc_clk] [get_bd_pins sys_ps7/FCLK_CLK0]
# connect_bd_net -net [get_bd_nets sys_rstgen_peripheral_reset] [get_bd_pins current_monitor_m2_pack/adc_rst] [get_bd_pins sys_rstgen/peripheral_reset]
# connect_bd_net -net current_monitor_m2_adc_enable_ia [get_bd_pins current_monitor_m2/adc_enable_ia] [get_bd_pins current_monitor_m2_pack/adc_enable_0]
# connect_bd_net -net current_monitor_m2_adc_enable_ib [get_bd_pins current_monitor_m2/adc_enable_ib] [get_bd_pins current_monitor_m2_pack/adc_enable_1]
# connect_bd_net -net current_monitor_m2_adc_enable_vbus [get_bd_pins current_monitor_m2/adc_enable_vbus] [get_bd_pins current_monitor_m2_pack/adc_enable_2]
# connect_bd_net -net current_monitor_m2_adc_enable_stub [get_bd_pins current_monitor_m2/adc_enable_stub] [get_bd_pins current_monitor_m2_pack/adc_enable_3]
# connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_pack/adc_valid_0] [get_bd_pins current_monitor_m2/i_ready_o]
# connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_pack/adc_valid_1] [get_bd_pins current_monitor_m2/i_ready_o]
# connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_pack/adc_valid_2] [get_bd_pins current_monitor_m2/i_ready_o]
# connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_pack/adc_valid_3] [get_bd_pins current_monitor_m2/i_ready_o]
# connect_bd_net [get_bd_pins current_monitor_m2/ia_o] [get_bd_pins current_monitor_m2_pack/adc_data_0]
# connect_bd_net [get_bd_pins current_monitor_m2/ib_o] [get_bd_pins current_monitor_m2_pack/adc_data_1]
# connect_bd_net [get_bd_pins current_monitor_m2/vbus_o] [get_bd_pins current_monitor_m2_pack/adc_data_2]
# connect_bd_net [get_bd_pins current_monitor_m2/vbus_o] [get_bd_pins current_monitor_m2_pack/adc_data_3]
# connect_bd_net [get_bd_pins current_monitor_m2_pack/adc_valid] [get_bd_pins current_monitor_m2_dma/fifo_wr_en]
# connect_bd_net [get_bd_pins current_monitor_m2_pack/adc_data] [get_bd_pins current_monitor_m2_dma/fifo_wr_din]
#controller
# motor 1
ad_connect sys_cpu_clk controller_m1/ref_clk
ad_connect controller_m1/ctrl_data_clk sys_audio_clkgen/clk_out5
ad_connect sys_cpu_clk controller_m1_dma/fifo_wr_clk
ad_connect fmc_m1_en_o controller_m1/fmc_en_o
ad_connect pwm_m1_al_o controller_m1/pwm_al_o
ad_connect pwm_m1_ah_o controller_m1/pwm_ah_o
ad_connect pwm_m1_bl_o controller_m1/pwm_bl_o
ad_connect pwm_m1_bh_o controller_m1/pwm_bh_o
ad_connect pwm_m1_cl_o controller_m1/pwm_cl_o
ad_connect pwm_m1_ch_o controller_m1/pwm_ch_o
ad_connect controller_m1/sensors_o speed_detector_m1/hall_bemf_i
ad_connect controller_m1/position_i speed_detector_m1/position_o
ad_connect controller_m1/ctrl_data_valid_i current_monitor_m1/i_ready_o
#connect_bd_net -net controller_m1_adc_clk_o [get_bd_pins controller_m1_pack/adc_clk] [get_bd_pins controller_m1/adc_clk_o]
#connect_bd_net -net [get_bd_nets sys_rstgen_peripheral_reset] [get_bd_pins controller_m1_pack/adc_rst] [get_bd_pins sys_rstgen/peripheral_reset]
#connect_bd_net -net controller_m1_adc_enable_c0 [get_bd_pins controller_m1/adc_enable_c0] [get_bd_pins controller_m1_pack/adc_enable_0]
#connect_bd_net -net controller_m1_adc_enable_c1 [get_bd_pins controller_m1/adc_enable_c1] [get_bd_pins controller_m1_pack/adc_enable_1]
#connect_bd_net -net controller_m1_adc_enable_c2 [get_bd_pins controller_m1/adc_enable_c2] [get_bd_pins controller_m1_pack/adc_enable_2]
#connect_bd_net -net controller_m1_adc_enable_c3 [get_bd_pins controller_m1/adc_enable_c3] [get_bd_pins controller_m1_pack/adc_enable_3]
#connect_bd_net -net controller_m1_adc_enable_c4 [get_bd_pins controller_m1/adc_enable_c4] [get_bd_pins controller_m1_pack/adc_enable_4]
#connect_bd_net -net controller_m1_adc_enable_c5 [get_bd_pins controller_m1/adc_enable_c5] [get_bd_pins controller_m1_pack/adc_enable_5]
#connect_bd_net -net controller_m1_adc_enable_c6 [get_bd_pins controller_m1/adc_enable_c6] [get_bd_pins controller_m1_pack/adc_enable_6]
#connect_bd_net -net controller_m1_adc_enable_c7 [get_bd_pins controller_m1/adc_enable_c7] [get_bd_pins controller_m1_pack/adc_enable_7]
#connect_bd_net -net controller_m1_adc_valid_c0 [get_bd_pins controller_m1/adc_valid_c0] [get_bd_pins controller_m1_pack/adc_valid_0]
#connect_bd_net -net controller_m1_adc_valid_c1 [get_bd_pins controller_m1/adc_valid_c1] [get_bd_pins controller_m1_pack/adc_valid_1]
#connect_bd_net -net controller_m1_adc_valid_c2 [get_bd_pins controller_m1/adc_valid_c2] [get_bd_pins controller_m1_pack/adc_valid_2]
#connect_bd_net -net controller_m1_adc_valid_c3 [get_bd_pins controller_m1/adc_valid_c3] [get_bd_pins controller_m1_pack/adc_valid_3]
#connect_bd_net -net controller_m1_adc_valid_c4 [get_bd_pins controller_m1/adc_valid_c4] [get_bd_pins controller_m1_pack/adc_valid_4]
#connect_bd_net -net controller_m1_adc_valid_c5 [get_bd_pins controller_m1/adc_valid_c5] [get_bd_pins controller_m1_pack/adc_valid_5]
#connect_bd_net -net controller_m1_adc_valid_c6 [get_bd_pins controller_m1/adc_valid_c6] [get_bd_pins controller_m1_pack/adc_valid_6]
#connect_bd_net -net controller_m1_adc_valid_c7 [get_bd_pins controller_m1/adc_valid_c7] [get_bd_pins controller_m1_pack/adc_valid_7]
#connect_bd_net -net controller_m1_data_c0 [get_bd_pins controller_m1/adc_data_c0] [get_bd_pins controller_m1_pack/adc_data_0]
#connect_bd_net -net controller_m1_data_c1 [get_bd_pins controller_m1/adc_data_c1] [get_bd_pins controller_m1_pack/adc_data_1]
#connect_bd_net -net controller_m1_data_c2 [get_bd_pins controller_m1/adc_data_c2] [get_bd_pins controller_m1_pack/adc_data_2]
#connect_bd_net -net controller_m1_data_c3 [get_bd_pins controller_m1/adc_data_c3] [get_bd_pins controller_m1_pack/adc_data_3]
#connect_bd_net -net controller_m1_data_c4 [get_bd_pins controller_m1/adc_data_c4] [get_bd_pins controller_m1_pack/adc_data_4]
#connect_bd_net -net controller_m1_data_c5 [get_bd_pins controller_m1/adc_data_c5] [get_bd_pins controller_m1_pack/adc_data_5]
#connect_bd_net -net controller_m1_data_c6 [get_bd_pins controller_m1/adc_data_c6] [get_bd_pins controller_m1_pack/adc_data_6]
#connect_bd_net -net controller_m1_data_c7 [get_bd_pins controller_m1/adc_data_c7] [get_bd_pins controller_m1_pack/adc_data_7]
#connect_bd_net [get_bd_pins controller_m1_pack/adc_data] [get_bd_pins controller_m1_dma/fifo_wr_din]
#connect_bd_net [get_bd_pins controller_m1_pack/adc_valid] [get_bd_pins controller_m1_dma/fifo_wr_en]
ad_connect sys_cpu_clk controller_m1_apack/clk
ad_connect controller_m1/adc_enable_c0 controller_m1_apack/chan_enable_0
ad_connect controller_m1/adc_enable_c1 controller_m1_apack/chan_enable_1
ad_connect controller_m1/adc_enable_c2 controller_m1_apack/chan_enable_2
ad_connect controller_m1/adc_enable_c3 controller_m1_apack/chan_enable_3
ad_connect controller_m1/adc_enable_c4 controller_m1_apack/chan_enable_4
ad_connect controller_m1/adc_enable_c5 controller_m1_apack/chan_enable_5
ad_connect controller_m1/adc_enable_c6 controller_m1_apack/chan_enable_6
ad_connect controller_m1/adc_enable_c7 controller_m1_apack/chan_enable_7
ad_connect controller_m1/adc_valid_c0 controller_m1_apack/chan_valid_0
ad_connect controller_m1/adc_valid_c1 controller_m1_apack/chan_valid_1
ad_connect controller_m1/adc_valid_c2 controller_m1_apack/chan_valid_2
ad_connect controller_m1/adc_valid_c3 controller_m1_apack/chan_valid_3
ad_connect controller_m1/adc_valid_c4 controller_m1_apack/chan_valid_4
ad_connect controller_m1/adc_valid_c5 controller_m1_apack/chan_valid_5
ad_connect controller_m1/adc_valid_c6 controller_m1_apack/chan_valid_6
ad_connect controller_m1/adc_valid_c7 controller_m1_apack/chan_valid_7
ad_connect controller_m1/adc_data_c0 controller_m1_apack/chan_data_0
ad_connect controller_m1/adc_data_c1 controller_m1_apack/chan_data_1
ad_connect controller_m1/adc_data_c2 controller_m1_apack/chan_data_2
ad_connect controller_m1/adc_data_c3 controller_m1_apack/chan_data_3
ad_connect controller_m1/adc_data_c4 controller_m1_apack/chan_data_4
ad_connect controller_m1/adc_data_c5 controller_m1_apack/chan_data_5
ad_connect controller_m1/adc_data_c6 controller_m1_apack/chan_data_6
ad_connect controller_m1/adc_data_c7 controller_m1_apack/chan_data_7
ad_connect controller_m1_apack/ddata controller_m1_dma/fifo_wr_din
ad_connect controller_m1_apack/dvalid controller_m1_dma/fifo_wr_en
# motor 2
ad_connect sys_cpu_clk controller_m2/ref_clk
ad_connect controller_m2/ctrl_data_clk sys_audio_clkgen/clk_out5
ad_connect sys_cpu_clk controller_m2_dma/fifo_wr_clk
ad_connect fmc_m2_en_o controller_m2/fmc_en_o
ad_connect pwm_m2_al_o controller_m2/pwm_al_o
ad_connect pwm_m2_ah_o controller_m2/pwm_ah_o
ad_connect pwm_m2_bl_o controller_m2/pwm_bl_o
ad_connect pwm_m2_bh_o controller_m2/pwm_bh_o
ad_connect pwm_m2_cl_o controller_m2/pwm_cl_o
ad_connect pwm_m2_ch_o controller_m2/pwm_ch_o
ad_connect controller_m2/sensors_o speed_detector_m2/hall_bemf_i
ad_connect controller_m2/position_i speed_detector_m2/position_o
ad_connect controller_m2/ctrl_data_valid_i current_monitor_m2/i_ready_o
#connect_bd_net -net controller_m2_adc_clk_o [get_bd_pins controller_m2_pack/adc_clk] [get_bd_pins controller_m2/adc_clk_o]
#connect_bd_net -net [get_bd_nets sys_rstgen_peripheral_reset] [get_bd_pins controller_m2_pack/adc_rst] [get_bd_pins sys_rstgen/peripheral_reset]
#connect_bd_net -net controller_m2_adc_enable_c0 [get_bd_pins controller_m2/adc_enable_c0] [get_bd_pins controller_m2_pack/adc_enable_0]
#connect_bd_net -net controller_m2_adc_enable_c1 [get_bd_pins controller_m2/adc_enable_c1] [get_bd_pins controller_m2_pack/adc_enable_1]
#connect_bd_net -net controller_m2_adc_enable_c2 [get_bd_pins controller_m2/adc_enable_c2] [get_bd_pins controller_m2_pack/adc_enable_2]
#connect_bd_net -net controller_m2_adc_enable_c3 [get_bd_pins controller_m2/adc_enable_c3] [get_bd_pins controller_m2_pack/adc_enable_3]
#connect_bd_net -net controller_m2_adc_enable_c4 [get_bd_pins controller_m2/adc_enable_c4] [get_bd_pins controller_m2_pack/adc_enable_4]
#connect_bd_net -net controller_m2_adc_enable_c5 [get_bd_pins controller_m2/adc_enable_c5] [get_bd_pins controller_m2_pack/adc_enable_5]
#connect_bd_net -net controller_m2_adc_enable_c6 [get_bd_pins controller_m2/adc_enable_c6] [get_bd_pins controller_m2_pack/adc_enable_6]
#connect_bd_net -net controller_m2_adc_enable_c7 [get_bd_pins controller_m2/adc_enable_c7] [get_bd_pins controller_m2_pack/adc_enable_7]
#connect_bd_net -net controller_m2_adc_valid_c0 [get_bd_pins controller_m2/adc_valid_c0] [get_bd_pins controller_m2_pack/adc_valid_0]
#connect_bd_net -net controller_m2_adc_valid_c1 [get_bd_pins controller_m2/adc_valid_c1] [get_bd_pins controller_m2_pack/adc_valid_1]
#connect_bd_net -net controller_m2_adc_valid_c2 [get_bd_pins controller_m2/adc_valid_c2] [get_bd_pins controller_m2_pack/adc_valid_2]
#connect_bd_net -net controller_m2_adc_valid_c3 [get_bd_pins controller_m2/adc_valid_c3] [get_bd_pins controller_m2_pack/adc_valid_3]
#connect_bd_net -net controller_m2_adc_valid_c4 [get_bd_pins controller_m2/adc_valid_c4] [get_bd_pins controller_m2_pack/adc_valid_4]
#connect_bd_net -net controller_m2_adc_valid_c5 [get_bd_pins controller_m2/adc_valid_c5] [get_bd_pins controller_m2_pack/adc_valid_5]
#connect_bd_net -net controller_m2_adc_valid_c6 [get_bd_pins controller_m2/adc_valid_c6] [get_bd_pins controller_m2_pack/adc_valid_6]
#connect_bd_net -net controller_m2_adc_valid_c7 [get_bd_pins controller_m2/adc_valid_c7] [get_bd_pins controller_m2_pack/adc_valid_7]
#connect_bd_net -net controller_m2_data_c0 [get_bd_pins controller_m2/adc_data_c0] [get_bd_pins controller_m2_pack/adc_data_0]
#connect_bd_net -net controller_m2_data_c1 [get_bd_pins controller_m2/adc_data_c1] [get_bd_pins controller_m2_pack/adc_data_1]
#connect_bd_net -net controller_m2_data_c2 [get_bd_pins controller_m2/adc_data_c2] [get_bd_pins controller_m2_pack/adc_data_2]
#connect_bd_net -net controller_m2_data_c3 [get_bd_pins controller_m2/adc_data_c3] [get_bd_pins controller_m2_pack/adc_data_3]
#connect_bd_net -net controller_m2_data_c4 [get_bd_pins controller_m2/adc_data_c4] [get_bd_pins controller_m2_pack/adc_data_4]
#connect_bd_net -net controller_m2_data_c5 [get_bd_pins controller_m2/adc_data_c5] [get_bd_pins controller_m2_pack/adc_data_5]
#connect_bd_net -net controller_m2_data_c6 [get_bd_pins controller_m2/adc_data_c6] [get_bd_pins controller_m2_pack/adc_data_6]
#connect_bd_net -net controller_m2_data_c7 [get_bd_pins controller_m2/adc_data_c7] [get_bd_pins controller_m2_pack/adc_data_7]
#connect_bd_net [get_bd_pins controller_m2_pack/adc_data] [get_bd_pins controller_m2_dma/fifo_wr_din]
#connect_bd_net [get_bd_pins controller_m2_pack/adc_valid] [get_bd_pins controller_m2_dma/fifo_wr_en]
ad_connect sys_cpu_clk controller_m2_apack/clk
ad_connect controller_m2/adc_enable_c0 controller_m2_apack/chan_enable_0
ad_connect controller_m2/adc_enable_c1 controller_m2_apack/chan_enable_1
ad_connect controller_m2/adc_enable_c2 controller_m2_apack/chan_enable_2
ad_connect controller_m2/adc_enable_c3 controller_m2_apack/chan_enable_3
ad_connect controller_m2/adc_enable_c4 controller_m2_apack/chan_enable_4
ad_connect controller_m2/adc_enable_c5 controller_m2_apack/chan_enable_5
ad_connect controller_m2/adc_enable_c6 controller_m2_apack/chan_enable_6
ad_connect controller_m2/adc_enable_c7 controller_m2_apack/chan_enable_7
ad_connect controller_m2/adc_valid_c0 controller_m2_apack/chan_valid_0
ad_connect controller_m2/adc_valid_c1 controller_m2_apack/chan_valid_1
ad_connect controller_m2/adc_valid_c2 controller_m2_apack/chan_valid_2
ad_connect controller_m2/adc_valid_c3 controller_m2_apack/chan_valid_3
ad_connect controller_m2/adc_valid_c4 controller_m2_apack/chan_valid_4
ad_connect controller_m2/adc_valid_c5 controller_m2_apack/chan_valid_5
ad_connect controller_m2/adc_valid_c6 controller_m2_apack/chan_valid_6
ad_connect controller_m2/adc_valid_c7 controller_m2_apack/chan_valid_7
ad_connect controller_m2/adc_data_c0 controller_m2_apack/chan_data_0
ad_connect controller_m2/adc_data_c1 controller_m2_apack/chan_data_1
ad_connect controller_m2/adc_data_c2 controller_m2_apack/chan_data_2
ad_connect controller_m2/adc_data_c3 controller_m2_apack/chan_data_3
ad_connect controller_m2/adc_data_c4 controller_m2_apack/chan_data_4
ad_connect controller_m2/adc_data_c5 controller_m2_apack/chan_data_5
ad_connect controller_m2/adc_data_c6 controller_m2_apack/chan_data_6
ad_connect controller_m2/adc_data_c7 controller_m2_apack/chan_data_7
ad_connect controller_m2_apack/ddata controller_m2_dma/fifo_wr_din
ad_connect controller_m2_apack/dvalid controller_m2_dma/fifo_wr_en
# ethernet
# connect_bd_net -net speed_detector_adc_clk [get_bd_pins axi_mc_speed_1/adc_clk_o] [get_bd_pins axi_speed_detector_dma/fifo_wr_clk]
# connect_bd_net -net speed_detector_adc_dwr [get_bd_pins axi_mc_speed_1/adc_dwr_o] [get_bd_pins axi_speed_detector_dma/fifo_wr_en]
# connect_bd_net -net speed_detector_adc_ddata [get_bd_pins axi_mc_speed_1/adc_ddata_o] [get_bd_pins axi_speed_detector_dma/fifo_wr_din]
# connect_bd_net -net speed_detector_adc_dovf [get_bd_pins axi_mc_speed_1/adc_dovf_i] [get_bd_pins axi_speed_detector_dma/fifo_wr_overflow]
ad_connect sys_200m_clk refclk
ad_connect sys_cpu_resetn refclk_rst
ad_connect sys_cpu_resetn eth_phy_rst_n
ad_connect sys_ps7/ENET0_MDIO_MDC eth_mdio_mdc
ad_connect sys_ps7/ENET0_MDIO_O eth_mdio_o
ad_connect sys_ps7/ENET0_MDIO_T eth_mdio_t
ad_connect sys_ps7/ENET0_MDIO_I eth_mdio_i
# phy 1
ad_connect gmii_to_rgmii_eth1/gmii sys_ps7/GMII_ETHERNET_0
ad_connect eth1_rgmii gmii_to_rgmii_eth1/rgmii
ad_connect gmii_to_rgmii_eth1/reset sys_rstgen/peripheral_reset
# interrupt
ad_connect gmii_to_rgmii_eth1/clk_20m sys_audio_clkgen/clk_out4
ad_connect gmii_to_rgmii_eth1/clk_25m sys_audio_clkgen/clk_out3
ad_connect gmii_to_rgmii_eth1/clk_125m sys_audio_clkgen/clk_out2
ad_connect eth_mdio_mdc gmii_to_rgmii_eth1/mdio_mdc
ad_connect eth_mdio_o gmii_to_rgmii_eth1/mdio_in_w
ad_connect eth_mdio_i gmii_to_rgmii_eth1/mdio_in_r
# phy 2
ad_connect gmii_to_rgmii_eth2/gmii sys_ps7/GMII_ETHERNET_1
ad_connect eth2_rgmii gmii_to_rgmii_eth2/rgmii
ad_connect gmii_to_rgmii_eth2/reset sys_rstgen/peripheral_reset
ad_connect gmii_to_rgmii_eth2/clk_20m sys_audio_clkgen/clk_out4
ad_connect gmii_to_rgmii_eth2/clk_25m sys_audio_clkgen/clk_out3
ad_connect gmii_to_rgmii_eth2/clk_125m sys_audio_clkgen/clk_out2
# connect_bd_net -net axi_speed_detector_dma_irq [get_bd_pins axi_speed_detector_dma/irq] [get_bd_ports motcon2_s_d_irq]
ad_connect eth_mdio_mdc gmii_to_rgmii_eth2/mdio_mdc
ad_connect eth_mdio_o gmii_to_rgmii_eth2/mdio_in_w
ad_connect eth_mdio_i gmii_to_rgmii_eth2/mdio_in_r
# xadc
ad_connect xadc_core/Vaux0 vaux0
ad_connect xadc_core/Vaux8 vaux8
#connect_bd_net -net xadc_muxout [get_bd_pins /xadc_core/muxaddr_out] [get_bd_ports muxaddr_out]
connect_bd_net -net sys_100m_clk [get_bd_pins xadc_wiz_1/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins xadc_wiz_1/s_axi_aresetn] $sys_100m_resetn_source
# iic
ad_connect iic_ee2/IIC iic_ee2
connect_bd_intf_net -intf_net Vp_Vn_1 [get_bd_intf_pins xadc_wiz_1/Vp_Vn] [get_bd_intf_ports Vp_Vn]
connect_bd_intf_net -intf_net Vaux0_1 [get_bd_intf_pins xadc_wiz_1/Vaux0] [get_bd_intf_ports Vaux0]
connect_bd_intf_net -intf_net Vaux8_1 [get_bd_intf_pins xadc_wiz_1/Vaux8] [get_bd_intf_ports Vaux8]
#ethernet
connect_bd_intf_net -intf_net gmii_to_rgmii_eth2_eth2_mdio [get_bd_intf_ports eth2_mdio] [get_bd_intf_pins gmii_to_rgmii_eth2/MDIO_PHY]
connect_bd_intf_net -intf_net gmii_to_rgmii_eth2_eth2_rgmii [get_bd_intf_ports eth2_rgmii] [get_bd_intf_pins gmii_to_rgmii_eth2/RGMII]
connect_bd_intf_net -intf_net sys_ps7_GMII_ETHERNET_1 [get_bd_intf_pins gmii_to_rgmii_eth2/GMII] [get_bd_intf_pins sys_ps7/GMII_ETHERNET_1]
connect_bd_intf_net -intf_net sys_ps7_MDIO_ETHERNET_1 [get_bd_intf_pins gmii_to_rgmii_eth2/MDIO_GEM] [get_bd_intf_pins sys_ps7/MDIO_ETHERNET_1]
connect_bd_net -net sys_200m_clk [get_bd_pins gmii_to_rgmii_eth2/clkin] $sys_200m_clk_source
connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_pins gmii_to_rgmii_eth2/rx_reset] [get_bd_pins gmii_to_rgmii_eth2/tx_reset] [get_bd_pins sys_rstgen/peripheral_reset]
connect_bd_net -net [get_bd_nets sys_100m_resetn] [get_bd_ports eth2_phy_rst_n] [get_bd_pins sys_rstgen/peripheral_aresetn]
# interconnect (cpu)
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_mc_current_monitor_1/s_axi]
# connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_mc_speed_1/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_current_monitor_2_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_mc_current_monitor_2/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_current_monitor_1_dma/s_axi]
# connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_speed_detector_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins xadc_wiz_1/s_axi_lite]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source
#inteconnects (current monitor 1)
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_current_monitor_1/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mc_current_monitor_1/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_current_monitor_1_dma/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_current_monitor_1_dma/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_current_monitor_1_dma/m_dest_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_current_monitor_1_dma/m_dest_axi_aresetn] $sys_100m_resetn_source
connect_bd_intf_net -intf_net axi_current_monitor_1_dma [get_bd_intf_pins axi_current_monitor_1_dma/m_dest_axi] [get_bd_intf_pins sys_ps7/S_AXI_HP1]
#interconnect (current monitor 2)
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_current_monitor_2/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mc_current_monitor_2/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_current_monitor_2_dma/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_current_monitor_2_dma/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_current_monitor_2_dma/m_dest_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_current_monitor_2_dma/m_dest_axi_aresetn] $sys_100m_resetn_source
connect_bd_intf_net -intf_net axi_current_monitor_2_dma [get_bd_intf_pins axi_current_monitor_2_dma/m_dest_axi] [get_bd_intf_pins sys_ps7/S_AXI_HP2]
# interconnect (speed detector)
# connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_speed_1/s_axi_aclk] $sys_100m_clk_source
# connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mc_speed_1/s_axi_aresetn] $sys_100m_resetn_source
# connect_bd_net -net sys_100m_clk [get_bd_pins axi_speed_detector_dma/m_dest_axi_aclk] $sys_100m_clk_source
# connect_bd_net -net sys_100m_resetn [get_bd_pins axi_speed_detector_dma/s_axi_aresetn] $sys_100m_resetn_source
# connect_bd_net -net sys_100m_clk [get_bd_pins axi_speed_detector_dma/s_axi_aclk] $sys_100m_clk_source
# connect_bd_net -net sys_100m_resetn [get_bd_pins axi_speed_detector_dma/m_dest_axi_aresetn] $sys_100m_resetn_source
# connect_bd_intf_net -intf_net axi_speed_detector_dma [get_bd_intf_pins axi_speed_detector_dma/m_dest_axi] [get_bd_intf_pins sys_ps7/S_AXI_HP3]
# interconnect (dmas)
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK] $sys_100m_clk_source
ad_connect sys_cpu_resetn speed_detector_m1_dma/m_dest_axi_aresetn
ad_connect sys_cpu_resetn speed_detector_m2_dma/m_dest_axi_aresetn
ad_connect sys_cpu_resetn current_monitor_m1_dma/m_dest_axi_aresetn
ad_connect sys_cpu_resetn current_monitor_m2_dma/m_dest_axi_aresetn
ad_connect sys_cpu_resetn controller_m1_dma/m_dest_axi_aresetn
ad_connect sys_cpu_resetn controller_m2_dma/m_dest_axi_aresetn
# address map
ad_cpu_interconnect 0x40410000 speed_detector_m1
ad_cpu_interconnect 0x40420000 current_monitor_m1
ad_cpu_interconnect 0x40430000 controller_m1
ad_cpu_interconnect 0x40440000 speed_detector_m2
ad_cpu_interconnect 0x40450000 current_monitor_m2
ad_cpu_interconnect 0x40460000 controller_m2
ad_cpu_interconnect 0x40510000 speed_detector_m1_dma
ad_cpu_interconnect 0x40520000 current_monitor_m1_dma
ad_cpu_interconnect 0x40530000 controller_m1_dma
ad_cpu_interconnect 0x40540000 speed_detector_m2_dma
ad_cpu_interconnect 0x40550000 current_monitor_m2_dma
ad_cpu_interconnect 0x40560000 controller_m2_dma
ad_cpu_interconnect 0x43200000 xadc_core
ad_cpu_interconnect 0x41510000 iic_ee2
create_bd_addr_seg -range 0x10000 -offset 0x40400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_current_monitor_1_dma/s_axi/axi_lite] SEG_data_c_m_1_dma
# create_bd_addr_seg -range 0x10000 -offset 0x40410000 $sys_addr_cntrl_space [get_bd_addr_segs axi_speed_detector_dma/s_axi/axi_lite] SEG_data_s_d_dma
create_bd_addr_seg -range 0x10000 -offset 0x40430000 $sys_addr_cntrl_space [get_bd_addr_segs axi_current_monitor_2_dma/s_axi/axi_lite] SEG_data_c_m_2_dma
create_bd_addr_seg -range 0x10000 -offset 0x40500000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_current_monitor_1/s_axi/axi_lite] SEG_data_c_m_1
# create_bd_addr_seg -range 0x10000 -offset 0x40510000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_speed_1/s_axi/axi_lite] SEG_data_s_d
create_bd_addr_seg -range 0x10000 -offset 0x40530000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_current_monitor_2/s_axi/axi_lite] SEG_data_c_m_2
create_bd_addr_seg -range 0x10000 -offset 0x43200000 $sys_addr_cntrl_space [get_bd_addr_segs xadc_wiz_1/s_axi_lite/Reg] SEG_data_xadc
ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_cpu_clk speed_detector_m1_dma/m_dest_axi
ad_mem_hp1_interconnect sys_cpu_clk speed_detector_m2_dma/m_dest_axi
ad_mem_hp1_interconnect sys_cpu_clk current_monitor_m1_dma/m_dest_axi
ad_mem_hp1_interconnect sys_cpu_clk current_monitor_m2_dma/m_dest_axi
ad_mem_hp1_interconnect sys_cpu_clk controller_m1_dma/m_dest_axi
ad_mem_hp1_interconnect sys_cpu_clk controller_m2_dma/m_dest_axi
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_current_monitor_1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_current_monitor_2_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm
# create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_speed_detector_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm
ad_cpu_interrupt ps-6 mb-6 controller_m2_dma/irq
ad_cpu_interrupt ps-7 mb-7 current_monitor_m2_dma/irq
ad_cpu_interrupt ps-8 mb-8 speed_detector_m2_dma/irq
ad_cpu_interrupt ps-9 mb-9 controller_m1_dma/irq
ad_cpu_interrupt ps-10 mb-10 current_monitor_m1_dma/irq
ad_cpu_interrupt ps-12 mb-12 iic_ee2/iic2intc_irpt
ad_cpu_interrupt ps-13 mb-13 speed_detector_m1_dma/irq

200
projects/motcon2_fmc/zed/system_constr.xdc Normal file → Executable file
View File

@ -1,92 +1,156 @@
# Motor Control
#set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports gpio_bd[27]] ; ## XADC-GIO0
#set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[28]] ; ## XADC-GIO1
#set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[29]] ; ## XADC-GIO2
#set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS33} [get_ports gpio_bd[30]] ; ## XADC-GIO3
set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS25 } [get_ports {position_m1_i[0]}]
set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS25 } [get_ports {position_m1_i[1]}]
set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS25 } [get_ports {position_m1_i[2]}]
set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS25} [get_ports {position_i[0]}]
set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS25} [get_ports {position_i[1]}]
set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS25} [get_ports {position_i[2]}]
set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS25} [get_ports {position_m2_i[0]}] ; #M2_SENSOR_A
set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS25} [get_ports {position_m2_i[1]}] ; #M2_SENSOR_B
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS25} [get_ports {position_m2_i[2]}] ; #M2_SENSOR_C
#set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS25} [get_ports {position_m2_i[0]}] ;#M2_SENSOR_A
#set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS25} [get_ports {position_m2_i[1]}] ;#M2_SENSOR_B
#set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS25} [get_ports {position_m2_i[2]}] ;#M2_SENSOR_C
set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS25} [get_ports vt_enable]
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports fmc_m1_en_o]
#set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports pwm_m1_ah_o]
#set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS25} [get_ports pwm_m1_al_o]
#set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports pwm_m1_bh_o]
#set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports pwm_m1_bl_o]
#set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports pwm_m1_ch_o]
#set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports pwm_m1_cl_o]
#set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports pwm_m1_dh_o]
#set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports pwm_m1_dl_o]
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports pwm_m1_ah_o]
set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS25} [get_ports pwm_m1_al_o]
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports pwm_m1_bh_o]
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports pwm_m1_bl_o]
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports pwm_m1_ch_o]
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports pwm_m1_cl_o]
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports pwm_m1_dh_o]
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports pwm_m1_dl_o]
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports fmc_m2_en_o]
#set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS25} [get_ports pwm_m2_ah_o]
#set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS25} [get_ports pwm_m2_al_o]
#set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS25} [get_ports pwm_m2_bh_o]
#set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS25} [get_ports pwm_m2_bl_o]
#set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports pwm_m2_ch_o]
#set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports pwm_m2_cl_o]
#set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25} [get_ports pwm_m2_dh_o]
#set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS25} [get_ports pwm_m2_dl_o]
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS25} [get_ports pwm_m2_ah_o]
set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS25} [get_ports pwm_m2_al_o]
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS25} [get_ports pwm_m2_bh_o]
set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS25} [get_ports pwm_m2_bl_o]
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports pwm_m2_ch_o]
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports pwm_m2_cl_o]
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25} [get_ports pwm_m2_dh_o]
set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS25} [get_ports pwm_m2_dl_o]
set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25 } [get_ports adc_clk_o]
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25 } [get_ports adc_m1_vbus_dat_i]
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25 } [get_ports adc_m2_vbus_dat_i]
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25 } [get_ports adc_m1_ia_dat_i]
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25 } [get_ports adc_m1_ib_dat_i]
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS25 } [get_ports adc_m2_ia_dat_i]
set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS25 } [get_ports adc_m2_ib_dat_i]
set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports adc_clk_o]
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports adc_m1_vbus_dat_i]
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25} [get_ports adc_m2_vbus_dat_i]
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports adc_m1_ia_dat_i]
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports adc_m1_ib_dat_i]
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS25} [get_ports adc_m2_ia_dat_i]
set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS25} [get_ports adc_m2_ib_dat_i]
# GPO
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25 } [get_ports {gpo[0]}]
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS25 } [get_ports {gpo[1]}]
set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS25 } [get_ports {gpo[2]}]
set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS25 } [get_ports {gpo[3]}]
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25} [get_ports {gpo_o[0]}]
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS25} [get_ports {gpo_o[1]}]
set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS25} [get_ports {gpo_o[2]}]
set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS25} [get_ports {gpo_o[3]}]
#set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS25} [get_ports {gpi_i[0]}]
#set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS25} [get_ports {gpi_i[1]}]
#set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[0]}]
#set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[1]}]
#set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[2]}]
#set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[3]}]
# GPI
set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS25} [get_ports {gpi[0]}]
set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS25} [get_ports {gpi[1]}]
set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS25} [get_ports vauxn0]
set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS25} [get_ports vauxn8]
set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS25} [get_ports vauxp0]
set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS25} [get_ports vauxp8]
set_property -dict {PACKAGE_PIN M12 IOSTANDARD LVCMOS25} [get_ports vn_in]
set_property -dict {PACKAGE_PIN L11 IOSTANDARD LVCMOS25} [get_ports vp_in]
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25} [get_ports eth2_mdio_mdc]
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports eth2_mdio_io]
set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS25} [get_ports eth2_phy_rst_n]
# SPI
set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS25} [get_ports fmc_spi1_sel1_rdc ]
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports fmc_spi1_miso ]
set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS25} [get_ports fmc_spi1_mosi ]
set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS25} [get_ports fmc_spi1_sck ]
#FMC_SAMPLE_N
set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS25} [get_ports fmc_sample_n]
# IIC
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_ee2_scl_io]
set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_ee2_sda_io]
# Ethernet common
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25} [get_ports eth_mdio_mdc]
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25 PULLUP true} [get_ports eth_mdio_io]
set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS25} [get_ports eth_phy_rst_n]
# Ethernet 1
set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_rxc]
set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_rx_ctl]
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[0]}]
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[1]}]
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[2]}]
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[3]}]
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports eth1_rgmii_txc]
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports eth1_rgmii_tx_ctl]
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth1_rgmii_td[0]}]
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth1_rgmii_td[1]}]
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth1_rgmii_td[2]}]
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth1_rgmii_td[3]}]
# Ethernet 2
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_rxc]
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_rx_ctl]
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[0]}]
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[1]}]
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[2]}]
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[3]}]
set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_txc]
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_tx_ctl]
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[0]}]
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[1]}]
set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[2]}]
set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[3]}]
set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports eth2_rgmii_txc]
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports eth2_rgmii_tx_ctl]
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[0]}]
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[1]}]
set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[2]}]
set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[3]}]
#set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_rxc]
#set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_rx_ctl]
#set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[0]}]
#set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[1]}]
#set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[2]}]
#set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[3]}]
#set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_txc]
#set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_tx_ctl]
#set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[0]}]
#set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[1]}]
#set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[2]}]
#set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[3]}]
#create clocks
# Clock Period Constraints
create_clock -name mdio_mdc -period 400 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/EMIOENET0MDIOMDC]
create_clock -period 8.000 -name rgmii_rxc1 [get_ports eth1_rgmii_rxc]
create_clock -period 8.000 -name rgmii_rxc2 [get_ports eth2_rgmii_rxc]
create_generated_clock -name pwm_ctrl_1 -source [get_pins i_system_wrapper/system_i/controller_m1/inst/ref_clk] \
-divide_by 2 [get_pins i_system_wrapper/system_i/controller_m1/inst/pwm_gen_clk_reg/Q]
create_generated_clock -name pwm_ctrl_2 -source [get_pins i_system_wrapper/system_i/controller_m2/inst/ref_clk] \
-divide_by 2 [get_pins i_system_wrapper/system_i/controller_m2/inst/pwm_gen_clk_reg/Q]
create_generated_clock -name cm1_ia -source [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/adc_clk_i] \
-divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/ia_if/filter/word_count_reg[7]/Q]
create_generated_clock -name cm1_ib -source [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/adc_clk_i] \
-divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/ib_if/filter/word_count_reg[7]/Q]
create_generated_clock -name cm1_vbus -source [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/adc_clk_i] \
-divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/vbus_if/filter/word_count_reg[7]/Q]
create_generated_clock -name cm2_ia -source [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/adc_clk_i] \
-divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/ia_if/filter/word_count_reg[7]/Q]
create_generated_clock -name cm2_ib -source [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/adc_clk_i] \
-divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/ib_if/filter/word_count_reg[7]/Q]
create_generated_clock -name cm2_vbus -source [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/adc_clk_i] \
-divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/vbus_if/filter/word_count_reg[7]/Q]
set_clock_groups -asynchronous \
-group [get_clocks {cm1_ia cm1_ib cm1_vbus }]
set_clock_groups -asynchronous \
-group [get_clocks {cm2_ia cm2_ib cm2_vbus }]
set_clock_groups -asynchronous \
-group [get_clocks {pwm_ctrl_1 }] \
-group [get_clocks {pwm_ctrl_2 }]
# Ethernet common
set_property IODELAY_GROUP eth_idelay_grp [get_cells dlyctrl]
# Ethernet 1
#IDELAY
set_property IDELAY_VALUE 16 [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl]
set_property IDELAY_VALUE 16 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth1*/*delay_rgmii_rd*}]
set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl]
set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth1*/*delay_rgmii_rd*}]
# Ethernet 2
#IDELAY
set_property IDELAY_VALUE 16 [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl]
set_property IDELAY_VALUE 16 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth2*/*delay_rgmii_rd*}]
set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl]
set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth2*/*delay_rgmii_rd*}]

1
projects/motcon2_fmc/zed/system_project.tcl
View File

@ -1,6 +1,7 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_create motcon2_fmc_zed
adi_project_files motcon2_fmc_zed [list \

427
projects/motcon2_fmc/zed/system_top.v
View File

@ -41,21 +41,28 @@
module system_top (
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
eth1_rgmii_rd,
eth1_rgmii_rx_ctl,
eth1_rgmii_rxc,
eth1_rgmii_td,
eth1_rgmii_tx_ctl,
eth1_rgmii_txc,
eth2_rgmii_rd,
eth2_rgmii_rx_ctl,
@ -63,16 +70,17 @@ module system_top (
eth2_rgmii_td,
eth2_rgmii_tx_ctl,
eth2_rgmii_txc,
eth2_mdio_io,
eth2_mdio_mdc,
eth2_phy_rst_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
eth_mdio_io,
eth_mdio_mdc,
eth_phy_rst_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
@ -82,6 +90,8 @@ module system_top (
hdmi_data_e,
hdmi_data,
position_m1_i,
position_m2_i,
adc_clk_o,
adc_m1_ia_dat_i,
adc_m1_ib_dat_i,
@ -91,22 +101,28 @@ module system_top (
adc_m2_ia_dat_i,
adc_m2_ib_dat_i,
adc_m2_vbus_dat_i,
gpo_o,
position_i,
/*pwm_ah_o,
pwm_al_o,
pwm_bh_o,
pwm_bl_o,
pwm_ch_o,
pwm_cl_o,*/
pwm_m1_ah_o,
pwm_m1_al_o,
pwm_m1_bh_o,
pwm_m1_bl_o,
pwm_m1_ch_o,
pwm_m1_cl_o,
pwm_m1_dh_o,
pwm_m1_dl_o,
pwm_m2_ah_o,
pwm_m2_al_o,
pwm_m2_bh_o,
pwm_m2_bl_o,
pwm_m2_ch_o,
pwm_m2_cl_o,
pwm_m2_dh_o,
pwm_m2_dl_o,
vt_enable,
vauxn0,
vauxn8,
vauxp0,
vauxp8,
vn_in,
vp_in,
//muxaddr_out,
/* muxaddr_out,*/
i2s_mclk,
i2s_bclk,
@ -121,23 +137,41 @@ module system_top (
iic_mux_scl,
iic_mux_sda,
iic_ee2_scl_io,
iic_ee2_sda_io,
fmc_spi1_sel1_rdc,
fmc_spi1_miso,
fmc_spi1_mosi,
fmc_spi1_sck,
fmc_sample_n,
gpo,
gpi,
otg_vbusoc);
inout [14:0] DDR_addr;
inout [ 2:0] DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [ 3:0] DDR_dm;
inout [31:0] DDR_dq;
inout [ 3:0] DDR_dqs_n;
inout [ 3:0] DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
input [3:0] eth1_rgmii_rd;
input eth1_rgmii_rx_ctl;
input eth1_rgmii_rxc;
output [3:0] eth1_rgmii_td;
output eth1_rgmii_tx_ctl;
output eth1_rgmii_txc;
input [3:0] eth2_rgmii_rd;
input eth2_rgmii_rx_ctl;
@ -145,16 +179,17 @@ module system_top (
output [3:0] eth2_rgmii_td;
output eth2_rgmii_tx_ctl;
output eth2_rgmii_txc;
inout eth2_mdio_io;
output eth2_mdio_mdc;
output eth2_phy_rst_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0] FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout eth_mdio_io;
output eth_mdio_mdc;
output eth_phy_rst_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [31:0] gpio_bd;
@ -164,6 +199,8 @@ module system_top (
output hdmi_data_e;
output [15:0] hdmi_data;
input [2:0] position_m1_i;
input [2:0] position_m2_i;
output adc_clk_o;
output fmc_m1_en_o;
input adc_m1_ia_dat_i;
@ -173,22 +210,30 @@ module system_top (
input adc_m2_ia_dat_i;
input adc_m2_ib_dat_i;
input adc_m2_vbus_dat_i;
output [3:0] gpo_o;
input [2:0] position_i;
/* output pwm_ah_o;
output pwm_al_o;
output pwm_bh_o;
output pwm_bl_o;
output pwm_ch_o;
output pwm_cl_o;*/
output pwm_m1_ah_o;
output pwm_m1_al_o;
output pwm_m1_bh_o;
output pwm_m1_bl_o;
output pwm_m1_ch_o;
output pwm_m1_cl_o;
output pwm_m1_dh_o;
output pwm_m1_dl_o;
output pwm_m2_ah_o;
output pwm_m2_al_o;
output pwm_m2_bh_o;
output pwm_m2_bl_o;
output pwm_m2_ch_o;
output pwm_m2_cl_o;
output pwm_m2_dh_o;
output pwm_m2_dl_o;
output vt_enable;
input vauxn0;
input vauxn8;
input vauxp0;
input vauxp8;
input vn_in;
input vp_in;
//output [3:0] muxaddr_out;
/* output [ 3:0] muxaddr_out;*/
output spdif;
@ -198,35 +243,63 @@ module system_top (
output i2s_sdata_out;
input i2s_sdata_in;
inout iic_scl;
inout iic_sda;
inout [ 1:0] iic_mux_scl;
inout [ 1:0] iic_mux_sda;
inout iic_ee2_scl_io;
inout iic_ee2_sda_io;
output fmc_spi1_sel1_rdc;
input fmc_spi1_miso;
output fmc_spi1_mosi;
output fmc_spi1_sck;
output fmc_sample_n;
output [ 3:0] gpo;
input [ 1:0] gpi;
input otg_vbusoc;
// internal signals
wire [31:0] gpio_i;
wire [31:0] gpio_o;
wire [31:0] gpio_t;
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
wire [15:0] ps_intrs;
wire refclk;
wire refclk_rst;
wire eth_mdio_o;
wire eth_mdio_i;
wire eth_mdio_t;
reg idelayctrl_reset;
reg [ 3:0] idelay_reset_cnt;
// assignments
assign fmc_sample_n = gpio_o[32];
assign gpio_i[34:33] = gpi[1:0];
assign vt_enable = 1'b1;
assign pwm_m1_dh_o = 1'b0;
assign pwm_m1_dl_o = 1'b0;
assign pwm_m2_dh_o = 1'b0;
assign pwm_m2_dl_o = 1'b0;
// instantiations
ad_iobuf #(
.DATA_WIDTH(32))
i_gpio_bd (
.dt(gpio_t),
.di(gpio_o),
.do(gpio_i),
.dt(gpio_t[31:0]),
.di(gpio_o[31:0]),
.do(gpio_i[31:0]),
.dio(gpio_bd));
ad_iobuf #(
@ -245,31 +318,80 @@ module system_top (
.do(iic_mux_sda_i_s),
.dio(iic_mux_sda));
ad_iobuf #(
.DATA_WIDTH(1))
i_mdio_io (
.dt(eth_mdio_t),
.di(eth_mdio_o),
.do(eth_mdio_i),
.dio(eth_mdio_io));
always @(posedge refclk) begin
if (refclk_rst == 1'b1) begin
idelay_reset_cnt <= 4'h0;
idelayctrl_reset <= 1'b1;
end else begin
idelayctrl_reset <= 1'b1;
case (idelay_reset_cnt)
4'h0: idelay_reset_cnt <= 4'h1;
4'h1: idelay_reset_cnt <= 4'h2;
4'h2: idelay_reset_cnt <= 4'h3;
4'h3: idelay_reset_cnt <= 4'h4;
4'h4: idelay_reset_cnt <= 4'h5;
4'h5: idelay_reset_cnt <= 4'h6;
4'h6: idelay_reset_cnt <= 4'h7;
4'h7: idelay_reset_cnt <= 4'h8;
4'h8: idelay_reset_cnt <= 4'h9;
4'h9: idelay_reset_cnt <= 4'ha;
4'ha: idelay_reset_cnt <= 4'hb;
4'hb: idelay_reset_cnt <= 4'hc;
4'hc: idelay_reset_cnt <= 4'hd;
4'hd: idelay_reset_cnt <= 4'he;
default: begin
idelay_reset_cnt <= 4'he;
idelayctrl_reset <= 1'b0;
end
endcase
end
end
IDELAYCTRL dlyctrl (
.RDY(),
.REFCLK(refclk),
.RST(idelayctrl_reset));
system_wrapper i_system_wrapper (
.DDR_addr (DDR_addr),
.DDR_ba (DDR_ba),
.DDR_cas_n (DDR_cas_n),
.DDR_ck_n (DDR_ck_n),
.DDR_ck_p (DDR_ck_p),
.DDR_cke (DDR_cke),
.DDR_cs_n (DDR_cs_n),
.DDR_dm (DDR_dm),
.DDR_dq (DDR_dq),
.DDR_dqs_n (DDR_dqs_n),
.DDR_dqs_p (DDR_dqs_p),
.DDR_odt (DDR_odt),
.DDR_ras_n (DDR_ras_n),
.DDR_reset_n (DDR_reset_n),
.DDR_we_n (DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.GPIO_I (gpio_i),
.GPIO_O (gpio_o),
.GPIO_T (gpio_t),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.eth1_rgmii_rd(eth1_rgmii_rd),
.eth1_rgmii_rx_ctl(eth1_rgmii_rx_ctl),
.eth1_rgmii_rxc(eth1_rgmii_rxc),
.eth1_rgmii_td(eth1_rgmii_td),
.eth1_rgmii_tx_ctl(eth1_rgmii_tx_ctl),
.eth1_rgmii_txc(eth1_rgmii_txc),
.eth2_rgmii_rd(eth2_rgmii_rd),
.eth2_rgmii_rx_ctl(eth2_rgmii_rx_ctl),
@ -277,15 +399,20 @@ module system_top (
.eth2_rgmii_td(eth2_rgmii_td),
.eth2_rgmii_tx_ctl(eth2_rgmii_tx_ctl),
.eth2_rgmii_txc(eth2_rgmii_txc),
.eth2_phy_rst_n(eth2_phy_rst_n),
.eth2_mdio_mdio_io(eth2_mdio_io),
.eth2_mdio_mdc(eth2_mdio_mdc),
.eth_phy_rst_n(eth_phy_rst_n),
.eth_mdio_o(eth_mdio_o),
.eth_mdio_t(eth_mdio_t),
.eth_mdio_i(eth_mdio_i),
.eth_mdio_mdc(eth_mdio_mdc),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.position_m1_i(position_m1_i),
.position_m2_i(position_m2_i),
.adc_clk_o(adc_clk_o),
.fmc_m1_en_o(fmc_m1_en_o),
.adc_m1_ia_dat_i(adc_m1_ia_dat_i),
@ -295,21 +422,24 @@ module system_top (
.adc_m2_ia_dat_i(adc_m2_ia_dat_i),
.adc_m2_ib_dat_i(adc_m2_ib_dat_i),
.adc_m2_vbus_dat_i(adc_m2_vbus_dat_i),
.gpo_o(gpo_o),
.position_i(position_i),
//.pwm_ah_o(pwm_ah_o),
//.pwm_al_o(pwm_al_o),
//.pwm_bh_o(pwm_bh_o),
//.pwm_bl_o(pwm_bl_o),
//.pwm_ch_o(pwm_ch_o),
//.pwm_cl_o(pwm_cl_o),
.Vaux0_v_n(vauxn0),
.Vaux0_v_p(vauxp0),
.Vaux8_v_n(vauxn8),
.Vaux8_v_p(vauxp8),
.Vp_Vn_v_n(vn_in),
.Vp_Vn_v_p(vp_in),
//.muxaddr_out(muxaddr_out),
.gpo_o(gpo),
.pwm_m1_ah_o(pwm_m1_ah_o),
.pwm_m1_al_o(pwm_m1_al_o),
.pwm_m1_bh_o(pwm_m1_bh_o),
.pwm_m1_bl_o(pwm_m1_bl_o),
.pwm_m1_ch_o(pwm_m1_ch_o),
.pwm_m1_cl_o(pwm_m1_cl_o),
.pwm_m2_ah_o(pwm_m2_ah_o),
.pwm_m2_al_o(pwm_m2_al_o),
.pwm_m2_bh_o(pwm_m2_bh_o),
.pwm_m2_bl_o(pwm_m2_bl_o),
.pwm_m2_ch_o(pwm_m2_ch_o),
.pwm_m2_cl_o(pwm_m2_cl_o),
.vaux0_v_n(vauxn0),
.vaux0_v_p(vauxp0),
.vaux8_v_n(vauxn8),
.vaux8_v_p(vauxp8),
/*.muxaddr_out(muxaddr_out),*/
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
@ -317,27 +447,40 @@ module system_top (
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_I (iic_mux_scl_i_s),
.iic_mux_scl_O (iic_mux_scl_o_s),
.iic_mux_scl_T (iic_mux_scl_t_s),
.iic_mux_sda_I (iic_mux_sda_i_s),
.iic_mux_sda_O (iic_mux_sda_o_s),
.iic_mux_sda_T (iic_mux_sda_t_s),
.ps_intr_10 (ps_intrs[10]),
.ps_intr_11 (ps_intrs[11]),
.ps_intr_12 (ps_intrs[12]),
.ps_intr_13 (ps_intrs[13]),
.ps_intr_4 (ps_intrs[4]),
.ps_intr_5 (ps_intrs[5]),
.ps_intr_6 (ps_intrs[6]),
.ps_intr_7 (ps_intrs[7]),
.ps_intr_8 (ps_intrs[8]),
.ps_intr_9 (ps_intrs[9]),
.iic_fmc_intr(ps_intrs[11]),
.motcon2_c_m_1_irq(ps_intrs[13]),
.motcon2_c_m_2_irq(ps_intrs[9]),
.motcon2_s_d_irq(ps_intrs[12]),
//.motcon2_ctrl_irq(ps_intrs[10]),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.iic_ee2_scl_io(iic_ee2_scl_io),
.iic_ee2_sda_io(iic_ee2_sda_io),
.spi0_clk_i (1'b0),
.spi0_clk_o (fmc_spi1_sck),
.spi0_csn_0_o (fmc_spi1_sel1_rdc),
.spi0_csn_1_o (),
.spi0_csn_2_o (),
.spi0_csn_i (1'b1),
.spi0_sdi_i (fmc_spi1_miso),
.spi0_sdo_i (1'b0),
.spi0_sdo_o (fmc_spi1_mosi),
.spi1_clk_i (1'b0),
.spi1_clk_o (),
.spi1_csn_0_o (),
.spi1_csn_1_o (),
.spi1_csn_2_o (),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b0),
.spi1_sdo_i (1'b0),
.spi1_sdo_o (),
.refclk(refclk),
.refclk_rst(refclk_rst),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif));