arradio/c5soc- interface updates
Rejeesh Kutty
parent
f3ad2e24c1
commit
fca88caf93
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9361_lvds_if_c5 (
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// physical interface (receive)
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input rx_clk_in_p,
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input rx_clk_in_n,
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input rx_frame_in_p,
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input rx_frame_in_n,
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input [ 5:0] rx_data_in_p,
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input [ 5:0] rx_data_in_n,
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// physical interface (transmit)
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output tx_clk_out_p,
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output tx_clk_out_n,
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output tx_frame_out_p,
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output tx_frame_out_n,
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output [ 5:0] tx_data_out_p,
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output [ 5:0] tx_data_out_n,
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// ensm control
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output enable,
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output txnrx,
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// clock (common to both receive and transmit)
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output clk,
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// receive data path interface
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output [ 3:0] rx_frame,
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output [ 5:0] rx_data_0,
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output [ 5:0] rx_data_1,
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output [ 5:0] rx_data_2,
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output [ 5:0] rx_data_3,
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// transmit data path interface
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input [ 3:0] tx_frame,
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input [ 5:0] tx_data_0,
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input [ 5:0] tx_data_1,
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input [ 5:0] tx_data_2,
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input [ 5:0] tx_data_3,
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input tx_enable,
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input tx_txnrx,
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// locked (status)
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output locked,
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// delay interface
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input up_clk,
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input up_rstn);
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// internal registers
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reg pll_rst = 'd0;
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reg locked_int = 'd0;
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reg tx_core_enable_int = 'd0;
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reg tx_core_txnrx_int = 'd0;
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reg [27:0] tx_core_data_int = 'd0;
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reg tx_core_enable = 'd0;
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reg tx_core_txnrx = 'd0;
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reg [27:0] tx_core_data = 'd0;
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reg tx_locked_int = 'd0;
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reg tx_locked = 'd0;
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// internal signals
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wire [27:0] rx_core_data_s;
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wire rx_locked_s;
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wire tx_core_clk;
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wire tx_locked_s;
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// pll reset
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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pll_rst <= 1'b1;
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end else begin
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pll_rst <= 1'b0;
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end
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end
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assign locked = locked_int;
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always @(posedge clk) begin
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locked_int <= rx_locked_s & tx_locked;
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end
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// receive
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assign rx_frame[3] = rx_core_data_s[24];
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assign rx_frame[2] = rx_core_data_s[25];
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assign rx_frame[1] = rx_core_data_s[26];
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assign rx_frame[0] = rx_core_data_s[27];
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assign rx_data_3[5] = rx_core_data_s[20];
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assign rx_data_3[4] = rx_core_data_s[16];
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assign rx_data_3[3] = rx_core_data_s[12];
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assign rx_data_3[2] = rx_core_data_s[ 8];
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assign rx_data_3[1] = rx_core_data_s[ 4];
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assign rx_data_3[0] = rx_core_data_s[ 0];
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assign rx_data_2[5] = rx_core_data_s[21];
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assign rx_data_2[4] = rx_core_data_s[17];
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assign rx_data_2[3] = rx_core_data_s[13];
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assign rx_data_2[2] = rx_core_data_s[ 9];
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assign rx_data_2[1] = rx_core_data_s[ 5];
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assign rx_data_2[0] = rx_core_data_s[ 1];
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assign rx_data_1[5] = rx_core_data_s[22];
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assign rx_data_1[4] = rx_core_data_s[18];
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assign rx_data_1[3] = rx_core_data_s[14];
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assign rx_data_1[2] = rx_core_data_s[10];
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assign rx_data_1[1] = rx_core_data_s[ 6];
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assign rx_data_1[0] = rx_core_data_s[ 2];
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assign rx_data_0[5] = rx_core_data_s[23];
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assign rx_data_0[4] = rx_core_data_s[19];
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assign rx_data_0[3] = rx_core_data_s[15];
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assign rx_data_0[2] = rx_core_data_s[11];
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assign rx_data_0[1] = rx_core_data_s[ 7];
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assign rx_data_0[0] = rx_core_data_s[ 3];
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// transmit (by definition, tx_core_clk and clk are the same (shared pll))
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// however, we safe guard transition - incase you keep them separate
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assign tx_clk_out_n = 1'd0;
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assign tx_frame_out_n = 1'd0;
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assign tx_data_out_n = 6'd0;
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always @(negedge clk) begin
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tx_core_enable_int <= tx_enable;
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tx_core_txnrx_int <= tx_txnrx;
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tx_core_data_int[24] <= tx_frame[3];
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tx_core_data_int[25] <= tx_frame[2];
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tx_core_data_int[26] <= tx_frame[1];
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tx_core_data_int[27] <= tx_frame[0];
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tx_core_data_int[20] <= tx_data_3[5];
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tx_core_data_int[16] <= tx_data_3[4];
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tx_core_data_int[12] <= tx_data_3[3];
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tx_core_data_int[ 8] <= tx_data_3[2];
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tx_core_data_int[ 4] <= tx_data_3[1];
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tx_core_data_int[ 0] <= tx_data_3[0];
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tx_core_data_int[21] <= tx_data_2[5];
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tx_core_data_int[17] <= tx_data_2[4];
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tx_core_data_int[13] <= tx_data_2[3];
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tx_core_data_int[ 9] <= tx_data_2[2];
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tx_core_data_int[ 5] <= tx_data_2[1];
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tx_core_data_int[ 1] <= tx_data_2[0];
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tx_core_data_int[22] <= tx_data_1[5];
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tx_core_data_int[18] <= tx_data_1[4];
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tx_core_data_int[14] <= tx_data_1[3];
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tx_core_data_int[10] <= tx_data_1[2];
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tx_core_data_int[ 6] <= tx_data_1[1];
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tx_core_data_int[ 2] <= tx_data_1[0];
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tx_core_data_int[23] <= tx_data_0[5];
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tx_core_data_int[19] <= tx_data_0[4];
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tx_core_data_int[15] <= tx_data_0[3];
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tx_core_data_int[11] <= tx_data_0[2];
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tx_core_data_int[ 7] <= tx_data_0[1];
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tx_core_data_int[ 3] <= tx_data_0[0];
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end
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always @(posedge tx_core_clk) begin
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tx_core_enable <= tx_core_enable_int;
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tx_core_txnrx <= tx_core_txnrx_int;
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tx_core_data <= tx_core_data_int;
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end
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always @(negedge tx_core_clk) begin
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tx_locked_int <= tx_locked_s;
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end
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always @(posedge clk) begin
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tx_locked <= tx_locked_int;
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end
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// instantiations
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altlvds_rx #(
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.buffer_implementation ("RAM"),
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.cds_mode ("UNUSED"),
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.common_rx_tx_pll ("ON"),
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.data_align_rollover (4),
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.data_rate ("500.0 Mbps"),
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.deserialization_factor (4),
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.dpa_initial_phase_value (0),
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.dpll_lock_count (0),
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.dpll_lock_window (0),
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.enable_clock_pin_mode ("UNUSED"),
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.enable_dpa_align_to_rising_edge_only ("OFF"),
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.enable_dpa_calibration ("ON"),
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.enable_dpa_fifo ("UNUSED"),
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.enable_dpa_initial_phase_selection ("OFF"),
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.enable_dpa_mode ("OFF"),
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.enable_dpa_pll_calibration ("OFF"),
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.enable_soft_cdr_mode ("OFF"),
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.implement_in_les ("OFF"),
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.inclock_boost (0),
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.inclock_data_alignment ("EDGE_ALIGNED"),
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.inclock_period (4000),
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.inclock_phase_shift (0),
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.input_data_rate (500),
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.intended_device_family ("Cyclone V"),
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.lose_lock_on_one_change ("UNUSED"),
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.lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_lvds_if_c5_rx"),
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.lpm_type ("altlvds_rx"),
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.number_of_channels (7),
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.outclock_resource ("Global clock"),
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.pll_operation_mode ("NORMAL"),
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.pll_self_reset_on_loss_lock ("UNUSED"),
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.port_rx_channel_data_align ("PORT_UNUSED"),
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.port_rx_data_align ("PORT_UNUSED"),
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.refclk_frequency ("250.000000 MHz"),
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.registered_data_align_input ("UNUSED"),
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.registered_output ("ON"),
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.reset_fifo_at_first_lock ("UNUSED"),
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.rx_align_data_reg ("RISING_EDGE"),
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.sim_dpa_is_negative_ppm_drift ("OFF"),
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.sim_dpa_net_ppm_variation (0),
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.sim_dpa_output_clock_phase_shift (0),
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.use_coreclock_input ("OFF"),
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.use_dpll_rawperror ("OFF"),
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.use_external_pll ("OFF"),
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.use_no_phase_shift ("ON"),
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.x_on_bitslip ("ON"),
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.clk_src_is_pll ("off"))
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i_altlvds_rx (
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.pll_areset (pll_rst),
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.rx_in ({rx_frame_in_p, rx_data_in_p}),
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.rx_inclock (rx_clk_in_p),
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.rx_locked (rx_locked_s),
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.rx_out (rx_core_data_s),
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.rx_outclock (clk),
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.dpa_pll_cal_busy (),
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.dpa_pll_recal (1'b0),
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.pll_phasecounterselect (),
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.pll_phasedone (1'b1),
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.pll_phasestep (),
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.pll_phaseupdown (),
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.pll_scanclk (),
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.rx_cda_max (),
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.rx_cda_reset ({7{1'b0}}),
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.rx_channel_data_align ({7{1'b0}}),
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.rx_coreclk ({7{1'b1}}),
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.rx_data_align (1'b0),
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.rx_data_align_reset (1'b0),
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.rx_data_reset (1'b0),
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.rx_deskew (1'b0),
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.rx_divfwdclk (),
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.rx_dpa_lock_reset ({7{1'b0}}),
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.rx_dpa_locked (),
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.rx_dpaclock (1'b0),
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.rx_dpll_enable ({7{1'b1}}),
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.rx_dpll_hold ({7{1'b0}}),
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.rx_dpll_reset ({7{1'b0}}),
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.rx_enable (1'b1),
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.rx_fifo_reset ({7{1'b0}}),
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.rx_pll_enable (1'b1),
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.rx_readclock (1'b0),
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.rx_reset ({7{1'b0}}),
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.rx_syncclock (1'b0));
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altlvds_tx #(
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.center_align_msb ("UNUSED"),
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.common_rx_tx_pll ("ON"),
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.coreclock_divide_by (1),
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.data_rate ("500.0 Mbps"),
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.deserialization_factor (4),
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.differential_drive (0),
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.enable_clock_pin_mode ("UNUSED"),
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.implement_in_les ("OFF"),
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.inclock_boost (0),
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.inclock_data_alignment ("EDGE_ALIGNED"),
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.inclock_period (4000),
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.inclock_phase_shift (0),
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.intended_device_family ("Cyclone V"),
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.lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_lvds_if_c5_tx"),
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.lpm_type ("altlvds_tx"),
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.multi_clock ("OFF"),
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.number_of_channels (7),
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.outclock_alignment ("EDGE_ALIGNED"),
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.outclock_divide_by (2),
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.outclock_duty_cycle (50),
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.outclock_multiply_by (1),
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.outclock_phase_shift (0),
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.outclock_resource ("Global clock"),
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.output_data_rate (500),
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.pll_compensation_mode ("AUTO"),
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.pll_self_reset_on_loss_lock ("OFF"),
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.preemphasis_setting (0),
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.refclk_frequency ("250.000000 MHz"),
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.registered_input ("TX_CORECLK"),
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.use_external_pll ("OFF"),
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.use_no_phase_shift ("ON"),
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.vod_setting (0),
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.clk_src_is_pll ("off"))
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i_altlvds_tx (
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.pll_areset (pll_rst),
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.tx_in (tx_core_data),
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.tx_inclock (rx_clk_in_p),
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.tx_coreclock (tx_core_clk),
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.tx_locked (tx_locked_s),
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.tx_out ({tx_frame_out_p, tx_data_out_p}),
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.tx_outclock (tx_clk_out_p),
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.sync_inclock (1'b0),
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.tx_data_reset (1'b0),
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.tx_enable (1'b1),
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.tx_pll_enable (1'b1),
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.tx_syncclock (1'b0));
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altddio_out #(
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.extend_oe_disable ("OFF"),
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.intended_device_family ("Cyclone V"),
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.invert_output ("OFF"),
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.lpm_hint ("UNUSED"),
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.lpm_type ("altddio_out"),
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.oe_reg ("UNREGISTERED"),
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.power_up_high ("OFF"),
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.width (1))
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i_altddio_enable (
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.datain_h (tx_core_enable),
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.datain_l (tx_core_enable),
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.outclock (tx_core_clk),
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.dataout (enable),
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.aclr (1'b0),
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.aset (1'b0),
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.oe (1'b1),
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.oe_out (),
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.outclocken (1'b1),
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.sclr (1'b0),
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.sset (1'b0));
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altddio_out #(
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.extend_oe_disable ("OFF"),
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.intended_device_family ("Cyclone V"),
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.invert_output ("OFF"),
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.lpm_hint ("UNUSED"),
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.lpm_type ("altddio_out"),
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.oe_reg ("UNREGISTERED"),
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.power_up_high ("OFF"),
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.width (1))
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i_altddio_txnrx (
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.datain_h (tx_core_txnrx),
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.datain_l (tx_core_txnrx),
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.outclock (tx_core_clk),
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.dataout (txnrx),
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.aclr (1'b0),
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.aset (1'b0),
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.oe (1'b1),
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.oe_out (),
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.outclocken (1'b1),
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.sclr (1'b0),
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.sset (1'b0));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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