diff --git a/projects/ad9081_fmca_ebz_x_band/Makefile b/projects/ad9081_fmca_ebz_x_band/Makefile new file mode 100644 index 000000000..2458d9876 --- /dev/null +++ b/projects/ad9081_fmca_ebz_x_band/Makefile @@ -0,0 +1,7 @@ +#################################################################################### +## Copyright (c) 2018 - 2021 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +include ../scripts/project-toplevel.mk diff --git a/projects/ad9081_fmca_ebz_x_band/Readme.md b/projects/ad9081_fmca_ebz_x_band/Readme.md new file mode 100644 index 000000000..5461c315a --- /dev/null +++ b/projects/ad9081_fmca_ebz_x_band/Readme.md @@ -0,0 +1,10 @@ +# AD9081-FMCA-EBZ X BAND HDL Project + +Here are some pointers to help you: + * [Board Product Page](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/x-band-development-platform.html) + * Parts : [AD9081 : Quad, 16-Bit, 12GSPS RFDAC and Quad, 12-Bit, 4GSPS RFADC](https://www.analog.com/AD9081) + * Parts : [ADAR1000 : 8 GHz to 16 GHz, 4-Channel, X Band and Ku Band Beamformer](https://www.analog.com/en/products/adar1000.html) + * Parts : [ADTR1107 : 6 GHz to 18 GHz, Front-End IC](https://www.analog.com/en/products/adtr1107.html) + * Project Doc: https://wiki.analog.com/resources/eval/developer-kits/x-band-dev-kit + * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad9081_fmca_ebz/ad9081_fmca_ebz_hdl + * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9081 diff --git a/projects/ad9081_fmca_ebz_x_band/zcu102/Makefile b/projects/ad9081_fmca_ebz_x_band/zcu102/Makefile new file mode 100644 index 000000000..cd51623e1 --- /dev/null +++ b/projects/ad9081_fmca_ebz_x_band/zcu102/Makefile @@ -0,0 +1,49 @@ +#################################################################################### +## Copyright (c) 2018 - 2021 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad9081_fmca_ebz_x_band_zcu102 + +M_DEPS += xband_constr.xdc +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc +M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl +M_DEPS += ../../common/xilinx/data_offload_bd.tcl +M_DEPS += ../../common/xilinx/dacfifo_bd.tcl +M_DEPS += ../../common/xilinx/adcfifo_bd.tcl +M_DEPS += ../../ad9081_fmca_ebz/zcu102/timing_constr.xdc +M_DEPS += ../../ad9081_fmca_ebz/zcu102/system_constr.xdc +M_DEPS += ../../ad9081_fmca_ebz/common/versal_transceiver.tcl +M_DEPS += ../../ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl +M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl +M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl +M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_3w_spi.v +M_DEPS += system_bd.tcl + +LIB_DEPS += axi_dmac +LIB_DEPS += axi_sysid +LIB_DEPS += axi_tdd +LIB_DEPS += data_offload +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac +LIB_DEPS += jesd204/axi_jesd204_rx +LIB_DEPS += jesd204/axi_jesd204_tx +LIB_DEPS += jesd204/jesd204_rx +LIB_DEPS += jesd204/jesd204_tx +LIB_DEPS += jesd204/jesd204_versal_gt_adapter_rx +LIB_DEPS += jesd204/jesd204_versal_gt_adapter_tx +LIB_DEPS += sysid_rom +LIB_DEPS += util_adcfifo +LIB_DEPS += util_dacfifo +LIB_DEPS += util_do_ram +LIB_DEPS += util_hbm +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 +LIB_DEPS += util_tdd_sync +LIB_DEPS += xilinx/axi_adxcvr +LIB_DEPS += xilinx/util_adxcvr + +include ../../scripts/project-xilinx.mk diff --git a/projects/ad9081_fmca_ebz_x_band/zcu102/system_bd.tcl b/projects/ad9081_fmca_ebz_x_band/zcu102/system_bd.tcl new file mode 100644 index 000000000..fd62b5a3a --- /dev/null +++ b/projects/ad9081_fmca_ebz_x_band/zcu102/system_bd.tcl @@ -0,0 +1,156 @@ + +## ADC FIFO depth in samples per converter +set adc_fifo_samples_per_converter [expr $ad_project_params(RX_KS_PER_CHANNEL)*1024] +## DAC FIFO depth in samples per converter +set dac_fifo_samples_per_converter [expr $ad_project_params(TX_KS_PER_CHANNEL)*1024] + +source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl + +ad_mem_hp0_interconnect $sys_cpu_clk sys_ps8/S_AXI_HP0 + +source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 + +sysid_gen_sys_init_file + +# Parameters for 15.5Gpbs lane rate + +ad_ip_parameter util_mxfe_xcvr CONFIG.RX_CLK25_DIV 31 +ad_ip_parameter util_mxfe_xcvr CONFIG.TX_CLK25_DIV 31 +ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG0 0x1fa +ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG1 0x23 +ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG2 0x2 +ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_FBDIV 2 +ad_ip_parameter util_mxfe_xcvr CONFIG.A_TXDIFFCTRL 0xc +ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG0 0x3 +ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG2_GEN2 0x265 +ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG2_GEN4 0x164 +ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3 0x1A +ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN2 0x1A +ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN3 0x1A +ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN4 0x12 +ad_ip_parameter util_mxfe_xcvr CONFIG.CH_HSPMUX 0x6868 +ad_ip_parameter util_mxfe_xcvr CONFIG.PREIQ_FREQ_BST 1 +ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG0 0x4 +ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG1 0x0 +ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG 0x0 +ad_ip_parameter util_mxfe_xcvr CONFIG.TX_PI_BIASSET 3 + +ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_REFCLK_DIV 1 +ad_ip_parameter util_mxfe_xcvr CONFIG.POR_CFG 0x0 +ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG0 0x333c +ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG4 0x45 +ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_FBDIV 20 +ad_ip_parameter util_mxfe_xcvr CONFIG.PPF0_CFG 0xF00 +ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CP 0xFF +ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CP_G3 0xF +ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_LPF 0x2FF + +# Overwrite parameter for lower lane rates which use CPLL +if {$ad_project_params(RX_LANE_RATE) < 12} { + ad_ip_parameter util_mxfe_xcvr CONFIG.RX_WIDEMODE_CDR 0x0 + ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG0 0x200 + ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG1 0xFD + + ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3 0x12 + ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN2 0x12 + ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN3 0x12 + ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN4 0x12 +} + +create_bd_port -dir O sys_clk +ad_connect sys_ps8/pl_clk0 sys_clk + +# SPI and IIC for PMOD0 and PMOD1 +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_pmod +ad_ip_instance axi_iic axi_iic_pmod +ad_connect iic_pmod axi_iic_pmod/iic + +ad_cpu_interrupt ps-14 mb-8 axi_iic_pmod/iic2intc_irpt + +ad_cpu_interconnect 0x45100000 axi_iic_pmod + +create_bd_port -dir O -from 7 -to 0 spi_pmod_csn_o +create_bd_port -dir I -from 7 -to 0 spi_pmod_csn_i +create_bd_port -dir I spi_pmod_clk_i +create_bd_port -dir O spi_pmod_clk_o +create_bd_port -dir I spi_pmod_sdo_i +create_bd_port -dir O spi_pmod_sdo_o +create_bd_port -dir I spi_pmod_sdi_i + +# SPI at 100/8 = 12.5 MHz +ad_ip_instance axi_quad_spi axi_spi_pmod +ad_ip_parameter axi_spi_pmod CONFIG.C_USE_STARTUP 0 +ad_ip_parameter axi_spi_pmod CONFIG.C_NUM_SS_BITS 8 +ad_ip_parameter axi_spi_pmod CONFIG.C_SCK_RATIO 8 + +ad_connect spi_pmod_csn_i axi_spi_pmod/ss_i +ad_connect spi_pmod_csn_o axi_spi_pmod/ss_o +ad_connect spi_pmod_clk_i axi_spi_pmod/sck_i +ad_connect spi_pmod_clk_o axi_spi_pmod/sck_o +ad_connect spi_pmod_sdo_i axi_spi_pmod/io0_i +ad_connect spi_pmod_sdo_o axi_spi_pmod/io0_o +ad_connect spi_pmod_sdi_i axi_spi_pmod/io1_i + +ad_connect $sys_cpu_clk axi_spi_pmod/ext_spi_clk + +ad_cpu_interrupt ps-15 mb-7 axi_spi_pmod/ip2intc_irpt + +ad_cpu_interconnect 0x45200000 axi_spi_pmod + +# SPI for FMC interposer +create_bd_port -dir O -from 7 -to 0 spi_fmc_csn_o +create_bd_port -dir I -from 7 -to 0 spi_fmc_csn_i +create_bd_port -dir I spi_fmc_clk_i +create_bd_port -dir O spi_fmc_clk_o +create_bd_port -dir I spi_fmc_sdo_i +create_bd_port -dir O spi_fmc_sdo_o +create_bd_port -dir I spi_fmc_sdi_i + +# SPI at 100/16 = 6.25 MHz +ad_ip_instance axi_quad_spi axi_spi_fmc +ad_ip_parameter axi_spi_fmc CONFIG.C_USE_STARTUP 0 +ad_ip_parameter axi_spi_fmc CONFIG.C_NUM_SS_BITS 8 +ad_ip_parameter axi_spi_fmc CONFIG.C_SCK_RATIO 16 +ad_ip_parameter axi_spi_fmc CONFIG.Multiples16 1 + +ad_connect spi_fmc_csn_i axi_spi_fmc/ss_i +ad_connect spi_fmc_csn_o axi_spi_fmc/ss_o +ad_connect spi_fmc_clk_i axi_spi_fmc/sck_i +ad_connect spi_fmc_clk_o axi_spi_fmc/sck_o +ad_connect spi_fmc_sdo_i axi_spi_fmc/io0_i +ad_connect spi_fmc_sdo_o axi_spi_fmc/io0_o +ad_connect spi_fmc_sdi_i axi_spi_fmc/io1_i + +ad_connect $sys_cpu_clk axi_spi_fmc/ext_spi_clk + +ad_cpu_interrupt ps-9 mb-7 axi_spi_fmc/ip2intc_irpt + +ad_cpu_interconnect 0x45300000 axi_spi_fmc + +# Connect TDD +create_bd_port -dir I tdd_sync +create_bd_port -dir O tdd_enabled +create_bd_port -dir O tdd_rx_mxfe_en +create_bd_port -dir O tdd_tx_mxfe_en +create_bd_port -dir O tdd_tx_stingray_en + +ad_disconnect tdd_sync_0/sync_in GND +ad_disconnect tdd_sync_0/sync_mode GND + +ad_connect tdd_sync_0/sync_in tdd_sync +ad_connect tdd_sync_0/sync_mode VCC + +ad_connect axi_tdd_0/tdd_enabled tdd_enabled +ad_connect axi_tdd_0/tdd_rx_rf_en tdd_rx_mxfe_en +ad_connect axi_tdd_0/tdd_tx_rf_en tdd_tx_mxfe_en +# repurpose tdd_tx_vco_en as XUD1A and Stingray TR +ad_connect axi_tdd_0/tdd_tx_vco_en tdd_tx_stingray_en + diff --git a/projects/ad9081_fmca_ebz_x_band/zcu102/system_project.tcl b/projects/ad9081_fmca_ebz_x_band/zcu102/system_project.tcl new file mode 100644 index 000000000..6b1ff9f73 --- /dev/null +++ b/projects/ad9081_fmca_ebz_x_band/zcu102/system_project.tcl @@ -0,0 +1,61 @@ + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +# get_env_param retrieves parameter value from the environment if exists, +# other case use the default value +# +# Use over-writable parameters from the environment. +# +# e.g. +# make RX_JESD_L=4 RX_JESD_M=8 RX_JESD_S=1 TX_JESD_L=4 TX_JESD_M=8 TX_JESD_S=1 +# make RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1 + +# +# Parameter description: +# JESD_MODE : Used link layer encoder mode +# 64B66B - 64b66b link layer defined in JESD 204C, uses Xilinx IP as Physical layer +# 8B10B - 8b10b link layer defined in JESD 204B, uses ADI IP as Physical layer +# +# RX_LANE_RATE : Line rate of the Rx link ( MxFE to FPGA ) +# TX_LANE_RATE : Line rate of the Tx link ( FPGA to MxFE ) +# [RX/TX]_JESD_M : Number of converters per link +# [RX/TX]_JESD_L : Number of lanes per link +# [RX/TX]_JESD_NP : Number of bits per sample, only 16 is supported +# [RX/TX]_NUM_LINKS : Number of links, matches numer of MxFE devices +# [RX/TX]_KS_PER_CHANNEL: Data offload depth capability, kilosamples per channel +# +# + +adi_project ad9081_fmca_ebz_x_band_zcu102 0 [list \ + JESD_MODE [get_env_param JESD_MODE 8B10B ] \ + RX_LANE_RATE [get_env_param RX_LANE_RATE 10 ] \ + TX_LANE_RATE [get_env_param TX_LANE_RATE 10 ] \ + RX_JESD_M [get_env_param RX_JESD_M 8 ] \ + RX_JESD_L [get_env_param RX_JESD_L 4 ] \ + RX_JESD_S [get_env_param RX_JESD_S 1 ] \ + RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ + TX_JESD_M [get_env_param TX_JESD_M 8 ] \ + TX_JESD_L [get_env_param TX_JESD_L 4 ] \ + TX_JESD_S [get_env_param TX_JESD_S 1 ] \ + TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ + TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ + RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 64 ] \ + TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 64 ] \ + TDD_SUPPORT [get_env_param TDD_SUPPORT 1 ] \ + SHARED_DEVCLK [get_env_param SHARED_DEVCLK 1 ] \ +] + +adi_project_files ad9081_fmca_ebz_x_band_zcu102 [list \ + "system_top.v" \ + "../../ad9081_fmca_ebz/zcu102/system_constr.xdc" \ + "../../ad9081_fmca_ebz/zcu102/timing_constr.xdc" \ + "xband_constr.xdc" \ + "../../../library/common/ad_3w_spi.v" \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ] + +adi_project_run ad9081_fmca_ebz_x_band_zcu102 + diff --git a/projects/ad9081_fmca_ebz_x_band/zcu102/system_top.v b/projects/ad9081_fmca_ebz_x_band/zcu102/system_top.v new file mode 100644 index 000000000..77c3c7990 --- /dev/null +++ b/projects/ad9081_fmca_ebz_x_band/zcu102/system_top.v @@ -0,0 +1,528 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top #( + parameter TX_JESD_L = 8, + parameter TX_NUM_LINKS = 1, + parameter RX_JESD_L = 8, + parameter RX_NUM_LINKS = 1, + parameter SHARED_DEVCLK = 0, + parameter TDD_SUPPORT = 0, + parameter JESD_MODE = "8B10B" +) ( + + input [12:0] gpio_bd_i, + output [ 7:0] gpio_bd_o, + + // FMC HPC IOs + input [1:0] agc0, + input [1:0] agc1, + input [1:0] agc2, + input [1:0] agc3, + input clkin6_n, + input clkin6_p, + input clkin10_n, + input clkin10_p, + input fpga_refclk_in_n, + input fpga_refclk_in_p, + input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_n, + input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_p, + output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_n, + output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_p, + input fpga_syncin_0_n, + input fpga_syncin_0_p, + inout fpga_syncin_1_n, + inout fpga_syncin_1_p, + output fpga_syncout_0_n, + output fpga_syncout_0_p, + inout fpga_syncout_1_n, + inout fpga_syncout_1_p, + inout [10:0] gpio, + inout hmc_gpio1, + output hmc_sync, + input [1:0] irqb, + output rstb, + output [1:0] rxen, + output spi0_csb, + input spi0_miso, + output spi0_mosi, + output spi0_sclk, + output spi1_csb, + output spi1_sclk, + inout spi1_sdio, + input sysref2_n, + input sysref2_p, + output [1:0] txen, + + // PMOD0 + output pmod0_0_1_PA_ON, + output pmod0_4_2_TR, + output pmod0_1_3_MOSI, + output pmod0_5_4_TX_LOAD, + input pmod0_2_5_MISO, + output pmod0_6_6_RX_LOAD, + output pmod0_3_7_SCLK, + inout pmod0_7_8_SCL, + // PMOD1 + output pmod1_0_1_CSB1, + output pmod1_4_2_CSB2, + output pmod1_1_3_CSB3, + output pmod1_5_4_CSB4, + output pmod1_2_5_CSB5, + output reg pmod1_6_6_5V_CTRL = 1'b0, + inout pmod1_3_7_SDA, + output reg pmod1_7_8_PWR_UP_DOWN = 1'b0, + + // FMC1 custom breakout board + output fmc_bob_xud1_imu_sclk, + output fmc_bob_xud1_imu_mosi, + inout fmc_bob_xud1_gpio0, + inout fmc_bob_xud1_gpio1, + input fmc_bob_xud1_imu_miso, + output fmc_bob_xud1_imu_csb, + output fmc_bob_xud1_imu_rst, + output fmc_bob_xud1_mosi, + output fmc_bob_xud1_csb, + inout fmc_bob_xud1_imu_gpio0, + inout fmc_bob_xud1_imu_gpio1, + inout fmc_bob_xud1_imu_gpio2, + inout fmc_bob_xud1_imu_gpio3, + output fmc_bob_xud1_sclk, + input fmc_bob_xud1_miso, + inout fmc_bob_xud1_gpio2, + inout fmc_bob_xud1_gpio3, + inout fmc_bob_xud1_gpio4, + inout fmc_bob_xud1_gpio5 +); + + // internal signals + + wire [94:0] gpio_i; + wire [94:0] gpio_o; + wire [94:0] gpio_t; + wire [ 2:0] spi0_csn; + + wire [ 2:0] spi1_csn; + wire spi1_mosi; + wire spi1_miso; + + wire ref_clk; + wire sysref; + wire [TX_NUM_LINKS-1:0] tx_syncin; + wire [RX_NUM_LINKS-1:0] rx_syncout; + + wire [7:0] rx_data_p_loc; + wire [7:0] rx_data_n_loc; + wire [7:0] tx_data_p_loc; + wire [7:0] tx_data_n_loc; + + wire clkin6; + wire clkin10; + wire tx_device_clk; + wire rx_device_clk_internal; + wire rx_device_clk; + + wire [7:0] spi_pmod_csn; + wire spi_pmod_clk; + wire spi_pmod_mosi; + wire spi_pmod_miso; + wire [7:0] spi_fmc_csn; + wire spi_fmc_clk; + wire spi_fmc_mosi; + wire spi_fmc_miso; + wire pwr_up_mask; + wire sys_clk; + + wire tdd_rx_mxfe_en; + wire tdd_tx_mxfe_en; + wire tdd_tx_stingray_en; + wire tdd_support; + wire tr; + wire tdd_enabled; + wire tdd_sync; + + assign pmod0_1_3_MOSI = spi_pmod_mosi; + assign pmod1_0_1_CSB1 = spi_pmod_csn[1]; + assign pmod1_4_2_CSB2 = spi_pmod_csn[2]; + assign pmod1_1_3_CSB3 = spi_pmod_csn[3]; + assign pmod1_5_4_CSB4 = spi_pmod_csn[4]; + assign pmod1_2_5_CSB5 = spi_pmod_csn[5]; + assign pmod0_3_7_SCLK = spi_pmod_clk; + + assign fmc_bob_xud1_mosi = spi_fmc_mosi; + assign fmc_bob_xud1_csb = spi_fmc_csn[6]; + assign fmc_bob_xud1_sclk = spi_fmc_clk; + + assign fmc_bob_xud1_imu_mosi = spi_fmc_mosi; + assign fmc_bob_xud1_imu_csb = spi_fmc_csn[7]; + assign fmc_bob_xud1_imu_sclk = spi_fmc_clk; + + assign spi_pmod_miso = ~&spi_pmod_csn[5:1] ? pmod0_2_5_MISO : + 1'b0; + + assign spi_fmc_miso = ~spi_fmc_csn[6] ? fmc_bob_xud1_miso : + ~spi_fmc_csn[7] ? fmc_bob_xud1_imu_miso : + 1'b0; + // instantiations + + IBUFDS_GTE4 i_ibufds_ref_clk ( + .CEB (1'd0), + .I (fpga_refclk_in_p), + .IB (fpga_refclk_in_n), + .O (ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_sysref ( + .I (sysref2_p), + .IB (sysref2_n), + .O (sysref)); + + IBUFDS i_ibufds_tx_device_clk ( + .I (clkin6_p), + .IB (clkin6_n), + .O (clkin6)); + + IBUFDS i_ibufds_rx_device_clk ( + .I (clkin10_p), + .IB (clkin10_n), + .O (clkin10)); + + IBUFDS i_ibufds_syncin_0 ( + .I (fpga_syncin_0_p), + .IB (fpga_syncin_0_n), + .O (tx_syncin[0])); + + OBUFDS i_obufds_syncout_0 ( + .I (rx_syncout[0]), + .O (fpga_syncout_0_p), + .OB (fpga_syncout_0_n)); + + BUFG i_tx_device_clk ( + .I (clkin6), + .O (tx_device_clk)); + + BUFG i_rx_device_clk ( + .I (clkin10), + .O (rx_device_clk_internal)); + + assign rx_device_clk = SHARED_DEVCLK ? tx_device_clk : rx_device_clk_internal; + + // spi + + assign spi0_csb = spi0_csn[0]; + assign spi1_csb = spi1_csn[0]; + + ad_3w_spi #( + .NUM_OF_SLAVES(1) + ) i_spi ( + .spi_csn (spi1_csn[0]), + .spi_clk (spi1_sclk), + .spi_mosi (spi1_mosi), + .spi_miso (spi1_miso), + .spi_sdio (spi1_sdio), + .spi_dir ()); + + // gpios + + ad_iobuf #( + .DATA_WIDTH(12) + ) i_iobuf ( + .dio_t (gpio_t[43:32]), + .dio_i (gpio_o[43:32]), + .dio_o (gpio_i[43:32]), + .dio_p ({ + hmc_gpio1, // 43 + gpio[10:0]})); // 42-32 + + assign gpio_i[44] = agc0[0]; + assign gpio_i[45] = agc0[1]; + assign gpio_i[46] = agc1[0]; + assign gpio_i[47] = agc1[1]; + assign gpio_i[48] = agc2[0]; + assign gpio_i[49] = agc2[1]; + assign gpio_i[50] = agc3[0]; + assign gpio_i[51] = agc3[1]; + assign gpio_i[52] = irqb[0]; + assign gpio_i[53] = irqb[1]; + + assign hmc_sync = gpio_o[54]; + assign rstb = gpio_o[55]; + assign rxen[0] = tdd_support ? tdd_rx_mxfe_en : gpio_o[56]; + assign rxen[1] = tdd_support ? tdd_rx_mxfe_en : gpio_o[57]; + assign txen[0] = tdd_support ? tdd_tx_mxfe_en : gpio_o[58]; + assign txen[1] = tdd_support ? tdd_tx_mxfe_en : gpio_o[59]; + + generate + if (TX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin + assign tx_syncin[1] = fpga_syncin_1_p; + end else begin + ad_iobuf #( + .DATA_WIDTH(2) + ) i_syncin_iobuf ( + .dio_t (gpio_t[61:60]), + .dio_i (gpio_o[61:60]), + .dio_o (gpio_i[61:60]), + .dio_p ({fpga_syncin_1_n, // 61 + fpga_syncin_1_p})); // 60 + end + + if (RX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin + assign fpga_syncout_1_p = rx_syncout[1]; + assign fpga_syncout_1_n = 0; + end else begin + ad_iobuf #( + .DATA_WIDTH(2) + ) i_syncout_iobuf ( + .dio_t (gpio_t[63:62]), + .dio_i (gpio_o[63:62]), + .dio_o (gpio_i[63:62]), + .dio_p ({fpga_syncout_1_n, // 63 + fpga_syncout_1_p})); // 62 + end + endgenerate + + assign tr = tdd_support ? tdd_tx_stingray_en : gpio_o[82]; + + // PMOD GPIOs + assign pmod0_0_1_PA_ON = pwr_up_mask ? 1'b0 : gpio_o[81]; + assign pmod0_4_2_TR = pwr_up_mask ? 1'b0 : tr; + assign pmod0_5_4_TX_LOAD = pwr_up_mask ? 1'b0 : gpio_o[83]; + assign pmod0_6_6_RX_LOAD = pwr_up_mask ? 1'b0 : gpio_o[84]; + + reg gpio_o_85_ms = 1'b0; + reg gpio_o_85_d1 = 1'b0; + always @(posedge sys_clk) begin + gpio_o_85_ms <= gpio_o[85]; + gpio_o_85_d1 <= gpio_o_85_ms; + end + + always @(posedge sys_clk) begin + if (pwr_up_mask) + pmod1_6_6_5V_CTRL <= 1'b0; + else + pmod1_6_6_5V_CTRL <= gpio_o_85_d1; + end + + reg gpio_o_86_ms = 1'b0; + reg gpio_o_86_d1 = 1'b0; + always @(posedge sys_clk) begin + gpio_o_86_ms <= gpio_o[86]; + gpio_o_86_d1 <= gpio_o_86_ms; + end + + always @(posedge sys_clk) begin + if (pwr_up_mask) + pmod1_7_8_PWR_UP_DOWN <= 1'b0; + else + pmod1_7_8_PWR_UP_DOWN <= gpio_o_86_d1; + end + + // XUD GPIOs + ad_iobuf #( + .DATA_WIDTH(10) + ) i_xud_iobuf ( + .dio_t ({tdd_support ? 1'b1 : gpio_t[76], // 76 TDD_EXT_TRIG + tdd_support ? 1'b0 : gpio_t[75], // 75 TDD_XUD1_STINGRAY_SYNC + tdd_support ? 1'b0 : gpio_t[74], // 74 TDD_RX_SYNC + tdd_support ? 1'b0 : gpio_t[73], // 73 TDD_TX_SYNC + gpio_t[72], // 72 + tdd_support ? 1'b0 : gpio_t[71], // 71 TRX3 + tdd_support ? 1'b0 : gpio_t[70], // 70 TRX2 + tdd_support ? 1'b0 : gpio_t[69], // 69 TRX1 + tdd_support ? 1'b0 : gpio_t[68], // 68 TRX0 + gpio_t[67] // 67 + }), + .dio_i ({gpio_o[76], // 76 TDD_EXT_TRIG + tdd_support ? tdd_tx_stingray_en : gpio_o[75], // 75 TDD_XUD1_STINGRAY_SYNC + tdd_support ? tdd_rx_mxfe_en : gpio_o[74], // 74 TDD_RX_SYNC + tdd_support ? tdd_tx_mxfe_en : gpio_o[73], // 73 TDD_TX_SYNC + gpio_o[72], // 72 + tdd_support ? tdd_tx_stingray_en : gpio_o[71], // 71 TRX3 + tdd_support ? tdd_tx_stingray_en : gpio_o[70], // 70 TRX2 + tdd_support ? tdd_tx_stingray_en : gpio_o[69], // 69 TRX1 + tdd_support ? tdd_tx_stingray_en : gpio_o[68], // 68 TRX0 + gpio_o[67] // 67 + }), + .dio_o ({gpio_i[76], + gpio_i[75], + gpio_i[74], + gpio_i[73], + gpio_i[72], + gpio_i[71], + gpio_i[70], + gpio_i[69], + gpio_i[68], + gpio_i[67] + }), + .dio_p ({fmc_bob_xud1_imu_gpio3, // 76 TDD_EXT_TRIG + fmc_bob_xud1_imu_gpio2, // 75 TDD_XUD1_STINGRAY_SYNC + fmc_bob_xud1_imu_gpio1, // 74 TDD_RX_SYNC + fmc_bob_xud1_imu_gpio0, // 73 TDD_TX_SYNC + fmc_bob_xud1_gpio5, // 72 + fmc_bob_xud1_gpio4, // 71 TRX3 + fmc_bob_xud1_gpio3, // 70 TRX2 + fmc_bob_xud1_gpio2, // 69 TRX1 + fmc_bob_xud1_gpio1, // 68 TRX0 + fmc_bob_xud1_gpio0})); // 67 + + assign tdd_support = TDD_SUPPORT ? tdd_enabled : 1'b0; + assign tdd_sync = gpio_i[76]; + + assign fmc_bob_xud1_imu_rst = gpio_o[77]; + + /* Board GPIOS. Buttons, LEDs, etc... */ + assign gpio_i[20: 8] = gpio_bd_i; + assign gpio_bd_o = gpio_o[7:0]; + + // Unused GPIOs + assign gpio_i[94:77] = gpio_o[94:77]; + assign gpio_i[59:54] = gpio_o[59:54]; + assign gpio_i[66:64] = gpio_o[66:64]; + assign gpio_i[31:21] = gpio_o[31:21]; + assign gpio_i[7:0] = gpio_o[7:0]; + + system_wrapper i_system_wrapper ( + .sys_clk (sys_clk), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .spi0_csn (spi0_csn), + .spi0_miso (spi0_miso), + .spi0_mosi (spi0_mosi), + .spi0_sclk (spi0_sclk), + .spi1_csn (spi1_csn), + .spi1_miso (spi1_miso), + .spi1_mosi (spi1_mosi), + .spi1_sclk (spi1_sclk), + // FMC HPC + .rx_data_0_n (rx_data_n_loc[0]), + .rx_data_0_p (rx_data_p_loc[0]), + .rx_data_1_n (rx_data_n_loc[1]), + .rx_data_1_p (rx_data_p_loc[1]), + .rx_data_2_n (rx_data_n_loc[2]), + .rx_data_2_p (rx_data_p_loc[2]), + .rx_data_3_n (rx_data_n_loc[3]), + .rx_data_3_p (rx_data_p_loc[3]), + .rx_data_4_n (rx_data_n_loc[4]), + .rx_data_4_p (rx_data_p_loc[4]), + .rx_data_5_n (rx_data_n_loc[5]), + .rx_data_5_p (rx_data_p_loc[5]), + .rx_data_6_n (rx_data_n_loc[6]), + .rx_data_6_p (rx_data_p_loc[6]), + .rx_data_7_n (rx_data_n_loc[7]), + .rx_data_7_p (rx_data_p_loc[7]), + .tx_data_0_n (tx_data_n_loc[0]), + .tx_data_0_p (tx_data_p_loc[0]), + .tx_data_1_n (tx_data_n_loc[1]), + .tx_data_1_p (tx_data_p_loc[1]), + .tx_data_2_n (tx_data_n_loc[2]), + .tx_data_2_p (tx_data_p_loc[2]), + .tx_data_3_n (tx_data_n_loc[3]), + .tx_data_3_p (tx_data_p_loc[3]), + .tx_data_4_n (tx_data_n_loc[4]), + .tx_data_4_p (tx_data_p_loc[4]), + .tx_data_5_n (tx_data_n_loc[5]), + .tx_data_5_p (tx_data_p_loc[5]), + .tx_data_6_n (tx_data_n_loc[6]), + .tx_data_6_p (tx_data_p_loc[6]), + .tx_data_7_n (tx_data_n_loc[7]), + .tx_data_7_p (tx_data_p_loc[7]), + .ref_clk_q0 (ref_clk), + .ref_clk_q1 (ref_clk), + .rx_device_clk (rx_device_clk), + .tx_device_clk (tx_device_clk), + .rx_sync_0 (rx_syncout), + .tx_sync_0 (tx_syncin), + .rx_sysref_0 (sysref), + .tx_sysref_0 (sysref), + .ext_sync_in (sysref), + // PMOD stuff + .iic_pmod_scl_io (pmod0_7_8_SCL), + .iic_pmod_sda_io (pmod1_3_7_SDA), + .spi_pmod_clk_i (spi_pmod_clk), + .spi_pmod_clk_o (spi_pmod_clk), + .spi_pmod_csn_i (spi_pmod_csn), + .spi_pmod_csn_o (spi_pmod_csn), + .spi_pmod_sdi_i (spi_pmod_miso), + .spi_pmod_sdo_i (spi_pmod_mosi), + .spi_pmod_sdo_o (spi_pmod_mosi), + .spi_fmc_clk_i (spi_fmc_clk), + .spi_fmc_clk_o (spi_fmc_clk), + .spi_fmc_csn_i (spi_fmc_csn), + .spi_fmc_csn_o (spi_fmc_csn), + .spi_fmc_sdi_i (spi_fmc_miso), + .spi_fmc_sdo_i (spi_fmc_mosi), + .spi_fmc_sdo_o (spi_fmc_mosi), + .tdd_sync (tdd_sync), + .tdd_enabled (tdd_enabled), + .tdd_rx_mxfe_en (tdd_rx_mxfe_en), + .tdd_tx_mxfe_en (tdd_tx_mxfe_en), + .tdd_tx_stingray_en (tdd_tx_stingray_en)); + + assign rx_data_p_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_p[RX_JESD_L*RX_NUM_LINKS-1:0]; + assign rx_data_n_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_n[RX_JESD_L*RX_NUM_LINKS-1:0]; + + assign tx_data_p[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_p_loc[TX_JESD_L*TX_NUM_LINKS-1:0]; + assign tx_data_n[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_n_loc[TX_JESD_L*TX_NUM_LINKS-1:0]; + + reg gpio_o_78_ms = 1'b0; + reg gpio_o_78_d1 = 1'b0; + always @(posedge sys_clk) begin + gpio_o_78_ms <= gpio_o[78]; + gpio_o_78_d1 <= gpio_o_78_ms; + end + + // Power up logic + // Mask gpios during powerup for 10ms + reg [20:0] pwr_up_cnt = {21'b0}; + + reg cooldown = 1'b0; + always @(posedge sys_clk) begin + if (pwr_up_cnt[20] & gpio_o_78_d1) + cooldown <= 1'b1; + end + + assign pwr_up_mask = ~pwr_up_cnt[20]; + always @(posedge sys_clk) begin + if (cooldown) begin + pwr_up_cnt <= 'h0; + end else if (~pwr_up_cnt[20]) begin + pwr_up_cnt <= pwr_up_cnt + 1; + end + end + +endmodule diff --git a/projects/ad9081_fmca_ebz_x_band/zcu102/xband_constr.xdc b/projects/ad9081_fmca_ebz_x_band/zcu102/xband_constr.xdc new file mode 100644 index 000000000..b52788a46 --- /dev/null +++ b/projects/ad9081_fmca_ebz_x_band/zcu102/xband_constr.xdc @@ -0,0 +1,40 @@ + +set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports pmod0_0_1_PA_ON ]; ## J55.1 +set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports pmod0_1_3_MOSI ]; ## J55.3 +set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS33 } [get_ports pmod0_2_5_MISO ]; ## J55.5 +set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS33 } [get_ports pmod0_3_7_SCLK ]; ## J55.7 +set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS33 } [get_ports pmod0_4_2_TR ]; ## J55.2 +set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS33 } [get_ports pmod0_5_4_TX_LOAD ]; ## J55.4 +set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS33 } [get_ports pmod0_6_6_RX_LOAD ]; ## J55.6 +set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS33 } [get_ports pmod0_7_8_SCL ]; ## J55.8 +set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS33 } [get_ports pmod1_0_1_CSB1 ]; ## J87.1 +set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS33 } [get_ports pmod1_1_3_CSB3 ]; ## J87.3 +set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS33 } [get_ports pmod1_2_5_CSB5 ]; ## J87.5 +set_property -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS33 } [get_ports pmod1_3_7_SDA ]; ## J87.7 +set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports pmod1_4_2_CSB2 ]; ## J87.2 +set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports pmod1_5_4_CSB4 ]; ## J87.4 +set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports pmod1_6_6_5V_CTRL ]; ## J87.6 +set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports pmod1_7_8_PWR_UP_DOWN]; ## J87.8 + +# XUD #1 custom break out board + +set_property -dict {PACKAGE_PIN AH2 IOSTANDARD LVCMOS18 } [get_ports fmc_bob_xud1_imu_sclk ]; ## FMC1.C10 IO_L19P_T3L_N0_DBC_AD9P_65 +set_property -dict {PACKAGE_PIN AJ2 IOSTANDARD LVCMOS18 } [get_ports fmc_bob_xud1_imu_mosi ]; ## FMC1.C11 IO_L19N_T3L_N1_DBC_AD9N_65 +set_property -dict {PACKAGE_PIN AH4 IOSTANDARD LVCMOS18 } [get_ports fmc_bob_xud1_gpio0 ]; ## FMC1.C14 IO_L15P_T2L_N4_AD11P_65 +set_property -dict {PACKAGE_PIN AJ4 IOSTANDARD LVCMOS18 } [get_ports fmc_bob_xud1_gpio1 ]; ## FMC1.C15 IO_L15N_T2L_N5_AD11N_65 +set_property -dict {PACKAGE_PIN AH7 IOSTANDARD LVCMOS18 } [get_ports fmc_bob_xud1_imu_miso ]; ## FMC1.C18 IO_L7P_T1L_N0_QBC_AD13P_65 +set_property -dict {PACKAGE_PIN AH6 IOSTANDARD LVCMOS18 } [get_ports fmc_bob_xud1_imu_csb ]; ## FMC1.C19 IO_L7N_T1L_N1_QBC_AD13N_65 +set_property -dict {PACKAGE_PIN U10 IOSTANDARD LVCMOS18 } [get_ports fmc_bob_xud1_imu_rst ]; ## FMC1.C26 IO_L3P_T0L_N4_AD15P_67 +set_property -dict {PACKAGE_PIN AJ6 IOSTANDARD LVCMOS18 } [get_ports fmc_bob_xud1_mosi ]; ## FMC1.D08 IO_L16P_T2U_N6_QBC_AD3P_65 +set_property -dict {PACKAGE_PIN AJ5 IOSTANDARD LVCMOS18 } [get_ports fmc_bob_xud1_csb ]; ## FMC1.D09 IO_L16N_T2U_N7_QBC_AD3N_65 +set_property -dict {PACKAGE_PIN AG3 IOSTANDARD LVCMOS18 } [get_ports fmc_bob_xud1_imu_gpio0 ]; ## FMC1.D11 IO_L20P_T3L_N2_AD1P_65 +set_property -dict {PACKAGE_PIN AH3 IOSTANDARD LVCMOS18 } [get_ports fmc_bob_xud1_imu_gpio1 ]; ## FMC1.D12 IO_L20N_T3L_N3_AD1N_65 +set_property -dict {PACKAGE_PIN AE2 IOSTANDARD LVCMOS18 } [get_ports fmc_bob_xud1_imu_gpio2 ]; ## FMC1.D14 IO_L24P_T3U_N10_PERSTN1_I2C_SDA_65 +set_property -dict {PACKAGE_PIN AE1 IOSTANDARD LVCMOS18 } [get_ports fmc_bob_xud1_imu_gpio3 ]; ## FMC1.D15 IO_L24N_T3U_N11_PERSTN0_65 +set_property -dict {PACKAGE_PIN AE5 IOSTANDARD LVCMOS18 } [get_ports fmc_bob_xud1_sclk ]; ## FMC1.G06 IO_L13P_T2L_N0_GC_QBC_65 +set_property -dict {PACKAGE_PIN AF5 IOSTANDARD LVCMOS18 } [get_ports fmc_bob_xud1_miso ]; ## FMC1.G07 IO_L13N_T2L_N1_GC_QBC_65 +set_property -dict {PACKAGE_PIN AD7 IOSTANDARD LVCMOS18 } [get_ports fmc_bob_xud1_gpio2 ]; ## FMC1.G15 IO_L9P_T1L_N4_AD12P_65 +set_property -dict {PACKAGE_PIN AD6 IOSTANDARD LVCMOS18 } [get_ports fmc_bob_xud1_gpio3 ]; ## FMC1.G16 IO_L9N_T1L_N5_AD12N_65 +set_property -dict {PACKAGE_PIN AG10 IOSTANDARD LVCMOS18 } [get_ports fmc_bob_xud1_gpio4 ]; ## FMC1.G18 IO_L5P_T0U_N8_AD14P_65 +set_property -dict {PACKAGE_PIN AG9 IOSTANDARD LVCMOS18 } [get_ports fmc_bob_xud1_gpio5 ]; ## FMC1.G19 IO_L5N_T0U_N9_AD14N_65 +