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fmcjesdadc1: Updated a5gt design

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Adrian Costina 2015-11-24 15:39:21 +02:00
parent 9281eb2c33
commit fd3910a915
2 changed files with 5 additions and 5 deletions
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8
projects/fmcjesdadc1/a5gt/system_project.tcl
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@ -4,12 +4,12 @@ load_package flow
source ../../scripts/adi_env.tcl
project_new fmcjesdadc1_a5gt -overwrite
source $ad_hdl_dir/projects/common/a5gt/a5gt_system_assign.tcl
file copy -force $ad_hdl_dir/projects/common/a5gt/a5gt_system_bd.qsys .
file copy -force $ad_hdl_dir/projects/fmcjesdadc1/common/fmcjesdadc1_bd.qsys .
source "../../common/a5gt/a5gt_system_assign.tcl"
set_global_assignment -name IP_SEARCH_PATHS "../common/;../../common/a5gt;../../../library/**/*"
set_user_option -name USER_IP_SEARCH_PATHS "../common/;../../common/a5gt/;../../../library/**/*"
set_global_assignment -name QSYS_FILE system_bd.qsys
set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/ad_iobuf.v
set_global_assignment -name VERILOG_FILE "../../../library/common/ad_iobuf.v"
set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v
set_global_assignment -name VERILOG_FILE system_top.v

2
projects/fmcjesdadc1/a5gt/system_top.v
View File

@ -255,7 +255,7 @@ module system_top (
.a5gt_base_sys_spi_MOSI (spi_mosi),
.a5gt_base_sys_spi_SCLK (spi_clk),
.a5gt_base_sys_spi_SS_n (spi_csn),
.rx_data_rx_serial_data (rx_data),
.rx_data_rx_serial_data (rx_data),
.rx_ref_clk_clk (ref_clk),
.rx_sync_rx_sync (rx_sync),
.rx_sysref_rx_ext_sysref_out (rx_sysref),