axi_fmcadc5_sync: rename generated spi clock
Rename the clock so it won't conflict with the main spi clock name.main
parent
1c99fde06b
commit
fd6a395347
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@ -41,6 +41,6 @@ set_false_path -to [get_cells -hier -filter {name =~ *rx_sync_disable_1* && IS_S
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set_false_path -to [get_cells -hier -filter {name =~ *rx_sync_disable_0* && IS_SEQUENTIAL}]
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# Define spi clock
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create_generated_clock -name spi_clk \
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create_generated_clock -name forwarded_spi_clk \
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-source [get_pins -hier up_spi_clk_int_reg/C] \
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-divide_by 2 [get_pins -hier up_spi_clk_int_reg/Q]
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