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axi_clkgen: Add interface definitions for clock inputs/outputs 

Add interface definition for the input and output clocks. This will allow
the tools to recognize them as clocks and enable things like clock
frequency propagation.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-04-20 19:22:23 +02:00
parent 15ce8cc356
commit fdedc9568c
1 changed files with 5 additions and 0 deletions
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5
library/axi_clkgen/axi_clkgen_ip.tcl
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@ -17,6 +17,11 @@ adi_ip_properties axi_clkgen
ipx::remove_bus_interface {clk} [ipx::current_core]
ipx::associate_bus_interfaces -busif s_axi -clock s_axi_aclk [ipx::current_core]
ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface clk2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
set cc [ipx::current_core]
set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]