diff --git a/library/axi_ad5766/axi_ad5766.v b/library/axi_ad5766/axi_ad5766.v index be8e5db7e..f89ee47d0 100644 --- a/library/axi_ad5766/axi_ad5766.v +++ b/library/axi_ad5766/axi_ad5766.v @@ -401,7 +401,7 @@ module axi_ad5766 #( // AXI wrapper up_axi #( - .ADDRESS_WIDTH (14) + .AXI_ADDRESS_WIDTH (16) ) i_up_axi ( .up_rstn (up_rstn), .up_clk (spi_clk), diff --git a/library/axi_ad7616/axi_ad7616.v b/library/axi_ad7616/axi_ad7616.v index 9b6b19652..fea28a83a 100644 --- a/library/axi_ad7616/axi_ad7616.v +++ b/library/axi_ad7616/axi_ad7616.v @@ -96,7 +96,6 @@ module axi_ad7616 #( localparam SERIAL = 0; localparam PARALLEL = 1; localparam NEG_EDGE = 1; - localparam UP_ADDRESS_WIDTH = 14; // internal registers @@ -110,9 +109,9 @@ module axi_ad7616 #( wire up_rstn; wire up_rst; wire up_rreq_s; - wire [(UP_ADDRESS_WIDTH-1):0] up_raddr_s; + wire [13:0] up_raddr_s; wire up_wreq_s; - wire [(UP_ADDRESS_WIDTH-1):0] up_waddr_s; + wire [13:0] up_waddr_s; wire [31:0] up_wdata_s; wire up_wack_if_s; @@ -214,8 +213,7 @@ module axi_ad7616 #( .DATA_WIDTH (8), .NUM_OF_SDI (NUM_OF_SDI), .NUM_OFFLOAD(1), - .MM_IF_TYPE(1), - .UP_ADDRESS_WIDTH (UP_ADDRESS_WIDTH) + .MM_IF_TYPE(1) ) i_axi_spi_engine ( .up_clk (up_clk), .up_rstn (up_rstn), @@ -432,7 +430,7 @@ module axi_ad7616 #( // up bus interface up_axi #( - .ADDRESS_WIDTH (UP_ADDRESS_WIDTH) + .AXI_ADDRESS_WIDTH (16) ) i_up_axi ( .up_rstn (up_rstn), .up_clk (up_clk), diff --git a/library/axi_adc_decimate/axi_adc_decimate.v b/library/axi_adc_decimate/axi_adc_decimate.v index 1baf3279f..f1971cb9f 100644 --- a/library/axi_adc_decimate/axi_adc_decimate.v +++ b/library/axi_adc_decimate/axi_adc_decimate.v @@ -148,8 +148,7 @@ module axi_adc_decimate #( .up_rack (up_rack)); up_axi #( - .AXI_ADDRESS_WIDTH(7), - .ADDRESS_WIDTH(5) + .AXI_ADDRESS_WIDTH(7) ) i_up_axi ( .up_rstn (up_rstn), .up_clk (up_clk), diff --git a/library/axi_adc_trigger/axi_adc_trigger.v b/library/axi_adc_trigger/axi_adc_trigger.v index de3135f04..fa4b11ca3 100644 --- a/library/axi_adc_trigger/axi_adc_trigger.v +++ b/library/axi_adc_trigger/axi_adc_trigger.v @@ -456,8 +456,7 @@ module axi_adc_trigger #( .up_rack(up_rack)); up_axi #( - .AXI_ADDRESS_WIDTH(7), - .ADDRESS_WIDTH(5) + .AXI_ADDRESS_WIDTH(7) ) i_up_axi ( .up_rstn (up_rstn), .up_clk (up_clk), diff --git a/library/axi_dac_interpolate/axi_dac_interpolate.v b/library/axi_dac_interpolate/axi_dac_interpolate.v index d28afdf22..1f67b1f66 100644 --- a/library/axi_dac_interpolate/axi_dac_interpolate.v +++ b/library/axi_dac_interpolate/axi_dac_interpolate.v @@ -171,8 +171,7 @@ module axi_dac_interpolate #( .up_rack (up_rack)); up_axi #( - .AXI_ADDRESS_WIDTH(7), - .ADDRESS_WIDTH(5) + .AXI_ADDRESS_WIDTH(7) ) i_up_axi ( .up_rstn (up_rstn), .up_clk (up_clk), diff --git a/library/axi_dmac/axi_dmac_regmap.v b/library/axi_dmac/axi_dmac_regmap.v index a87ff5a64..4a180140f 100644 --- a/library/axi_dmac/axi_dmac_regmap.v +++ b/library/axi_dmac/axi_dmac_regmap.v @@ -261,8 +261,7 @@ axi_dmac_regmap_request #( ); up_axi #( - .AXI_ADDRESS_WIDTH (12), - .ADDRESS_WIDTH (9) + .AXI_ADDRESS_WIDTH (12) ) i_up_axi ( .up_rstn(s_axi_aresetn), .up_clk(s_axi_aclk), diff --git a/library/axi_fan_control/axi_fan_control.v b/library/axi_fan_control/axi_fan_control.v index 43e560aa3..caab1b20f 100644 --- a/library/axi_fan_control/axi_fan_control.v +++ b/library/axi_fan_control/axi_fan_control.v @@ -183,7 +183,7 @@ assign up_irq_source_clear = (up_wreq_s == 1'b1 && up_waddr_s == 8'h11) ? up_wda assign counter_resetn = (pwm_change_done ) ? (!tacho_edge_det) : ((!pwm_change_done) & (!counter_overflow)); up_axi #( - .ADDRESS_WIDTH(8)) + .AXI_ADDRESS_WIDTH(10)) i_up_axi ( .up_rstn (s_axi_aresetn), .up_clk (up_clk), diff --git a/library/axi_logic_analyzer/axi_logic_analyzer.v b/library/axi_logic_analyzer/axi_logic_analyzer.v index 23493d2e9..87123d2ff 100644 --- a/library/axi_logic_analyzer/axi_logic_analyzer.v +++ b/library/axi_logic_analyzer/axi_logic_analyzer.v @@ -350,8 +350,7 @@ module axi_logic_analyzer ( // axi interface up_axi #( - .AXI_ADDRESS_WIDTH(7), - .ADDRESS_WIDTH(5) + .AXI_ADDRESS_WIDTH(7) ) i_up_axi ( .up_rstn (up_rstn), .up_clk (up_clk), diff --git a/library/axi_pulse_gen/axi_pulse_gen.v b/library/axi_pulse_gen/axi_pulse_gen.v index f4c679d0d..1a7049b39 100644 --- a/library/axi_pulse_gen/axi_pulse_gen.v +++ b/library/axi_pulse_gen/axi_pulse_gen.v @@ -132,7 +132,7 @@ module axi_pulse_gen #( .pulse (pulse)); up_axi #( - .ADDRESS_WIDTH(14)) + .AXI_ADDRESS_WIDTH(16)) i_up_axi ( .up_rstn (up_rstn), .up_clk (up_clk), diff --git a/library/common/up_axi.v b/library/common/up_axi.v index 59f1f42fc..4ea460241 100644 --- a/library/common/up_axi.v +++ b/library/common/up_axi.v @@ -37,7 +37,6 @@ module up_axi #( - parameter ADDRESS_WIDTH = 14, parameter AXI_ADDRESS_WIDTH = 16) ( // reset and clocks @@ -76,6 +75,10 @@ module up_axi #( input [31:0] up_rdata, input up_rack); + // local parameters + + localparam ADDRESS_WIDTH = AXI_ADDRESS_WIDTH - 2; + // internal registers reg up_axi_awready_int = 'd0; diff --git a/library/intel/axi_adxcvr/axi_adxcvr.v b/library/intel/axi_adxcvr/axi_adxcvr.v index d16557a0e..5b4c3e6d2 100644 --- a/library/intel/axi_adxcvr/axi_adxcvr.v +++ b/library/intel/axi_adxcvr/axi_adxcvr.v @@ -123,7 +123,6 @@ module axi_adxcvr #( .up_rack (up_rack)); up_axi #( - .ADDRESS_WIDTH (10), .AXI_ADDRESS_WIDTH (12) ) i_axi ( .up_rstn (up_rstn), diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v index 1a831c13a..09cd10036 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v @@ -133,8 +133,7 @@ module ad_ip_jesd204_tpl_adc_regmap #( // up bus interface up_axi #( - .AXI_ADDRESS_WIDTH (12), - .ADDRESS_WIDTH (10) + .AXI_ADDRESS_WIDTH (12) ) i_up_axi ( .up_clk (up_clk), .up_rstn (up_rstn), diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v index 435a643a7..c675943e2 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v +++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v @@ -120,8 +120,7 @@ module ad_ip_jesd204_tpl_dac_regmap #( // up bus interface up_axi #( - .AXI_ADDRESS_WIDTH (12), - .ADDRESS_WIDTH (10) + .AXI_ADDRESS_WIDTH (12) ) i_up_axi ( .up_clk (up_clk), .up_rstn (up_rstn), diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v index 57b337b0d..d8611f16f 100644 --- a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v +++ b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v @@ -138,8 +138,7 @@ wire up_reset; wire up_reset_synchronizer; up_axi #( - .AXI_ADDRESS_WIDTH (14), - .ADDRESS_WIDTH (12) + .AXI_ADDRESS_WIDTH (14) ) i_up_axi ( .up_rstn(~up_reset), .up_clk(s_axi_aclk), diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v index 006b62f3b..b231dc95c 100644 --- a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v +++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v @@ -137,8 +137,7 @@ wire [4:0] up_irq_trigger; assign up_irq_trigger[4:0] = 5'b00000; up_axi #( - .AXI_ADDRESS_WIDTH (14), - .ADDRESS_WIDTH (12) + .AXI_ADDRESS_WIDTH (14) ) i_up_axi ( .up_rstn(~up_reset), .up_clk(s_axi_aclk), diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine.v b/library/spi_engine/axi_spi_engine/axi_spi_engine.v index 8b8adc95c..793da5ec6 100644 --- a/library/spi_engine/axi_spi_engine/axi_spi_engine.v +++ b/library/spi_engine/axi_spi_engine/axi_spi_engine.v @@ -42,7 +42,6 @@ module axi_spi_engine #( parameter SDO_FIFO_ADDRESS_WIDTH = 5, parameter SDI_FIFO_ADDRESS_WIDTH = 5, parameter MM_IF_TYPE = 0, - parameter UP_ADDRESS_WIDTH = 14, parameter ASYNC_SPI_CLK = 0, parameter NUM_OFFLOAD = 0, parameter OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = 4, @@ -80,11 +79,11 @@ module axi_spi_engine #( input up_clk, input up_rstn, input up_wreq, - input [(UP_ADDRESS_WIDTH-1):0] up_waddr, + input [13:0] up_waddr, input [31:0] up_wdata, output up_wack, input up_rreq, - input [(UP_ADDRESS_WIDTH-1):0] up_raddr, + input [13:0] up_raddr, output [31:0] up_rdata, output up_rack, @@ -165,8 +164,8 @@ module axi_spi_engine #( wire up_wreq_s; wire up_rreq_s; wire [31:0] up_wdata_s; - wire [(UP_ADDRESS_WIDTH-1):0] up_waddr_s; - wire [(UP_ADDRESS_WIDTH-1):0] up_raddr_s; + wire [13:0] up_waddr_s; + wire [13:0] up_raddr_s; // Scratch register reg [31:0] up_scratch = 'h00; @@ -184,7 +183,7 @@ module axi_spi_engine #( // interface wrapper up_axi #( - .ADDRESS_WIDTH (UP_ADDRESS_WIDTH) + .AXI_ADDRESS_WIDTH (16) ) i_up_axi ( .up_rstn(rstn), .up_clk(clk), diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr.v b/library/xilinx/axi_adxcvr/axi_adxcvr.v index 36499bbeb..cef8a47c8 100644 --- a/library/xilinx/axi_adxcvr/axi_adxcvr.v +++ b/library/xilinx/axi_adxcvr/axi_adxcvr.v @@ -1927,7 +1927,7 @@ module axi_adxcvr #( .up_rdata (up_rdata), .up_rack (up_rack)); - up_axi #(.ADDRESS_WIDTH (10)) i_axi ( + up_axi #(.AXI_ADDRESS_WIDTH (12)) i_axi ( .up_rstn (up_rstn), .up_clk (up_clk), .up_axi_awvalid (s_axi_awvalid), diff --git a/library/xilinx/axi_xcvrlb/axi_xcvrlb.v b/library/xilinx/axi_xcvrlb/axi_xcvrlb.v index 11e710f3b..03ede9a4b 100644 --- a/library/xilinx/axi_xcvrlb/axi_xcvrlb.v +++ b/library/xilinx/axi_xcvrlb/axi_xcvrlb.v @@ -165,7 +165,7 @@ module axi_xcvrlb #( end endgenerate - up_axi #(.ADDRESS_WIDTH (8)) i_axi ( + up_axi #(.AXI_ADDRESS_WIDTH (10)) i_axi ( .up_rstn (up_rstn), .up_clk (up_clk), .up_axi_awvalid (s_axi_awvalid),