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axi_ad9671: Updated synchronization mechanism to have a software defined starting code

main
Adrian Costina 2014-10-22 13:10:28 +03:00
parent 121a416916
commit fe92b8b210
2 changed files with 59 additions and 23 deletions
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38
library/axi_ad9671/axi_ad9671.v
View File

@ -1,9 +1,9 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
//
// All rights reserved.
//
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
@ -21,16 +21,16 @@
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
@ -41,7 +41,7 @@
module axi_ad9671 (
// jesd interface
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
@ -56,6 +56,8 @@ module axi_ad9671 (
adc_data,
adc_dovf,
adc_dunf,
adc_sync_in,
adc_sync_out,
adc_raddr_in,
adc_raddr_out,
@ -89,7 +91,7 @@ module axi_ad9671 (
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
// jesd interface
// jesd interface
// rx_clk is the jesd clock (ref_clk/2)
input rx_clk;
@ -104,6 +106,8 @@ module axi_ad9671 (
output [127:0] adc_data;
input adc_dovf;
input adc_dunf;
input adc_sync_in;
output adc_sync_out;
input [ 3:0] adc_raddr_in;
output [ 3:0] adc_raddr_out;
@ -149,6 +153,7 @@ module axi_ad9671 (
// internal signals
wire adc_status_s;
wire adc_sync_status_s;
wire adc_valid_s;
wire [ 15:0] adc_data_s[7:0];
wire [ 7:0] adc_or_s;
@ -163,6 +168,8 @@ module axi_ad9671 (
wire [ 31:0] up_rdata_s[8:0];
wire up_rack_s[8:0];
wire up_wack_s[8:0];
wire [ 31:0] adc_start_code;
wire adc_sync;
// signal name changes
@ -194,7 +201,10 @@ module axi_ad9671 (
// main (device interface)
axi_ad9671_if #(.PCORE_4L_2L_N(PCORE_4L_2L_N), .PCORE_ID(PCORE_ID)) i_if (
axi_ad9671_if #(
.PCORE_4L_2L_N(PCORE_4L_2L_N),
.PCORE_ID(PCORE_ID)
) i_if (
.rx_clk (rx_clk),
.rx_data (rx_data),
.rx_data_sof (rx_data_sof),
@ -217,6 +227,11 @@ module axi_ad9671 (
.adc_or_g (adc_or_s[6]),
.adc_data_h (adc_data_s[7]),
.adc_or_h (adc_or_s[7]),
.adc_start_code (adc_start_code),
.adc_sync (adc_sync),
.adc_sync_in (adc_sync_in),
.adc_sync_out (adc_sync_out),
.adc_sync_status (adc_sync_status_s),
.adc_status (adc_status_s),
.adc_raddr_in(adc_raddr_in),
.adc_raddr_out(adc_raddr_out));
@ -253,13 +268,18 @@ module axi_ad9671 (
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
up_adc_common #(
.PCORE_ID(PCORE_ID)
) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_start_code (adc_start_code),
.adc_sync (adc_sync),
.adc_sync_status (adc_sync_status_s),
.adc_status (adc_status_s),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),

44
library/axi_ad9671/axi_ad9671_if.v
View File

@ -70,6 +70,11 @@ module axi_ad9671_if (
adc_or_g,
adc_data_h,
adc_or_h,
adc_start_code,
adc_sync_in,
adc_sync_out,
adc_sync,
adc_sync_status,
adc_status,
adc_raddr_in,
adc_raddr_out);
@ -107,6 +112,11 @@ module axi_ad9671_if (
output adc_or_g;
output [ 15:0] adc_data_h;
output adc_or_h;
input [ 31:0] adc_start_code;
input adc_sync_in;
output adc_sync_out;
input adc_sync;
output adc_sync_status;
output adc_status;
input [ 3:0] adc_raddr_in;
output [ 3:0] adc_raddr_out;
@ -124,13 +134,14 @@ module axi_ad9671_if (
wire [ 15:0] adc_data_g_s;
wire [ 15:0] adc_data_h_s;
wire [ 3:0] adc_raddr_s;
wire adc_sync_s;
// internal registers
reg int_valid = 'd0;
reg [127:0] int_data = 'd0;
reg adc_status = 'd0;
reg adc_start = 'd0;
reg adc_sync_status = 'd0;
reg [ 3:0] adc_waddr = 'd0;
reg [ 3:0] adc_raddr_out = 'd0;
@ -146,7 +157,8 @@ module axi_ad9671_if (
// adc clock & valid
assign adc_clk = rx_clk;
assign adc_valid = int_valid & adc_start;
assign adc_valid = int_valid;
assign adc_sync_out = adc_sync;
assign adc_or_a = 'd0;
assign adc_or_b = 'd0;
@ -170,9 +182,9 @@ module axi_ad9671_if (
adc_data_d_s, adc_data_c_s, adc_data_b_s, adc_data_a_s};
assign adc_raddr_s = (PCORE_ID == 0) ? adc_raddr_out : adc_raddr_in;
assign adc_sync_s = (PCORE_ID == 0) ? adc_sync_out : adc_sync_in;
always @(posedge rx_clk)
begin
always @(posedge rx_clk) begin
adc_data_a <= adc_rdata[ 15: 0];
adc_data_b <= adc_rdata[ 31: 16];
adc_data_c <= adc_rdata[ 47: 32];
@ -185,17 +197,21 @@ module axi_ad9671_if (
always @(posedge rx_clk) begin
if (adc_rst == 1'b1) begin
adc_waddr <= 4'h0;
adc_raddr_out <= 4'h8;
adc_start <= 1'b0;
end
else begin
if (int_valid == 1'b1 && adc_data_a_s == 16'hbeef) begin
adc_start <= 1'b1;
adc_waddr <= 4'h0;
adc_raddr_out <= 4'h8;
adc_sync_status <= 1'b0;
end else begin
if (adc_data_a_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin
adc_sync_status <= 1'b0;
end else if(adc_sync_s == 1'b1) begin
adc_sync_status <= 1'b1;
end
if (int_valid == 1'b1 && adc_start == 1'b1) begin
adc_waddr <= adc_waddr + 1;
adc_raddr_out <= adc_raddr_out + 1;
if (adc_data_a_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin
adc_waddr <= 4'h0;
adc_raddr_out <= 4'h8;
end else if (int_valid == 1'b1) begin
adc_waddr <= adc_waddr + 1;
adc_raddr_out <= adc_raddr_out + 1;
end
end
end