Merge branch 'hdl_2014_r2'
Adrian Costina
commit
fe9601643d
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@ -47,7 +47,6 @@ module axi_mc_controller
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// physical interface
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input fmc_m1_fault_i,
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output fmc_m1_en_o,
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output pwm_ah_o,
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output pwm_al_o,
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@ -55,7 +54,7 @@ module axi_mc_controller
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output pwm_bl_o,
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output pwm_ch_o,
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output pwm_cl_o,
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output [7:0] gpo_o,
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output [3:0] gpo_o,
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// controller connections
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@ -77,11 +76,9 @@ module axi_mc_controller
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output[1:0] sensors_o,
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input [2:0] position_i,
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// dma interface
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// channel interface
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output adc_clk_o,
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input adc_dovf_i,
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input adc_dunf_i,
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output adc_enable_c0,
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output adc_enable_c1,
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output adc_enable_c2,
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@ -137,13 +134,10 @@ module axi_mc_controller
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//------------------------------------------------------------------------------
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// internal registers
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reg adc_valid = 'd0;
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reg [31:0] adc_data = 'd0;
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reg [31:0] up_rdata = 'd0;
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reg up_wack = 'd0;
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reg up_rack = 'd0;
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reg pwm_gen_clk = 'd0;
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reg one_chan_reg = 'd0;
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reg [31:0] up_rdata = 'd0;
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reg up_wack = 'd0;
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reg up_rack = 'd0;
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reg pwm_gen_clk = 'd0;
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//------------------------------------------------------------------------------
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//----------- Wires Declarations -----------------------------------------------
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@ -196,16 +190,12 @@ wire star_delta_s;
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wire dir_s;
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wire [10:0] pwm_open_s;
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wire [10:0] pwm_s;
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wire [10:0] gpo_s;
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wire dpwm_ah_s;
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wire dpwm_al_s;
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wire dpwm_bh_s;
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wire dpwm_bl_s;
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wire dpwm_ch_s;
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wire dpwm_cl_s;
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wire foc_ctrl_s;
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//------------------------------------------------------------------------------
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@ -237,7 +227,6 @@ assign adc_data_c5 = ctrl_data5_i;
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assign adc_data_c6 = ctrl_data6_i;
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assign adc_data_c7 = ctrl_data7_i;
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assign ctrl_rst_o = !run_s;
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// monitor signals
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@ -252,11 +241,6 @@ assign pwm_bl_o = foc_ctrl_s ? pwm_b_i : dpwm_bl_s;
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assign pwm_ch_o = foc_ctrl_s ? !pwm_c_i : dpwm_ch_s;
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assign pwm_cl_o = foc_ctrl_s ? pwm_c_i : dpwm_cl_s;
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// assign gpo
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assign gpo_o[7:4] = gpo_s[10:7];
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assign gpo_o[3:0] = gpo_s[3:0];
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// clock generation
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always @(posedge ref_clk)
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@ -264,7 +248,6 @@ begin
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pwm_gen_clk <= ~pwm_gen_clk; // generate 50 MHz clk
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end
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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@ -284,7 +267,7 @@ end
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motor_driver
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#( .PWM_BITS(11))
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motor_driver_inst(
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.clk_i(ref_clk),
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.clk_i(ctrl_data_clk),
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.pwm_clk_i(pwm_gen_clk),
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.rst_n_i(up_rstn) ,
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.run_i(run_s),
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@ -322,7 +305,7 @@ control_registers control_reg_inst(
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.kp1_o(),
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.ki1_o(),
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.kd1_o(),
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.gpo_o(gpo_s),
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.gpo_o(gpo_o),
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.reference_speed_o(),
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.oloop_matlab_o(foc_ctrl_s),
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.err_i(),
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@ -707,9 +690,9 @@ up_adc_common i_up_adc_common(
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.adc_ddr_edgesel(),
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.adc_pin_mode(),
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.adc_status(1'b1),
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.adc_sync_status(1'b0),
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.adc_status_ovf(adc_dovf_i),
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.adc_status_unf(adc_dunf_i),
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.adc_sync_status(1'b1),
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.adc_status_ovf(),
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.adc_status_unf(),
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.adc_clk_ratio(32'd1),
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.adc_start_code(),
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.adc_sync(),
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@ -735,7 +718,7 @@ up_adc_common i_up_adc_common(
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.drp_ready(1'b0),
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.drp_locked(1'b0),
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.up_usr_chanmax(),
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.adc_usr_chanmax(8'd0),
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.adc_usr_chanmax(8'd7),
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.up_adc_gpio_in(32'h0),
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.up_adc_gpio_out(),
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.up_rstn (up_rstn),
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@ -784,4 +767,3 @@ endmodule
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// ***************************************************************************
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// ***************************************************************************
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@ -17,6 +17,7 @@ adi_ip_files axi_mc_controller [list \
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"$ad_hdl_dir/library/common/up_adc_common.v" \
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"$ad_hdl_dir/library/common/up_adc_channel.v" \
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"motor_driver.v" \
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"delay.v" \
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"control_registers.v" \
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"axi_mc_controller.v" ]
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@ -66,8 +66,8 @@ module control_registers
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output break_o,
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output dir_o,
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output star_delta_o,
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output [1:0] sensors_o,
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output [10:0] gpo_o,
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output [ 1:0] sensors_o,
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output [ 3:0] gpo_o,
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output oloop_matlab_o,
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output calibrate_adcs_o
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);
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@ -96,8 +96,6 @@ reg [10:0] gpo_r;
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//----------- Wires Declarations -----------------------------------------------
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//------------------------------------------------------------------------------
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//internal signals
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wire up_wreq_s;
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wire up_rreq_s;
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@ -115,7 +113,7 @@ assign star_delta_o = control_r[4]; // Select between star [0] o
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assign sensors_o = control_r[9:8]; // Select between Hall[00] and BEMF[01] sensors
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assign calibrate_adcs_o = control_r[16];
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assign oloop_matlab_o = control_r[12]; // Select between open loop control [0] and matlab control [1]
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assign gpo_o = control_r[30:20];
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assign gpo_o = control_r[23:20];
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assign pwm_open_o = pwm_open_r[10:0]; // PWM value, for open loop control
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assign reference_speed_o = reference_speed_r;
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@ -0,0 +1,80 @@
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// -----------------------------------------------------------------------------
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//
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// Copyright 2014(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
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// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
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// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// -----------------------------------------------------------------------------
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// FILE NAME : delay.v
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// MODULE NAME : debouncer
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// AUTHOR : ACozma
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// AUTHOR’S EMAIL : andrei.cozma@analog.com
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//
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// -----------------------------------------------------------------------------
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`timescale 1ns / 1ps
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module delay
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//----------- Parameters Declarations -------------------------------------------
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#(
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parameter DELAY = 128
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)
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//----------- Ports Declarations -----------------------------------------------
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(
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input clk_i,
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input rst_n_i,
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input sig_i,
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output reg sig_o
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);
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//------------------------------------------------------------------------------
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//----------- Registers Declarations -------------------------------------------
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//------------------------------------------------------------------------------
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reg [DELAY-1:0] shift_reg;
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//------------------------------------------------------------------------------
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//----------- Assign/Always Blocks ---------------------------------------------
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//------------------------------------------------------------------------------
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always @(posedge clk_i)
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begin
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if(rst_n_i == 0)
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begin
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shift_reg <= 0;
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sig_o <= 0;
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end
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else
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begin
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shift_reg <= {shift_reg[DELAY-2:0], sig_i};
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sig_o <= shift_reg[DELAY-1];
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end
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end
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endmodule
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@ -90,6 +90,19 @@ wire align_complete;
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wire [PWMBW:0] pwm_duty_s;
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wire [1:0] commutation_table[0:2];
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wire pwm_al_s;
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wire pwm_ah_s;
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wire pwm_bl_s;
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wire pwm_bh_s;
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wire pwm_cl_s;
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wire pwm_ch_s;
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wire pwmd_al_s;
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wire pwmd_ah_s;
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wire pwmd_bl_s;
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wire pwmd_bh_s;
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wire pwmd_cl_s;
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wire pwmd_ch_s;
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//------------------------------------------------------------------------------
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//----------- Local Parameters -------------------------------------------------
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//------------------------------------------------------------------------------
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@ -97,9 +110,10 @@ wire [1:0] commutation_table[0:2];
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localparam OFF = 3'b001;
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localparam ALIGN = 3'b010;
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localparam RUN = 3'b100;
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localparam DT = 20;
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localparam [PWMBW:0] ALIGN_PWM_DUTY = 2**(PWMBW) + 2**(PWMBW-3);
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localparam [15:0] ALIGN_TIME = 16'h4000;
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localparam [15:0] ALIGN_TIME = 16'h8000;
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localparam [1:0] COMMUTATION_TABLE_DELTA_CW_0[0:5] = { 2'd1,-2'd1, 2'd1,-2'd1, 2'd1,-2'd1};
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@ -116,6 +130,51 @@ localparam [1:0] COMMUTATION_TABLE_STAR_CCW_0[0:5] = {-2'd1, 2'd1, 2'd0, 2'd0,
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localparam [1:0] COMMUTATION_TABLE_STAR_CCW_1[0:5] = { 2'd0,-2'd1,-2'd1, 2'd1, 2'd1, 2'd0};
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localparam [1:0] COMMUTATION_TABLE_STAR_CCW_2[0:5] = { 2'd1, 2'd0, 2'd1,-2'd1, 2'd0,-2'd1};
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delay #(
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.DELAY(DT))
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delay_ah_i (
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.clk_i (clk_i),
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.rst_n_i (pwm_ah_s),
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.sig_i (pwm_ah_s),
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.sig_o (pwmd_ah_s));
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delay #(
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.DELAY(DT))
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delay_al_i (
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.clk_i (clk_i),
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.rst_n_i (pwm_al_s),
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.sig_i (pwm_al_s),
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.sig_o (pwmd_al_s));
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delay #(
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.DELAY(DT))
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delay_bh_i (
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.clk_i (clk_i),
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.rst_n_i (pwm_bh_s),
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.sig_i (pwm_bh_s),
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.sig_o (pwmd_bh_s));
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delay #(
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.DELAY(DT))
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delay_bl_i (
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.clk_i (clk_i),
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.rst_n_i (pwm_bl_s),
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.sig_i (pwm_bl_s),
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.sig_o (pwmd_bl_s));
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delay #(
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.DELAY(DT))
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delay_ch_i (
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.clk_i (clk_i),
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.rst_n_i (pwm_ch_s),
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.sig_i (pwm_ch_s),
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.sig_o (pwmd_ch_s));
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delay #(
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.DELAY(DT))
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delay_cl_i (
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.clk_i (clk_i),
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.rst_n_i (pwm_cl_s),
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.sig_i (pwm_cl_s),
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.sig_o (pwmd_cl_s));
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//------------------------------------------------------------------------------
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//----------- Assign/Always Blocks ---------------------------------------------
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//------------------------------------------------------------------------------
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@ -136,14 +195,23 @@ assign commutation_table[2] = star_delta_i ?
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//Motor Phases Control
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assign AH_o = commutation_table[0] == 2'd1 ? ~pwm_s : commutation_table[0] == -2'd1 ? pwm_s : 1;
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assign AL_o = commutation_table[0] == 2'd1 ? pwm_s : commutation_table[0] == -2'd1 ? ~pwm_s : 1;
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assign pwm_ah_s = commutation_table[0] == 2'd1 ? ~pwm_s : commutation_table[0] == -2'd1 ? pwm_s : 0;
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assign pwm_al_s = commutation_table[0] == 2'd1 ? pwm_s : commutation_table[0] == -2'd1 ? ~pwm_s : 0;
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assign BH_o = commutation_table[1] == 2'd1 ? ~pwm_s : commutation_table[1] == -2'd1 ? pwm_s : 1;
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assign BL_o = commutation_table[1] == 2'd1 ? pwm_s : commutation_table[1] == -2'd1 ? ~pwm_s : 1;
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assign pwm_bh_s = commutation_table[1] == 2'd1 ? ~pwm_s : commutation_table[1] == -2'd1 ? pwm_s : 0;
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assign pwm_bl_s = commutation_table[1] == 2'd1 ? pwm_s : commutation_table[1] == -2'd1 ? ~pwm_s : 0;
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assign CH_o = commutation_table[2] == 2'd1 ? ~pwm_s : commutation_table[2] == -2'd1 ? pwm_s : 1;
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assign CL_o = commutation_table[2] == 2'd1 ? pwm_s : commutation_table[2] == -2'd1 ? ~pwm_s : 1;
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assign pwm_ch_s = commutation_table[2] == 2'd1 ? ~pwm_s : commutation_table[2] == -2'd1 ? pwm_s : 0;
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assign pwm_cl_s = commutation_table[2] == 2'd1 ? pwm_s : commutation_table[2] == -2'd1 ? ~pwm_s : 0;
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assign AL_o = pwmd_ah_s? 0 : pwmd_al_s;
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assign AH_o = pwmd_ah_s;
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assign BL_o = pwmd_bh_s ? 0 : pwmd_bl_s;
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assign BH_o = pwmd_bh_s;
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assign CL_o = pwmd_ch_s ? 0 : pwmd_cl_s;
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assign CH_o = pwmd_ch_s;
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//Control the current motor state
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always @(posedge clk_i)
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|
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@ -77,8 +77,7 @@ module ad7401
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output reg adc_status_o,
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//AD7401 control and data interface
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input adc_mdata_i, // AD7401 MDAT pin
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output adc_mclkin_o // AD7401 MCLKIN pin
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input adc_mdata_i // AD7401 MDAT pin
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);
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//------------------------------------------------------------------------------
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@ -113,7 +112,6 @@ localparam WAIT_DATA_RDY_LOW_STATE = 5'b10000;
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//------------------------------------------------------------------------------
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//----------- Assign/Always Blocks ---------------------------------------------
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//------------------------------------------------------------------------------
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assign adc_mclkin_o = adc_clk_i; // use clock signal for driver and for ADC
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// synchronize data on fpga_clki
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always @(posedge fpga_clk_i)
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|
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@ -37,8 +37,7 @@
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`timescale 1ns/100ps
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module axi_mc_current_monitor
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#(
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module axi_mc_current_monitor #(
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parameter C_S_AXI_MIN_SIZE = 32'hffff
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)
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(
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@ -46,30 +45,22 @@ module axi_mc_current_monitor
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// physical interface
|
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input adc_ia_dat_i,
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output adc_ia_clk_o,
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output adc_enable_ia,
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input adc_ib_dat_i,
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output adc_ib_clk_o,
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input adc_it_dat_i,
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output adc_it_clk_o,
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output adc_enable_ib,
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input adc_vbus_dat_i,
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output adc_vbus_clk_o,
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output adc_enable_vbus,
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output adc_enable_stub,
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output adc_clk_o,
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input ref_clk,
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input adc_clk_i,
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output [17:0] ia_o,
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output [17:0] ib_o,
|
||||
output [17:0] it_o,
|
||||
output [15:0] ia_o,
|
||||
output [15:0] ib_o,
|
||||
output [15:0] vbus_o,
|
||||
output i_ready_o,
|
||||
|
||||
// dma interface
|
||||
|
||||
output adc_clk_o,
|
||||
output adc_dwr_o,
|
||||
output [63:0] adc_ddata_o,
|
||||
output adc_dsync_o,
|
||||
input adc_dovf_i,
|
||||
input adc_dunf_i,
|
||||
|
||||
// axi interface
|
||||
|
||||
input s_axi_aclk,
|
||||
|
|
@ -90,40 +81,16 @@ module axi_mc_current_monitor
|
|||
output s_axi_rvalid,
|
||||
output [1:0] s_axi_rresp,
|
||||
output [31:0] s_axi_rdata,
|
||||
input s_axi_rready,
|
||||
|
||||
// debug signals
|
||||
|
||||
output adc_mon_valid,
|
||||
output [31:0] adc_mon_data
|
||||
input s_axi_rready
|
||||
);
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
//----------- Registers Declarations -------------------------------------------
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
reg adc_valid = 'd0;
|
||||
reg [63:0] adc_data = 'd0;
|
||||
reg [47:0] adc_data_3 = 'd0;
|
||||
reg [31:0] up_rdata = 'd0;
|
||||
reg up_wack = 'd0;
|
||||
reg up_rack = 'd0;
|
||||
reg [1:0] adc_data_cnt = 'd0;
|
||||
reg [9:0] adc_clk_cnt = 'd0; // used to generate 10 MHz clock for ADCs
|
||||
reg adc_clk_reg = 'd0; // used to generate 10 MHz clock for ADCs
|
||||
|
||||
reg acq_run_reg = 'd0; // register used for synchronizing data acquisition
|
||||
reg adc_valid_3 = 'd0;
|
||||
reg [47:0] adc_data_3_1110 = 'd0;
|
||||
reg [47:0] adc_data_3_1101 = 'd0;
|
||||
reg [47:0] adc_data_3_1011 = 'd0;
|
||||
reg [47:0] adc_data_3_0111 = 'd0;
|
||||
reg [63:0] adc_data_1110 = 'd0;
|
||||
reg [63:0] adc_data_1101 = 'd0;
|
||||
reg [63:0] adc_data_1011 = 'd0;
|
||||
reg [63:0] adc_data_0111 = 'd0;
|
||||
reg adc_dsync_r_3 = 'd0;
|
||||
reg adc_dsync_r = 'd0;
|
||||
reg up_wack = 'd0;
|
||||
reg up_rack = 'd0;
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
//----------- Wires Declarations -----------------------------------------------
|
||||
|
|
@ -148,27 +115,22 @@ wire [31:0] up_rdata_0_s;
|
|||
wire [31:0] up_rdata_1_s;
|
||||
wire [31:0] up_rdata_2_s;
|
||||
wire [31:0] up_rdata_3_s;
|
||||
wire up_ack_0_s;
|
||||
wire up_ack_1_s;
|
||||
wire up_ack_2_s;
|
||||
wire up_ack_3_s;
|
||||
wire up_rack_0_s;
|
||||
wire up_rack_1_s;
|
||||
wire up_rack_2_s;
|
||||
wire up_rack_3_s;
|
||||
wire up_wack_0_s;
|
||||
wire up_wack_1_s;
|
||||
wire up_wack_2_s;
|
||||
wire up_wack_3_s;
|
||||
|
||||
wire adc_status_a_s;
|
||||
wire [15:0] adc_data_ia_s ;
|
||||
wire data_rd_ready_ia_s;
|
||||
wire adc_status_b_s;
|
||||
wire [15:0] adc_data_ib_s;
|
||||
wire adc_status_it_s;
|
||||
wire [15:0] adc_data_it_s;
|
||||
wire [15:0] adc_data_it_n_s;
|
||||
wire adc_status_vbus_s;
|
||||
wire [15:0] adc_data_vbus_s ;
|
||||
wire adc_enable_ia;
|
||||
wire adc_enable_ib;
|
||||
wire adc_enable_it;
|
||||
wire adc_enable_vbus;
|
||||
|
||||
wire adc_clk_s;
|
||||
wire [15:0] adc_data_vbus_s;
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
//----------- Assign/Always Blocks ---------------------------------------------
|
||||
|
|
@ -179,304 +141,17 @@ wire adc_clk_s;
|
|||
assign up_clk = s_axi_aclk;
|
||||
assign up_rstn = s_axi_aresetn;
|
||||
|
||||
assign adc_clk_o = ref_clk; // use reference clock to send data to the dma
|
||||
assign adc_dwr_o = adc_valid;
|
||||
assign adc_ddata_o = adc_data;
|
||||
assign adc_dsync_o = adc_dsync_r;
|
||||
|
||||
// monitor signals
|
||||
|
||||
assign adc_mon_valid = data_rd_ready_ia_s;
|
||||
assign adc_mon_data[15: 0] = adc_data[15:0];
|
||||
assign adc_mon_data[31:16] = {adc_enable_vbus, adc_enable_it, adc_enable_ib, adc_enable_ia, adc_rst, data_rd_ready_ia_s, adc_data_cnt, adc_ia_clk_o, adc_data_ia_s[6:0]};
|
||||
|
||||
// current outputs
|
||||
|
||||
assign i_ready_o = data_rd_ready_ia_s;
|
||||
assign ia_o = {adc_data_ia_s - 16'h7FFF, 2'b00};
|
||||
assign ib_o = {adc_data_ib_s - 16'h7FFF, 2'b00};
|
||||
assign it_o = {adc_data_it_s, 2'b00};
|
||||
assign adc_data_it_n_s = 65535 - adc_data_it_s;
|
||||
assign i_ready_o = data_rd_ready_ia_s;
|
||||
|
||||
assign ia_o = adc_data_ia_s ;
|
||||
assign ib_o = adc_data_ib_s ;
|
||||
assign vbus_o = adc_data_vbus_s;
|
||||
|
||||
// adc clock
|
||||
|
||||
assign adc_clk_s = adc_clk_reg;
|
||||
|
||||
// ADC clock generation
|
||||
|
||||
always @(posedge ref_clk)
|
||||
begin
|
||||
if(adc_clk_cnt < 10'd4)
|
||||
begin
|
||||
adc_clk_cnt <= adc_clk_cnt + 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
adc_clk_cnt <= 10'd0;
|
||||
adc_clk_reg <= ~adc_clk_reg;
|
||||
end
|
||||
end
|
||||
|
||||
// adc channels - dma interface
|
||||
|
||||
always @(posedge ref_clk)
|
||||
begin
|
||||
if(data_rd_ready_ia_s == 1'b1)
|
||||
begin
|
||||
adc_valid_3 <= adc_data_cnt[0] | adc_data_cnt[1];
|
||||
adc_dsync_r_3 <= adc_data_cnt[0] | ~adc_data_cnt[1];
|
||||
adc_data_3_1110[47:32] <= adc_data_vbus_s;
|
||||
adc_data_3_1110[31:16] <= adc_data_it_n_s;
|
||||
adc_data_3_1110[15:0] <= adc_data_ib_s;
|
||||
adc_data_3_1101[47:32] <= adc_data_vbus_s;
|
||||
adc_data_3_1101[31:16] <= adc_data_it_n_s;
|
||||
adc_data_3_1101[15:0] <= adc_data_ia_s;
|
||||
adc_data_3_1011[47:32] <= adc_data_vbus_s;
|
||||
adc_data_3_1011[31:16] <= adc_data_ib_s;
|
||||
adc_data_3_1011[15:0] <= adc_data_ia_s;
|
||||
adc_data_3_0111[47:32] <= adc_data_it_n_s;
|
||||
adc_data_3_0111[31:16] <= adc_data_ib_s;
|
||||
adc_data_3_0111[15:0] <= adc_data_ia_s;
|
||||
case(adc_data_cnt)
|
||||
2'b11:
|
||||
begin
|
||||
adc_data_1110[63:48] <= adc_data_vbus_s;
|
||||
adc_data_1110[47:32] <= adc_data_it_n_s;
|
||||
adc_data_1110[31:16] <= adc_data_ib_s;
|
||||
adc_data_1110[15:0] <= adc_data_3_1110[47:32];
|
||||
adc_data_1101[63:48] <= adc_data_vbus_s;
|
||||
adc_data_1101[47:32] <= adc_data_it_n_s;
|
||||
adc_data_1101[31:16] <= adc_data_ia_s;
|
||||
adc_data_1101[15:0] <= adc_data_3_1101[47:32];
|
||||
adc_data_1011[63:48] <= adc_data_vbus_s;
|
||||
adc_data_1011[47:32] <= adc_data_ib_s;
|
||||
adc_data_1011[31:16] <= adc_data_ia_s;
|
||||
adc_data_1011[15:0] <= adc_data_3_1011[47:32];
|
||||
adc_data_0111[63:48] <= adc_data_it_n_s;
|
||||
adc_data_0111[47:32] <= adc_data_ib_s;
|
||||
adc_data_0111[31:16] <= adc_data_ia_s;
|
||||
adc_data_0111[15:0] <= adc_data_3_0111[47:32];
|
||||
end
|
||||
2'b10:
|
||||
begin
|
||||
adc_data_1110[63:48] <= adc_data_it_n_s;
|
||||
adc_data_1110[47:32] <= adc_data_ib_s;
|
||||
adc_data_1110[31:16] <= adc_data_3_1110[47:32];
|
||||
adc_data_1110[15:0] <= adc_data_3_1110[31:16];
|
||||
adc_data_1101[63:48] <= adc_data_it_n_s;
|
||||
adc_data_1101[47:32] <= adc_data_ia_s;
|
||||
adc_data_1101[31:16] <= adc_data_3_1101[47:32];
|
||||
adc_data_1101[15:0] <= adc_data_3_1101[31:16];
|
||||
adc_data_1011[63:48] <= adc_data_ib_s;
|
||||
adc_data_1011[47:32] <= adc_data_ia_s;
|
||||
adc_data_1011[31:16] <= adc_data_3_1011[47:32];
|
||||
adc_data_1011[15:0] <= adc_data_3_1011[31:16];
|
||||
adc_data_0111[63:48] <= adc_data_ib_s;
|
||||
adc_data_0111[47:32] <= adc_data_ia_s;
|
||||
adc_data_0111[31:16] <= adc_data_3_0111[47:32];
|
||||
adc_data_0111[15:0] <= adc_data_3_0111[31:16];
|
||||
end
|
||||
2'b01:
|
||||
begin
|
||||
adc_data_1110[63:48] <= adc_data_ib_s;
|
||||
adc_data_1110[47:32] <= adc_data_3_1110[47:32];
|
||||
adc_data_1110[31:16] <= adc_data_3_1110[31:16];
|
||||
adc_data_1110[15:0] <= adc_data_3_1110[15:0];
|
||||
adc_data_1101[63:48] <= adc_data_ia_s;
|
||||
adc_data_1101[47:32] <= adc_data_3_1101[47:32];
|
||||
adc_data_1101[31:16] <= adc_data_3_1101[31:16];
|
||||
adc_data_1101[15:0] <= adc_data_3_1101[15:0];
|
||||
adc_data_1011[63:48] <= adc_data_ia_s;
|
||||
adc_data_1011[47:32] <= adc_data_3_1011[47:32];
|
||||
adc_data_1011[31:16] <= adc_data_3_1011[31:16];
|
||||
adc_data_1011[15:0] <= adc_data_3_1011[15:0];
|
||||
adc_data_0111[63:48] <= adc_data_ia_s;
|
||||
adc_data_0111[47:32] <= adc_data_3_0111[47:32];
|
||||
adc_data_0111[31:16] <= adc_data_3_0111[31:16];
|
||||
adc_data_0111[15:0] <= adc_data_3_0111[15:0];
|
||||
end
|
||||
2'b00:
|
||||
begin
|
||||
adc_data_1110[63:48] <= 16'hdead;
|
||||
adc_data_1110[47:32] <= 16'hdead;
|
||||
adc_data_1110[31:16] <= 16'hdead;
|
||||
adc_data_1110[15:0] <= 16'hdead;
|
||||
adc_data_1101[63:48] <= 16'hdead;
|
||||
adc_data_1101[47:32] <= 16'hdead;
|
||||
adc_data_1101[31:16] <= 16'hdead;
|
||||
adc_data_1101[15:0] <= 16'hdead;
|
||||
adc_data_1011[63:48] <= 16'hdead;
|
||||
adc_data_1011[47:32] <= 16'hdead;
|
||||
adc_data_1011[31:16] <= 16'hdead;
|
||||
adc_data_1011[15:0] <= 16'hdead;
|
||||
adc_data_0111[63:48] <= 16'hdead;
|
||||
adc_data_0111[47:32] <= 16'hdead;
|
||||
adc_data_0111[31:16] <= 16'hdead;
|
||||
adc_data_0111[15:0] <= 16'hdead;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge ref_clk)
|
||||
begin
|
||||
if(data_rd_ready_ia_s == 1'b1)
|
||||
begin
|
||||
case({adc_enable_vbus, adc_enable_it, adc_enable_ib, adc_enable_ia})
|
||||
4'b1111:
|
||||
begin
|
||||
adc_dsync_r <= 1'b1;
|
||||
adc_data_3 <= 48'd0;
|
||||
adc_valid <= 1'b1;
|
||||
adc_data[63:48] <= adc_data_vbus_s;
|
||||
adc_data[47:32] <= adc_data_it_n_s;
|
||||
adc_data[31:16] <= adc_data_ib_s;
|
||||
adc_data[15: 0] <= adc_data_ia_s;
|
||||
end
|
||||
4'b1110:
|
||||
begin
|
||||
adc_dsync_r <= adc_dsync_r_3;
|
||||
adc_valid <= adc_valid_3;
|
||||
adc_data <= adc_data_1110;
|
||||
end
|
||||
4'b1101:
|
||||
begin
|
||||
adc_dsync_r <= adc_dsync_r_3;
|
||||
adc_valid <= adc_valid_3;
|
||||
adc_data <= adc_data_1101;
|
||||
end
|
||||
4'b1100:
|
||||
begin
|
||||
adc_dsync_r <= 1'b1;
|
||||
adc_data_3 <= 48'd0;
|
||||
adc_valid <= adc_data_cnt[0];
|
||||
adc_data[63:48] <= adc_data_vbus_s;
|
||||
adc_data[47:32] <= adc_data_it_n_s;
|
||||
adc_data[31:16] <= adc_data[63:48];
|
||||
adc_data[15: 0] <= adc_data[47:32];
|
||||
end
|
||||
4'b1011:
|
||||
begin
|
||||
adc_dsync_r <= adc_dsync_r_3;
|
||||
adc_valid <= adc_valid_3;
|
||||
adc_data <= adc_data_1011;
|
||||
end
|
||||
4'b1010:
|
||||
begin
|
||||
adc_dsync_r <= 1'b1;
|
||||
adc_data_3 <= 48'd0;
|
||||
adc_valid <= adc_data_cnt[0];
|
||||
adc_data[63:48] <= adc_data_vbus_s;
|
||||
adc_data[47:32] <= adc_data_ib_s;
|
||||
adc_data[31:16] <= adc_data[63:48];
|
||||
adc_data[15: 0] <= adc_data[47:32];
|
||||
end
|
||||
4'b1001:
|
||||
begin
|
||||
adc_dsync_r <= 1'b1;
|
||||
adc_data_3 <= 48'd0;
|
||||
adc_valid <= adc_data_cnt[0];
|
||||
adc_data[63:48] <= adc_data_vbus_s;
|
||||
adc_data[47:32] <= adc_data_ia_s;
|
||||
adc_data[31:16] <= adc_data[63:48];
|
||||
adc_data[15: 0] <= adc_data[47:32];
|
||||
end
|
||||
4'b1000:
|
||||
begin
|
||||
adc_dsync_r <= 1'b1;
|
||||
adc_data_3 <= 48'd0;
|
||||
adc_valid <= adc_data_cnt[1] & adc_data_cnt[0];
|
||||
adc_data[63:48] <= adc_data_vbus_s;
|
||||
adc_data[47:32] <= adc_data[63:48];
|
||||
adc_data[31:16] <= adc_data[47:32];
|
||||
adc_data[15: 0] <= adc_data[31:16];
|
||||
end
|
||||
4'b0111:
|
||||
begin
|
||||
adc_dsync_r <= adc_dsync_r_3;
|
||||
adc_valid <= adc_valid_3;
|
||||
adc_data <= adc_data_0111;
|
||||
end
|
||||
4'b0110:
|
||||
begin
|
||||
adc_dsync_r <= 1'b1;
|
||||
adc_data_3 <= 48'd0;
|
||||
adc_valid <= adc_data_cnt[0];
|
||||
adc_data[63:48] <= adc_data_it_n_s;
|
||||
adc_data[47:32] <= adc_data_ib_s;
|
||||
adc_data[31:16] <= adc_data[63:48];
|
||||
adc_data[15: 0] <= adc_data[47:32];
|
||||
end
|
||||
4'b0101:
|
||||
begin
|
||||
adc_dsync_r <= 1'b1;
|
||||
adc_data_3 <= 48'd0;
|
||||
adc_valid <= adc_data_cnt[0];
|
||||
adc_data[63:48] <= adc_data_it_n_s;
|
||||
adc_data[47:32] <= adc_data_ia_s;
|
||||
adc_data[31:16] <= adc_data[63:48];
|
||||
adc_data[15: 0] <= adc_data[47:32];
|
||||
end
|
||||
4'b0100:
|
||||
begin
|
||||
adc_dsync_r <= 1'b1;
|
||||
adc_data_3 <= 48'd0;
|
||||
adc_valid <= adc_data_cnt[1] & adc_data_cnt[0];
|
||||
adc_data[63:48] <= adc_data_it_n_s;
|
||||
adc_data[47:32] <= adc_data[63:48];
|
||||
adc_data[31:16] <= adc_data[47:32];
|
||||
adc_data[15: 0] <= adc_data[31:16];
|
||||
end
|
||||
4'b0011:
|
||||
begin
|
||||
adc_dsync_r <= 1'b1;
|
||||
adc_data_3 <= 48'd0;
|
||||
adc_valid <= adc_data_cnt[0];
|
||||
adc_data[63:48] <= adc_data_ib_s;
|
||||
adc_data[47:32] <= adc_data_ia_s;
|
||||
adc_data[31:16] <= adc_data[63:48];
|
||||
adc_data[15: 0] <= adc_data[47:32];
|
||||
end
|
||||
4'b0010:
|
||||
begin
|
||||
adc_dsync_r <= 1'b1;
|
||||
adc_data_3 <= 48'd0;
|
||||
adc_valid <= adc_data_cnt[1] & adc_data_cnt[0];
|
||||
adc_data[63:48] <= adc_data_ib_s;
|
||||
adc_data[47:32] <= adc_data[63:48];
|
||||
adc_data[31:16] <= adc_data[47:32];
|
||||
adc_data[15: 0] <= adc_data[31:16];
|
||||
end
|
||||
4'b0001:
|
||||
begin
|
||||
adc_dsync_r <= 1'b1;
|
||||
adc_data_3 <= 48'd0;
|
||||
adc_valid <= adc_data_cnt[1] & adc_data_cnt[0];
|
||||
adc_data[63:48] <= adc_data_ia_s;
|
||||
adc_data[47:32] <= adc_data[63:48];
|
||||
adc_data[31:16] <= adc_data[47:32];
|
||||
adc_data[15: 0] <= adc_data[31:16];
|
||||
end
|
||||
default:
|
||||
begin
|
||||
adc_dsync_r <= 1'b0;
|
||||
adc_data_3 <= 48'd0;
|
||||
adc_valid <= 1'b1;
|
||||
adc_data[63:48] <= 16'hdead;
|
||||
adc_data[47:32] <= 16'hdead;
|
||||
adc_data[31:16] <= 16'hdead;
|
||||
adc_data[15: 0] <= 16'hdead;
|
||||
end
|
||||
endcase
|
||||
adc_data_cnt <= adc_data_cnt + 2'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
adc_valid <= 1'b0;
|
||||
adc_data <= adc_data;
|
||||
adc_data_cnt <= adc_data_cnt;
|
||||
end
|
||||
end
|
||||
assign adc_clk_o = adc_clk_i;
|
||||
|
||||
// processor read interface
|
||||
|
||||
|
|
@ -485,14 +160,14 @@ begin
|
|||
if(up_rstn == 0)
|
||||
begin
|
||||
up_rdata <= 'd0;
|
||||
up_rack <= 'd0;
|
||||
up_wack <= 'd0;
|
||||
up_rack <= 'd0;
|
||||
up_wack <= 'd0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
up_rdata <= up_adc_common_rdata_s | up_rdata_0_s | up_rdata_1_s | up_rdata_2_s | up_rdata_3_s ;
|
||||
up_rack <= up_adc_common_rack_s | up_rack_0_s | up_rack_1_s | up_rack_2_s | up_rack_3_s ;
|
||||
up_wack <= up_adc_common_wack_s | up_wack_0_s | up_wack_1_s | up_wack_2_s | up_wack_3_s ;
|
||||
up_rdata <= up_adc_common_rdata_s | up_rdata_0_s | up_rdata_1_s | up_rdata_2_s |up_rdata_3_s ;
|
||||
up_rack <= up_adc_common_rack_s | up_rack_0_s | up_rack_1_s | up_rack_2_s | up_rack_3_s ;
|
||||
up_wack <= up_adc_common_wack_s | up_wack_0_s | up_wack_1_s | up_wack_2_s | up_wack_3_s;
|
||||
end
|
||||
end
|
||||
|
||||
|
|
@ -500,46 +175,33 @@ end
|
|||
|
||||
ad7401 ia_if(
|
||||
.fpga_clk_i(ref_clk),
|
||||
.adc_clk_i(adc_clk_s),
|
||||
.adc_clk_i(adc_clk_o),
|
||||
.reset_i(adc_rst),
|
||||
.adc_status_o(adc_status_a_s),
|
||||
.data_o(adc_data_ia_s),
|
||||
.data_rd_ready_o(data_rd_ready_ia_s),
|
||||
.adc_mdata_i(adc_ia_dat_i),
|
||||
.adc_mclkin_o(adc_ia_clk_o));
|
||||
.adc_mdata_i(adc_ia_dat_i));
|
||||
|
||||
ad7401 ib_if(
|
||||
.fpga_clk_i(ref_clk),
|
||||
.adc_clk_i(adc_clk_s),
|
||||
.adc_clk_i(adc_clk_o),
|
||||
.reset_i(adc_rst),
|
||||
.adc_status_o(adc_status_b_s),
|
||||
.data_o(adc_data_ib_s),
|
||||
.data_rd_ready_o(),
|
||||
.adc_mdata_i(adc_ib_dat_i),
|
||||
.adc_mclkin_o(adc_ib_clk_o));
|
||||
|
||||
ad7401 it_if(
|
||||
.fpga_clk_i(ref_clk),
|
||||
.adc_clk_i(adc_clk_s),
|
||||
.reset_i(adc_rst),
|
||||
.adc_status_o(adc_status_it_s),
|
||||
.data_o(adc_data_it_s),
|
||||
.data_rd_ready_o(),
|
||||
.adc_mdata_i(adc_it_dat_i),
|
||||
.adc_mclkin_o(adc_it_clk_o));
|
||||
.adc_mdata_i(adc_ib_dat_i));
|
||||
|
||||
ad7401 vbus_if(
|
||||
.fpga_clk_i(ref_clk),
|
||||
.adc_clk_i(adc_clk_s),
|
||||
.adc_clk_i(adc_clk_o),
|
||||
.reset_i(adc_rst),
|
||||
.adc_status_o(adc_status_vbus_s),
|
||||
.data_o(adc_data_vbus_s),
|
||||
.data_rd_ready_o(),
|
||||
.adc_mdata_i(adc_vbus_dat_i),
|
||||
.adc_mclkin_o(adc_vbus_clk_o));
|
||||
.adc_mdata_i(adc_vbus_dat_i));
|
||||
|
||||
up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel_ia(
|
||||
.adc_clk(adc_clk_s),
|
||||
.adc_clk(adc_clk_o),
|
||||
.adc_rst(adc_rst),
|
||||
.adc_enable(adc_enable_ia),
|
||||
.adc_iqcor_enb(),
|
||||
|
|
@ -585,7 +247,7 @@ up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel_ia(
|
|||
.up_rack (up_rack_0_s));
|
||||
|
||||
up_adc_channel #(.PCORE_ADC_CHID(1)) i_up_adc_channel_ib(
|
||||
.adc_clk(adc_clk_s),
|
||||
.adc_clk(adc_clk_o),
|
||||
.adc_rst(adc_rst),
|
||||
.adc_enable(adc_enable_ib),
|
||||
.adc_iqcor_enb(),
|
||||
|
|
@ -628,10 +290,10 @@ up_adc_channel #(.PCORE_ADC_CHID(1)) i_up_adc_channel_ib(
|
|||
.up_rdata (up_rdata_1_s),
|
||||
.up_rack (up_rack_1_s));
|
||||
|
||||
up_adc_channel #(.PCORE_ADC_CHID(2)) i_up_adc_channel_it(
|
||||
.adc_clk(adc_clk_s),
|
||||
up_adc_channel #(.PCORE_ADC_CHID(2)) i_up_adc_channel_vbus(
|
||||
.adc_clk(adc_clk_o),
|
||||
.adc_rst(adc_rst),
|
||||
.adc_enable(adc_enable_it),
|
||||
.adc_enable(adc_enable_vbus),
|
||||
.adc_iqcor_enb(),
|
||||
.adc_dcfilt_enb(),
|
||||
.adc_dfmt_se(),
|
||||
|
|
@ -672,10 +334,10 @@ up_adc_channel #(.PCORE_ADC_CHID(2)) i_up_adc_channel_it(
|
|||
.up_rdata (up_rdata_2_s),
|
||||
.up_rack (up_rack_2_s));
|
||||
|
||||
up_adc_channel #(.PCORE_ADC_CHID(3)) i_up_adc_channel_vbus(
|
||||
.adc_clk(adc_clk_s),
|
||||
up_adc_channel #(.PCORE_ADC_CHID(3)) i_up_adc_channel_stub(
|
||||
.adc_clk(adc_clk_o),
|
||||
.adc_rst(adc_rst),
|
||||
.adc_enable(adc_enable_vbus),
|
||||
.adc_enable(adc_enable_stub),
|
||||
.adc_iqcor_enb(),
|
||||
.adc_dcfilt_enb(),
|
||||
.adc_dfmt_se(),
|
||||
|
|
@ -720,15 +382,15 @@ up_adc_channel #(.PCORE_ADC_CHID(3)) i_up_adc_channel_vbus(
|
|||
|
||||
up_adc_common i_up_adc_common(
|
||||
.mmcm_rst(),
|
||||
.adc_clk(adc_clk_s),
|
||||
.adc_clk(adc_clk_o),
|
||||
.adc_rst(adc_rst),
|
||||
.adc_r1_mode(),
|
||||
.adc_ddr_edgesel(),
|
||||
.adc_pin_mode(),
|
||||
.adc_status(1'b1),
|
||||
.adc_sync_status(1'b0),
|
||||
.adc_status_ovf(adc_dovf_i),
|
||||
.adc_status_unf(adc_dunf_i),
|
||||
.adc_sync_status(1'b1),
|
||||
.adc_status_ovf(),
|
||||
.adc_status_unf(),
|
||||
.adc_clk_ratio(32'd1),
|
||||
.adc_start_code(),
|
||||
.adc_sync(),
|
||||
|
|
@ -758,7 +420,7 @@ up_adc_common i_up_adc_common(
|
|||
.drp_locked(1'b0),
|
||||
|
||||
.up_usr_chanmax(),
|
||||
.adc_usr_chanmax(8'd0),
|
||||
.adc_usr_chanmax(8'd3),
|
||||
.up_adc_gpio_in(32'h0),
|
||||
.up_adc_gpio_out(),
|
||||
|
||||
|
|
@ -808,4 +470,3 @@ endmodule
|
|||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
|
|
|
|||
|
|
@ -39,14 +39,12 @@
|
|||
|
||||
module axi_mc_speed
|
||||
#(
|
||||
parameter C_S_AXI_MIN_SIZE = 32'hffff,
|
||||
parameter MOTOR_CONTROL_REVISION = 2
|
||||
parameter C_S_AXI_MIN_SIZE = 32'hffff
|
||||
)
|
||||
//----------- Ports Declarations -----------------------------------------------
|
||||
(
|
||||
// physical interface
|
||||
input [2:0] position_i,
|
||||
input [2:0] bemf_i,
|
||||
output [2:0] position_o,
|
||||
output [31:0] speed_o,
|
||||
output new_speed_o,
|
||||
|
|
@ -54,16 +52,7 @@ module axi_mc_speed
|
|||
|
||||
input ref_clk,
|
||||
|
||||
// dma interface
|
||||
|
||||
output adc_clk_o,
|
||||
output adc_dwr_o,
|
||||
output [31:0] adc_ddata_o,
|
||||
input adc_dovf_i,
|
||||
input adc_dunf_i,
|
||||
|
||||
// axi interface
|
||||
|
||||
input s_axi_aclk,
|
||||
input s_axi_aresetn,
|
||||
input s_axi_awvalid,
|
||||
|
|
@ -82,19 +71,11 @@ module axi_mc_speed
|
|||
output s_axi_rvalid,
|
||||
output [ 1:0] s_axi_rresp,
|
||||
output [31:0] s_axi_rdata,
|
||||
input s_axi_rready,
|
||||
|
||||
// debug signals
|
||||
|
||||
output adc_mon_valid,
|
||||
output [31:0] adc_mon_data);
|
||||
input s_axi_rready);
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
//----------- Registers Declarations -------------------------------------------
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
reg adc_valid = 'd0;
|
||||
reg [31:0] adc_data = 'd0;
|
||||
reg [31:0] up_rdata = 'd0;
|
||||
reg up_wack = 'd0;
|
||||
reg up_rack = 'd0;
|
||||
|
|
@ -103,14 +84,11 @@ reg up_rack = 'd0;
|
|||
//----------- Wires Declarations -----------------------------------------------
|
||||
//------------------------------------------------------------------------------
|
||||
// internal clocks & resets
|
||||
|
||||
wire adc_rst;
|
||||
wire up_rstn;
|
||||
wire up_clk;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire adc_start_s;
|
||||
wire [31:0] speed_data_s;
|
||||
wire adc_enable_s;
|
||||
wire adc_status_s;
|
||||
|
|
@ -123,45 +101,25 @@ wire [31:0] up_adc_common_rdata_s;
|
|||
wire up_adc_common_wack_s;
|
||||
wire up_adc_common_rack_s;
|
||||
wire [31:0] pid_s;
|
||||
|
||||
wire [ 2:0] position_s;
|
||||
wire [ 2:0] bemf_s;
|
||||
wire [ 2:0] bemf_delayed_s;
|
||||
wire new_speed_s;
|
||||
wire [ 2:0] bemf_multiplex_s;
|
||||
wire [ 2:0] position_s;
|
||||
wire [ 2:0] bemf_s;
|
||||
wire [ 2:0] bemf_delayed_s;
|
||||
wire new_speed_s;
|
||||
wire [ 2:0] bemf_multiplex_s;
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
//----------- Assign/Always Blocks ---------------------------------------------
|
||||
//------------------------------------------------------------------------------
|
||||
// signal name changes
|
||||
|
||||
assign up_clk = s_axi_aclk;
|
||||
assign up_rstn = s_axi_aresetn;
|
||||
|
||||
assign adc_clk_o = ref_clk;
|
||||
assign adc_dwr_o = adc_valid;
|
||||
assign adc_ddata_o = adc_data;
|
||||
|
||||
// monitor signals
|
||||
|
||||
assign adc_mon_valid = new_speed_s;
|
||||
assign adc_mon_data = { 20'h0, bemf_multiplex_s, bemf_s, bemf_delayed_s, position_s };
|
||||
|
||||
assign bemf_multiplex_s =(MOTOR_CONTROL_REVISION == 2) ? position_i : bemf_i;
|
||||
assign bemf_s = position_s ;
|
||||
assign position_o =(hall_bemf_i == 2'b01) ? bemf_delayed_s : position_s;
|
||||
assign new_speed_o = new_speed_s;
|
||||
assign speed_o = speed_data_s;
|
||||
|
||||
// adc channels - dma interface
|
||||
|
||||
always @(posedge ref_clk)
|
||||
begin
|
||||
adc_data <= speed_data_s;
|
||||
adc_valid <= new_speed_s;
|
||||
end
|
||||
|
||||
// processor read interface
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk)
|
||||
begin
|
||||
if(up_rstn == 0)
|
||||
|
|
@ -178,7 +136,6 @@ begin
|
|||
end
|
||||
|
||||
// HALL sensors debouncers
|
||||
|
||||
debouncer
|
||||
#( .DEBOUNCER_LEN(400))
|
||||
position_0(
|
||||
|
|
@ -203,31 +160,6 @@ position_2(
|
|||
.sig_i(position_i[2]),
|
||||
.sig_o(position_s[2]));
|
||||
|
||||
// BEMF debouncer
|
||||
debouncer
|
||||
#( .DEBOUNCER_LEN(400))
|
||||
bemf_0(
|
||||
.clk_i(ref_clk),
|
||||
.rst_i(adc_rst),
|
||||
.sig_i(bemf_multiplex_s[0]),
|
||||
.sig_o(bemf_s[0]));
|
||||
|
||||
debouncer
|
||||
#( .DEBOUNCER_LEN(400))
|
||||
bemf_1(
|
||||
.clk_i(ref_clk),
|
||||
.rst_i(adc_rst),
|
||||
.sig_i(bemf_multiplex_s[1]),
|
||||
.sig_o(bemf_s[1]));
|
||||
|
||||
debouncer
|
||||
#( .DEBOUNCER_LEN(400))
|
||||
bemf_2(
|
||||
.clk_i(ref_clk),
|
||||
.rst_i(adc_rst),
|
||||
.sig_i(bemf_multiplex_s[2]),
|
||||
.sig_o(bemf_s[2]));
|
||||
|
||||
delay_30_degrees delay_30_degrees_i1(
|
||||
.clk_i(ref_clk),
|
||||
.rst_i(adc_rst),
|
||||
|
|
@ -247,8 +179,7 @@ speed_detector_inst(
|
|||
.current_speed_o(),
|
||||
.speed_o(speed_data_s));
|
||||
|
||||
// common processor control
|
||||
|
||||
// common processor control
|
||||
up_adc_common i_up_adc_common(
|
||||
.mmcm_rst(),
|
||||
.adc_clk(ref_clk),
|
||||
|
|
@ -257,9 +188,15 @@ up_adc_common i_up_adc_common(
|
|||
.adc_ddr_edgesel(),
|
||||
.adc_pin_mode(),
|
||||
.adc_status(1'b1),
|
||||
.adc_status_ovf(adc_dovf_i),
|
||||
.adc_status_unf(adc_dunf_i),
|
||||
.adc_sync_status(1'b1),
|
||||
.adc_status_ovf(),
|
||||
.adc_status_unf(),
|
||||
.adc_clk_ratio(32'd1),
|
||||
.adc_start_code(),
|
||||
.adc_sync(),
|
||||
.up_status_pn_err(1'b0),
|
||||
.up_status_pn_oos(1'b0),
|
||||
.up_status_or(1'b0),
|
||||
.delay_clk(1'b0),
|
||||
.delay_rst(),
|
||||
.delay_sel(),
|
||||
|
|
@ -279,8 +216,8 @@ up_adc_common i_up_adc_common(
|
|||
.drp_ready(1'b0),
|
||||
.drp_locked(1'b0),
|
||||
.up_usr_chanmax(),
|
||||
.adc_usr_chanmax(8'd0),
|
||||
.up_adc_gpio_in(),
|
||||
.adc_usr_chanmax(8'd2),
|
||||
.up_adc_gpio_in(32'h0),
|
||||
.up_adc_gpio_out(),
|
||||
.up_rstn(up_rstn),
|
||||
.up_clk(up_clk),
|
||||
|
|
@ -294,7 +231,6 @@ up_adc_common i_up_adc_common(
|
|||
.up_rack (up_adc_common_rack_s));
|
||||
|
||||
// up bus interface
|
||||
|
||||
up_axi i_up_axi(
|
||||
.up_rstn(up_rstn),
|
||||
.up_clk(up_clk),
|
||||
|
|
@ -325,6 +261,5 @@ up_axi i_up_axi(
|
|||
.up_rack (up_rack));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
|
|
|||
|
|
@ -77,6 +77,7 @@ reg [DEBOUNCER_LEN-1:0] shift_reg;
|
|||
//------------------------------------------------------------------------------
|
||||
//----------- Assign/Always Blocks ---------------------------------------------
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
always @(posedge clk_i)
|
||||
begin
|
||||
if(rst_i == 1)
|
||||
|
|
|
|||
|
|
@ -83,12 +83,12 @@ localparam IDLE = 6'b100000;
|
|||
//------------------------------------------------------------------------------
|
||||
//----------- Registers Declarations -------------------------------------------
|
||||
//------------------------------------------------------------------------------
|
||||
reg [5:0] state; // current state
|
||||
reg [5:0] next_state; // next state
|
||||
reg [2:0] position_old; // saves the latest position
|
||||
reg [31:0] speed_count; // counts the current speed of rotation
|
||||
reg [31:0] speed_divider; // divides the speed of rotation by 2, correspoding to 30 degrees
|
||||
reg [31:0] delay_count; // Applied the delay to the input signal
|
||||
reg [5:0] state = RESET; // current state
|
||||
reg [5:0] next_state = RESET; // next state
|
||||
reg [2:0] position_old = 3'h0; // saves the latest position
|
||||
reg [31:0] speed_count = 32'h0; // counts the current speed of rotation
|
||||
reg [31:0] speed_divider = 32'h0; // divides the speed of rotation by 2, correspoding to 30 degrees
|
||||
reg [31:0] delay_count = 32'h0; // Applied the delay to the input signal
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
//----------- Assign/Always Blocks ---------------------------------------------
|
||||
|
|
|
|||
|
|
@ -77,9 +77,7 @@ module speed_detector
|
|||
//------------------------------------------------------------------------------
|
||||
//----------- Local Parameters -------------------------------------------------
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
localparam AW = LOG_2_AW - 1;
|
||||
|
||||
localparam MAX_SPEED_CNT = 32'h10000;
|
||||
|
||||
//State machine
|
||||
|
|
@ -94,14 +92,13 @@ localparam IDLE = 8'b10000000;
|
|||
//------------------------------------------------------------------------------
|
||||
//----------- Registers Declarations -------------------------------------------
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
reg [ 2:0] position_old;
|
||||
reg [63:0] avg_register;
|
||||
reg [63:0] avg_register_stable;
|
||||
reg [31:0] cnt_period;
|
||||
reg [31:0] decimation; // register used to divide by ten the speed
|
||||
reg [31:0] decimation; // register used to divide by ten the speed
|
||||
reg [31:0] cnt_period_old;
|
||||
reg [31:0] fifo [0:((2**LOG_2_AW)-1)]; // 32 bit wide RAM
|
||||
reg [31:0] fifo [0:((2**LOG_2_AW)-1)]; // 32 bit wide RAM
|
||||
reg [AW:0] write_addr;
|
||||
reg [AW:0] read_addr;
|
||||
|
||||
|
|
@ -113,7 +110,6 @@ reg [ 7:0] next_state;
|
|||
//------------------------------------------------------------------------------
|
||||
//----------- Assign/Always Blocks ---------------------------------------------
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
// Count ticks per position
|
||||
always @(posedge clk_i)
|
||||
begin
|
||||
|
|
|
|||
|
|
@ -0,0 +1,112 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2011(c) Analog Devices, Inc.
|
||||
//
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
// contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
module mdc_mdio (
|
||||
|
||||
mdio_mdc,
|
||||
mdio_in_w,
|
||||
mdio_in_r,
|
||||
|
||||
speed_select,
|
||||
duplex_mode);
|
||||
|
||||
parameter PHY_AD = 5'b10000;
|
||||
|
||||
input mdio_mdc;
|
||||
input mdio_in_w;
|
||||
input mdio_in_r;
|
||||
output [ 1:0] speed_select;
|
||||
output duplex_mode;
|
||||
|
||||
localparam IDLE = 2'b01;
|
||||
localparam ACQUIRE = 2'b10;
|
||||
|
||||
wire preamble;
|
||||
|
||||
reg [ 1:0] current_state = IDLE;
|
||||
reg [ 1:0] next_state = IDLE;
|
||||
reg [31:0] data_in = 32'h0;
|
||||
reg [31:0] data_in_r = 32'h0;
|
||||
reg [ 5:0] data_counter = 6'h0;
|
||||
reg [ 1:0] speed_select = 2'h0;
|
||||
reg duplex_mode = 1'h0;
|
||||
|
||||
assign preamble = &data_in;
|
||||
|
||||
always @(posedge mdio_mdc) begin
|
||||
current_state <= next_state;
|
||||
data_in <= {data_in[30:0], mdio_in_w};
|
||||
if (current_state == ACQUIRE) begin
|
||||
data_counter <= data_counter + 1;
|
||||
end else begin
|
||||
data_counter <= 0;
|
||||
end
|
||||
if (data_counter == 6'h1f) begin
|
||||
if (data_in[31] == 1'b0 && data_in[29:28]==2'b10 && data_in[27:23] == PHY_AD && data_in[22:18] == 5'h11) begin
|
||||
speed_select <= data_in_r[16:15] ;
|
||||
duplex_mode <= data_in_r[14];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(negedge mdio_mdc) begin
|
||||
data_in_r <= {data_in_r[30:0], mdio_in_r};
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
case (current_state)
|
||||
IDLE: begin
|
||||
if (preamble == 1 && mdio_in_w == 0) begin
|
||||
next_state <= ACQUIRE;
|
||||
end else begin
|
||||
next_state <= IDLE;
|
||||
end
|
||||
end
|
||||
ACQUIRE: begin
|
||||
if (data_counter == 6'h1f) begin
|
||||
next_state <= IDLE;
|
||||
end else begin
|
||||
next_state <= ACQUIRE;
|
||||
end
|
||||
end
|
||||
default: begin
|
||||
next_state <= IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,329 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2011(c) Analog Devices, Inc.
|
||||
//
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
// contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// based on XILINX xapp692
|
||||
// specific for MOTCON2 ADI board
|
||||
// works correctly if the PHY is set with Autonegotiation on
|
||||
|
||||
module util_gmii_to_rgmii (
|
||||
|
||||
clk_20m,
|
||||
clk_25m,
|
||||
clk_125m,
|
||||
|
||||
reset,
|
||||
|
||||
rgmii_td,
|
||||
rgmii_tx_ctl,
|
||||
rgmii_txc,
|
||||
rgmii_rd,
|
||||
rgmii_rx_ctl,
|
||||
rgmii_rxc,
|
||||
|
||||
mdio_mdc,
|
||||
mdio_in_w,
|
||||
mdio_in_r,
|
||||
|
||||
gmii_txd,
|
||||
gmii_tx_en,
|
||||
gmii_tx_er,
|
||||
gmii_tx_clk,
|
||||
gmii_crs,
|
||||
gmii_col,
|
||||
gmii_rxd,
|
||||
gmii_rx_dv,
|
||||
gmii_rx_er,
|
||||
gmii_rx_clk);
|
||||
|
||||
parameter PHY_AD = 5'b10000;
|
||||
|
||||
input clk_20m;
|
||||
input clk_25m;
|
||||
input clk_125m;
|
||||
|
||||
input reset;
|
||||
|
||||
output [ 3:0] rgmii_td;
|
||||
output rgmii_tx_ctl;
|
||||
output rgmii_txc;
|
||||
input [ 3:0] rgmii_rd;
|
||||
input rgmii_rx_ctl;
|
||||
input rgmii_rxc;
|
||||
|
||||
input mdio_mdc;
|
||||
input mdio_in_w;
|
||||
input mdio_in_r;
|
||||
|
||||
input [ 7:0] gmii_txd;
|
||||
input gmii_tx_en;
|
||||
input gmii_tx_er;
|
||||
output gmii_tx_clk;
|
||||
output gmii_crs;
|
||||
output gmii_col;
|
||||
output [ 7:0] gmii_rxd;
|
||||
output gmii_rx_dv;
|
||||
output gmii_rx_er;
|
||||
output gmii_rx_clk;
|
||||
|
||||
// wires
|
||||
wire clk_2_5m;
|
||||
wire clk_100msps;
|
||||
wire [ 3:0] rgmii_rd_delay;
|
||||
wire [ 7:0] gmii_rxd_s;
|
||||
wire [ 3:0] gmii_txd_low;
|
||||
wire rgmii_rx_ctl_delay;
|
||||
wire gmii_rx_er_s;
|
||||
wire rgmii_rxc_s;
|
||||
wire rgmii_rx_ctl_clk_s;
|
||||
wire rgmii_rx_ctl_s;
|
||||
wire rgmii_rxc_bufmr;
|
||||
|
||||
wire [ 1:0] speed_selection; // 1x gigabit, 01 100Mbps, 00 10mbps
|
||||
wire duplex_mode; // 1 full, 0 half
|
||||
|
||||
// registers
|
||||
reg tx_reset_d1;
|
||||
reg tx_reset_sync;
|
||||
reg rx_reset_d1;
|
||||
reg rx_reset_sync;
|
||||
reg [ 7:0] gmii_txd_r;
|
||||
reg gmii_tx_en_r;
|
||||
reg gmii_tx_er_r;
|
||||
|
||||
// assignments
|
||||
assign gigabit = speed_selection [1];
|
||||
|
||||
assign gmii_tx_clk = gmii_tx_clk_s;
|
||||
assign rgmii_tx_ctl_r = gmii_tx_en_r ^ gmii_tx_er_r;
|
||||
assign gmii_txd_low = gigabit ? gmii_txd_r[7:4] : gmii_txd_r[3:0];
|
||||
assign gmii_col = duplex_mode ? 1'b0 : (gmii_tx_en_r | gmii_tx_er_r) & ( gmii_rx_dv_s | gmii_rx_er_s) ;
|
||||
assign gmii_crs = duplex_mode ? 1'b0 : (gmii_tx_en_r | gmii_tx_er_r | gmii_rx_dv_s | gmii_rx_er_s);
|
||||
|
||||
assign gmii_rxd = gmii_rxd_s;
|
||||
assign gmii_rx_dv = gmii_rx_dv_s;
|
||||
assign gmii_rx_er = gmii_rx_er_s;
|
||||
assign gmii_rx_er_s = gmii_rx_dv_s ^ rgmii_rx_ctl_s;
|
||||
|
||||
always @(posedge gmii_tx_clk_s) begin
|
||||
tx_reset_d1 <= reset;
|
||||
tx_reset_sync <= tx_reset_d1;
|
||||
end
|
||||
|
||||
always @(posedge gmii_tx_clk_s) begin
|
||||
if (tx_reset_sync == 1'b1) begin
|
||||
gmii_txd_r <= 8'h0;
|
||||
gmii_tx_en_r <= 1'b0;
|
||||
gmii_tx_er_r <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
gmii_txd_r <= gmii_txd;
|
||||
gmii_tx_en_r <= gmii_tx_en;
|
||||
gmii_tx_er_r <= gmii_tx_er;
|
||||
end
|
||||
end
|
||||
|
||||
BUFR #(
|
||||
.BUFR_DIVIDE("8"),
|
||||
.SIM_DEVICE("7SERIES")
|
||||
) clk_2_5_divide (
|
||||
.I(clk_20m),
|
||||
.CE(1),
|
||||
.CLR(0),
|
||||
.O(clk_2_5m));
|
||||
|
||||
BUFGMUX #(
|
||||
.CLK_SEL_TYPE ("SYNC")
|
||||
) clk_tx_mux0 (
|
||||
.S(speed_selection[0]),
|
||||
.I0(clk_2_5m),
|
||||
.I1(clk_25m),
|
||||
.O(clk_100msps));
|
||||
|
||||
BUFGMUX #(
|
||||
.CLK_SEL_TYPE ("SYNC")
|
||||
) clk_tx_mux1 (
|
||||
.S(speed_selection[1]),
|
||||
.I0(clk_100msps),
|
||||
.I1(clk_125m),
|
||||
.O(gmii_tx_clk_s));
|
||||
|
||||
ODDR #(
|
||||
.DDR_CLK_EDGE("SAME_EDGE")
|
||||
) rgmii_txc_out (
|
||||
.Q (rgmii_txc),
|
||||
.C (gmii_tx_clk_s),
|
||||
.CE(1),
|
||||
.D1(1),
|
||||
.D2(0),
|
||||
.R(tx_reset_sync),
|
||||
.S(0));
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
for (i = 0; i < 4; i = i + 1) begin : gen_tx_data
|
||||
ODDR #(
|
||||
.DDR_CLK_EDGE("SAME_EDGE")
|
||||
) rgmii_td_out (
|
||||
.Q (rgmii_td[i]),
|
||||
.C (gmii_tx_clk_s),
|
||||
.CE(1),
|
||||
.D1(gmii_txd_r[i]),
|
||||
.D2(gmii_txd_low[i]),
|
||||
.R(tx_reset_sync),
|
||||
.S(0));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
ODDR #(
|
||||
.DDR_CLK_EDGE("SAME_EDGE")
|
||||
) rgmii_tx_ctl_out (
|
||||
.Q (rgmii_tx_ctl),
|
||||
.C (gmii_tx_clk_s),
|
||||
.CE(1),
|
||||
.D1(gmii_tx_en_r),
|
||||
.D2(rgmii_tx_ctl_r),
|
||||
.R(tx_reset_sync),
|
||||
.S(0));
|
||||
|
||||
|
||||
always @(posedge rgmii_rxc_s) begin
|
||||
rx_reset_d1 <= reset;
|
||||
rx_reset_sync <= rx_reset_d1;
|
||||
end
|
||||
|
||||
BUFMR bufmr_rgmii_rxc(
|
||||
.I(rgmii_rxc),
|
||||
.O(rgmii_rxc_bufmr));
|
||||
|
||||
BUFR #(
|
||||
.SIM_DEVICE("7SERIES"),
|
||||
.BUFR_DIVIDE(1)
|
||||
) bufr_rgmii_rx_clk (
|
||||
.I(rgmii_rxc_bufmr),
|
||||
.CE(1),
|
||||
.CLR(0),
|
||||
.O(rgmii_rxc_s));
|
||||
|
||||
BUFR #(
|
||||
.SIM_DEVICE("7SERIES"),
|
||||
.BUFR_DIVIDE(1)
|
||||
) bufr_rgmii_rx_ctl_clk (
|
||||
.I(rgmii_rxc_bufmr),
|
||||
.CE(1),
|
||||
.CLR(0),
|
||||
.O(rgmii_rx_ctl_clk_s));
|
||||
|
||||
BUFG bufg_rgmii_rx_clk (
|
||||
.I(rgmii_rxc_s),
|
||||
.O(gmii_rx_clk));
|
||||
|
||||
IDELAYE2 #(
|
||||
.IDELAY_TYPE("FIXED"),
|
||||
.HIGH_PERFORMANCE_MODE("TRUE"),
|
||||
.REFCLK_FREQUENCY(200.0),
|
||||
.SIGNAL_PATTERN("DATA"),
|
||||
.DELAY_SRC("IDATAIN")
|
||||
) delay_rgmii_rx_ctl (
|
||||
.IDATAIN(rgmii_rx_ctl),
|
||||
.DATAOUT(rgmii_rx_ctl_delay),
|
||||
.DATAIN(0),
|
||||
.C(0),
|
||||
.CE(0),
|
||||
.INC(0),
|
||||
.CINVCTRL(0),
|
||||
.CNTVALUEOUT(),
|
||||
.LD(0),
|
||||
.LDPIPEEN(0),
|
||||
.CNTVALUEIN(0),
|
||||
.REGRST(0));
|
||||
|
||||
generate
|
||||
for (i = 0; i < 4; i = i + 1) begin
|
||||
IDELAYE2 #(
|
||||
.IDELAY_TYPE("FIXED"),
|
||||
.HIGH_PERFORMANCE_MODE("TRUE"),
|
||||
.REFCLK_FREQUENCY(200.0),
|
||||
.SIGNAL_PATTERN("DATA"),
|
||||
.DELAY_SRC("IDATAIN")
|
||||
) delay_rgmii_rd (
|
||||
.IDATAIN(rgmii_rd[i]),
|
||||
.DATAOUT(rgmii_rd_delay[i]),
|
||||
.DATAIN(0),
|
||||
.C(0),
|
||||
.CE(0),
|
||||
.INC(0),
|
||||
.CINVCTRL(0),
|
||||
.CNTVALUEOUT(),
|
||||
.LD(0),
|
||||
.LDPIPEEN(0),
|
||||
.CNTVALUEIN(0),
|
||||
.REGRST(0));
|
||||
|
||||
IDDR #(
|
||||
.DDR_CLK_EDGE("SAME_EDGE_PIPELINED")
|
||||
) rgmii_rx_iddr (
|
||||
.Q1(gmii_rxd_s[i]),
|
||||
.Q2(gmii_rxd_s[i+4]),
|
||||
.C(rgmii_rxc_s),
|
||||
.CE(1),
|
||||
.D(rgmii_rd_delay[i]),
|
||||
.R(0),
|
||||
.S(0));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
IDDR #(
|
||||
.DDR_CLK_EDGE("SAME_EDGE_PIPELINED")
|
||||
) rgmii_rx_ctl_iddr (
|
||||
.Q1(gmii_rx_dv_s),
|
||||
.Q2(rgmii_rx_ctl_s),
|
||||
.C(rgmii_rx_ctl_clk_s),
|
||||
.CE(1),
|
||||
.D(rgmii_rx_ctl_delay),
|
||||
.R(0),
|
||||
.S(0));
|
||||
|
||||
mdc_mdio #(
|
||||
.PHY_AD(PHY_AD)
|
||||
) mdc_mdio_in(
|
||||
.mdio_mdc(mdio_mdc),
|
||||
.mdio_in_w(mdio_in_w),
|
||||
.mdio_in_r(mdio_in_r),
|
||||
.speed_select(speed_selection),
|
||||
.duplex_mode(duplex_mode));
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
# ip
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip.tcl
|
||||
|
||||
adi_ip_create util_gmii_to_rgmii
|
||||
adi_ip_files util_gmii_to_rgmii [list \
|
||||
"mdc_mdio.v" \
|
||||
"util_gmii_to_rgmii.v" ]
|
||||
|
||||
adi_ip_properties_lite util_gmii_to_rgmii
|
||||
|
||||
ipx::infer_bus_interface {gmii_tx_clk gmii_txd gmii_tx_en gmii_tx_er gmii_crs gmii_col gmii_rx_clk gmii_rxd gmii_rx_dv gmii_rx_er} xilinx.com:interface:gmii_rtl:1.0 [ipx::current_core]
|
||||
set_property name {gmii} [ipx::get_bus_interface gmii_rtl_1 [ipx::current_core]]
|
||||
ipx::infer_bus_interface {rgmii_td rgmii_tx_ctl rgmii_txc rgmii_rd rgmii_rx_ctl rgmii_rxc} xilinx.com:interface:rgmii_rtl:1.0 [ipx::current_core]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
|
@ -2,4 +2,12 @@
|
|||
source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
|
||||
source ../common/fmcomms1_bd.tcl
|
||||
|
||||
|
||||
# Add extra register slice between ADC DMA and HP1 to meet timing
|
||||
delete_bd_objs [get_bd_intf_nets axi_ad9643_dma_axi]
|
||||
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0
|
||||
set_property -dict [list CONFIG.REG_AW {0} CONFIG.REG_AR {0} CONFIG.REG_W {1} CONFIG.REG_R {0} CONFIG.REG_B {0}] [get_bd_cells axi_register_slice_0]
|
||||
connect_bd_intf_net [get_bd_intf_pins axi_register_slice_0/S_AXI] [get_bd_intf_pins axi_ad9643_dma/m_dest_axi]
|
||||
connect_bd_intf_net [get_bd_intf_pins sys_ps7/S_AXI_HP1] [get_bd_intf_pins axi_register_slice_0/M_AXI]
|
||||
connect_bd_net -net [get_bd_nets sys_200m_clk] [get_bd_pins axi_register_slice_0/aclk] [get_bd_pins sys_ps7/FCLK_CLK1]
|
||||
connect_bd_net -net [get_bd_nets sys_100m_resetn] [get_bd_pins axi_register_slice_0/aresetn] [get_bd_pins sys_rstgen/peripheral_aresetn]
|
||||
assign_bd_address [get_bd_addr_segs {sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM }]
|
||||
|
|
|
|||
|
|
@ -1,450 +0,0 @@
|
|||
|
||||
# motor control
|
||||
|
||||
# position detection interface
|
||||
|
||||
set position_i [ create_bd_port -dir I -from 2 -to 0 position_i ]
|
||||
|
||||
# current monitor 1 interface
|
||||
|
||||
set adc_ia_dat_i [ create_bd_port -dir I adc_ia_dat_i ]
|
||||
set adc_ib_dat_i [ create_bd_port -dir I adc_ib_dat_i ]
|
||||
set adc_it_dat_i [ create_bd_port -dir I adc_it_dat_i ]
|
||||
set adc_vbus_dat_i [ create_bd_port -dir I adc_vbus_dat_i ]
|
||||
set adc_ia_clk_o [ create_bd_port -dir O adc_ia_clk_o ]
|
||||
set adc_ib_clk_o [ create_bd_port -dir O adc_ib_clk_o ]
|
||||
set adc_it_clk_o [ create_bd_port -dir O adc_it_clk_o ]
|
||||
set adc_vbus_clk_o [ create_bd_port -dir O adc_vbus_clk_o ]
|
||||
|
||||
# cuurrent monitor 2 interface
|
||||
|
||||
set adc_ia_dat_d_i [ create_bd_port -dir I adc_ia_dat_d_i ]
|
||||
set adc_ib_dat_d_i [ create_bd_port -dir I adc_ib_dat_d_i ]
|
||||
set adc_it_dat_d_i [ create_bd_port -dir I adc_it_dat_d_i ]
|
||||
set adc_ia_clk_d_o [ create_bd_port -dir O adc_ia_clk_d_o ]
|
||||
set adc_ib_clk_d_o [ create_bd_port -dir O adc_ib_clk_d_o ]
|
||||
set adc_it_clk_d_o [ create_bd_port -dir O adc_it_clk_d_o ]
|
||||
|
||||
# motor control interface
|
||||
|
||||
set fmc_m1_fault_i [ create_bd_port -dir I fmc_m1_fault_i ]
|
||||
set fmc_m1_en_o [ create_bd_port -dir O fmc_m1_en_o ]
|
||||
|
||||
set pwm_al_o [ create_bd_port -dir O pwm_al_o]
|
||||
set pwm_ah_o [ create_bd_port -dir O pwm_ah_o]
|
||||
set pwm_cl_o [ create_bd_port -dir O pwm_cl_o]
|
||||
set pwm_ch_o [ create_bd_port -dir O pwm_ch_o]
|
||||
set pwm_bl_o [ create_bd_port -dir O pwm_bl_o]
|
||||
set pwm_bh_o [ create_bd_port -dir O pwm_bh_o]
|
||||
|
||||
# gpo interface
|
||||
|
||||
set gpo_o [ create_bd_port -dir O -from 7 -to 0 gpo_o ]
|
||||
|
||||
# interrupts
|
||||
|
||||
set motcon1_c_m_1_irq [create_bd_port -dir O motcon1_c_m_1_irq]
|
||||
set motcon1_c_m_2_irq [create_bd_port -dir O motcon1_c_m_2_irq]
|
||||
set motcon1_s_d_irq [create_bd_port -dir O motcon1_s_d_irq]
|
||||
set motcon1_ctrl_irq [create_bd_port -dir O motcon1_ctrl_irq]
|
||||
|
||||
# xadc interface
|
||||
|
||||
#create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0
|
||||
#create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8
|
||||
#create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn
|
||||
|
||||
#set muxaddr_out [ create_bd_port -dir O -from 4 -to 0 muxaddr_out ]
|
||||
|
||||
# additions to default configuration
|
||||
|
||||
set_property -dict [list CONFIG.NUM_MI {17}] $axi_cpu_interconnect
|
||||
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1} ] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1} ] $sys_ps7
|
||||
|
||||
# current monitor 1 peripherals
|
||||
|
||||
set axi_mc_current_monitor_1 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_current_monitor:1.0 axi_mc_current_monitor_1 ]
|
||||
|
||||
set axi_current_monitor_1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_current_monitor_1_dma]
|
||||
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_current_monitor_1_dma
|
||||
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_current_monitor_1_dma
|
||||
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_current_monitor_1_dma
|
||||
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_current_monitor_1_dma
|
||||
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_current_monitor_1_dma
|
||||
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_current_monitor_1_dma
|
||||
|
||||
# current monitor 2 peripherals
|
||||
|
||||
set axi_mc_current_monitor_2 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_current_monitor:1.0 axi_mc_current_monitor_2 ]
|
||||
|
||||
set axi_current_monitor_2_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_current_monitor_2_dma]
|
||||
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_current_monitor_2_dma
|
||||
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_current_monitor_2_dma
|
||||
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_current_monitor_2_dma
|
||||
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_current_monitor_2_dma
|
||||
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_current_monitor_2_dma
|
||||
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_current_monitor_2_dma
|
||||
|
||||
# speed detector
|
||||
|
||||
set axi_mc_speed_1 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_speed:1.0 axi_mc_speed_1 ]
|
||||
|
||||
set axi_speed_detector_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_speed_detector_dma]
|
||||
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_speed_detector_dma
|
||||
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_speed_detector_dma
|
||||
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_speed_detector_dma
|
||||
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_speed_detector_dma
|
||||
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_speed_detector_dma
|
||||
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {32}] $axi_speed_detector_dma
|
||||
|
||||
# controller
|
||||
|
||||
set axi_mc_controller [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_controller:1.0 axi_mc_controller ]
|
||||
|
||||
set foc_controller [ create_bd_cell -type ip -vlnv analog.com:user:controllerperipheralhdladi_pcore:1.0 foc_controller ]
|
||||
|
||||
set axi_controller_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_controller_dma]
|
||||
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_controller_dma
|
||||
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_controller_dma
|
||||
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_controller_dma
|
||||
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_controller_dma
|
||||
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_controller_dma
|
||||
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {256}] $axi_controller_dma
|
||||
|
||||
# controller ILA
|
||||
set ila_controller [ create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_controller ]
|
||||
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_controller
|
||||
set_property -dict [ list CONFIG.C_ADV_TRIGGER {true} ] $ila_controller
|
||||
set_property -dict [ list CONFIG.C_DATA_DEPTH {8192} ] $ila_controller
|
||||
set_property -dict [ list CONFIG.C_EN_STRG_QUAL {1} ] $ila_controller
|
||||
set_property -dict [ list CONFIG.C_NUM_OF_PROBES {10} ] $ila_controller
|
||||
set_property -dict [ list CONFIG.C_PROBE0_WIDTH {32} ] $ila_controller
|
||||
set_property -dict [ list CONFIG.C_PROBE1_WIDTH {32} ] $ila_controller
|
||||
set_property -dict [ list CONFIG.C_PROBE2_WIDTH {32} ] $ila_controller
|
||||
set_property -dict [ list CONFIG.C_PROBE3_WIDTH {32} ] $ila_controller
|
||||
set_property -dict [ list CONFIG.C_PROBE4_WIDTH {32} ] $ila_controller
|
||||
set_property -dict [ list CONFIG.C_PROBE5_WIDTH {32} ] $ila_controller
|
||||
set_property -dict [ list CONFIG.C_PROBE6_WIDTH {32} ] $ila_controller
|
||||
set_property -dict [ list CONFIG.C_PROBE7_WIDTH {32} ] $ila_controller
|
||||
set_property -dict [ list CONFIG.C_PROBE8_WIDTH {32} ] $ila_controller
|
||||
set_property -dict [ list CONFIG.C_PROBE9_WIDTH {1} ] $ila_controller
|
||||
set_property -dict [ list CONFIG.C_TRIGIN_EN {false} ] $ila_controller
|
||||
|
||||
#adc_pack
|
||||
set util_adc_pack_0 [ create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 util_adc_pack_0 ]
|
||||
set_property -dict [ list CONFIG.DATA_WIDTH {32} ] $util_adc_pack_0
|
||||
|
||||
# slice0
|
||||
set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ]
|
||||
set_property -dict [ list CONFIG.DIN_FROM {1} CONFIG.DIN_TO {1} CONFIG.DIN_WIDTH {3} ] $xlslice_0
|
||||
|
||||
# slice1
|
||||
set xlslice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 ]
|
||||
set_property -dict [ list CONFIG.DIN_FROM {2} CONFIG.DIN_TO {2} CONFIG.DIN_WIDTH {3} ] $xlslice_1
|
||||
|
||||
# slice2
|
||||
set xlslice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2 ]
|
||||
set_property -dict [ list CONFIG.DIN_FROM {0} CONFIG.DIN_TO {0} CONFIG.DIN_WIDTH {3} ] $xlslice_2
|
||||
|
||||
# xadc
|
||||
|
||||
# set xadc_wiz_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.0 xadc_wiz_1 ]
|
||||
# set_property -dict [ list CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} ] $xadc_wiz_1
|
||||
# set_property -dict [ list CONFIG.OT_ALARM {false} ] $xadc_wiz_1
|
||||
# set_property -dict [ list CONFIG.USER_TEMP_ALARM {false} ] $xadc_wiz_1
|
||||
# set_property -dict [ list CONFIG.VCCINT_ALARM {false} ] $xadc_wiz_1
|
||||
# set_property -dict [ list CONFIG.VCCAUX_ALARM {false} ] $xadc_wiz_1
|
||||
# set_property -dict [ list CONFIG.ENABLE_EXTERNAL_MUX {true} ] $xadc_wiz_1
|
||||
# set_property -dict [list CONFIG.EXTERNAL_MUX_CHANNEL {VAUXP0_VAUXN0}] $xadc_wiz_1
|
||||
|
||||
# additional interconnect
|
||||
|
||||
set axi_mem_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_interconnect ]
|
||||
set_property -dict [ list CONFIG.NUM_SI {4} CONFIG.NUM_MI {1} ] $axi_mem_interconnect
|
||||
|
||||
# connections
|
||||
|
||||
# position
|
||||
|
||||
connect_bd_net -net position_i_1 [get_bd_ports position_i] [get_bd_pins axi_mc_speed_1/position_i]
|
||||
connect_bd_net -net position_i_1 [get_bd_pins axi_mc_speed_1/bemf_i]
|
||||
|
||||
# current monitor 1
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_current_monitor_1/ref_clk] $sys_100m_clk_source
|
||||
|
||||
connect_bd_net -net adc_ia_dat_i_1 [get_bd_ports adc_ia_dat_i] [get_bd_pins axi_mc_current_monitor_1/adc_ia_dat_i]
|
||||
connect_bd_net -net adc_ib_dat_i_1 [get_bd_ports adc_ib_dat_i] [get_bd_pins axi_mc_current_monitor_1/adc_ib_dat_i]
|
||||
connect_bd_net -net adc_it_dat_i_1 [get_bd_ports adc_it_dat_i] [get_bd_pins axi_mc_current_monitor_1/adc_it_dat_i]
|
||||
connect_bd_net -net adc_vbus_dat_i_1 [get_bd_ports adc_vbus_dat_i] [get_bd_pins axi_mc_current_monitor_1/adc_vbus_dat_i]
|
||||
|
||||
connect_bd_net -net axi_mc_current_monitor_1_adc_ia_clk_o [get_bd_ports adc_ia_clk_o] [get_bd_pins axi_mc_current_monitor_1/adc_ia_clk_o]
|
||||
connect_bd_net -net axi_mc_current_monitor_1_adc_ib_clk_o [get_bd_ports adc_ib_clk_o] [get_bd_pins axi_mc_current_monitor_1/adc_ib_clk_o]
|
||||
connect_bd_net -net axi_mc_current_monitor_1_adc_it_clk_o [get_bd_ports adc_it_clk_o] [get_bd_pins axi_mc_current_monitor_1/adc_it_clk_o]
|
||||
connect_bd_net -net axi_mc_current_monitor_1_adc_vbus_clk_o [get_bd_ports adc_vbus_clk_o] [get_bd_pins axi_mc_current_monitor_1/adc_vbus_clk_o]
|
||||
|
||||
connect_bd_net -net axi_mc_current_monitor_1_adc_clk [get_bd_pins axi_mc_current_monitor_1/adc_clk_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_clk]
|
||||
connect_bd_net -net axi_mc_current_monitor_1_adc_dwr [get_bd_pins axi_mc_current_monitor_1/adc_dwr_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_en]
|
||||
connect_bd_net -net axi_mc_current_monitor_1_adc_ddata [get_bd_pins axi_mc_current_monitor_1/adc_ddata_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_din]
|
||||
connect_bd_net -net axi_mc_current_monitor_1_adc_dsync [get_bd_pins axi_mc_current_monitor_1/adc_dsync_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_sync]
|
||||
connect_bd_net -net axi_mc_current_monitor_1_adc_dovf [get_bd_pins axi_mc_current_monitor_1/adc_dovf_i] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_overflow]
|
||||
|
||||
connect_bd_net -net axi_mc_current_monitor_1_ia_o [get_bd_pins axi_mc_current_monitor_1/ia_o] [get_bd_pins foc_controller/adc_current1]
|
||||
connect_bd_net -net axi_mc_current_monitor_1_ib_o [get_bd_pins axi_mc_current_monitor_1/ib_o] [get_bd_pins foc_controller/adc_current2]
|
||||
connect_bd_net -net axi_mc_current_monitor_1_i_ready_o [get_bd_pins axi_mc_controller/ctrl_data_valid_i] [get_bd_pins axi_mc_current_monitor_1/i_ready_o]
|
||||
|
||||
# interrupt
|
||||
|
||||
connect_bd_net -net axi_current_monitor_1_dma_irq [get_bd_pins axi_current_monitor_1_dma/irq] [get_bd_ports motcon1_c_m_1_irq]
|
||||
|
||||
# current monitor 2
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_current_monitor_2/ref_clk] $sys_100m_clk_source
|
||||
|
||||
connect_bd_net -net adc_ia_dat_d_i [get_bd_ports adc_ia_dat_d_i] [get_bd_pins axi_mc_current_monitor_2/adc_ia_dat_i]
|
||||
connect_bd_net -net axi_mc_current_monitor_2_adc_ia_clk_o [get_bd_ports adc_ia_clk_d_o] [get_bd_pins axi_mc_current_monitor_2/adc_ia_clk_o]
|
||||
connect_bd_net -net adc_ib_dat_d_i [get_bd_ports adc_ib_dat_d_i] [get_bd_pins axi_mc_current_monitor_2/adc_ib_dat_i]
|
||||
connect_bd_net -net axi_mc_current_monitor_2_adc_ib_clk_o [get_bd_ports adc_ib_clk_d_o] [get_bd_pins axi_mc_current_monitor_2/adc_ib_clk_o]
|
||||
connect_bd_net -net adc_it_dat_d_i [get_bd_ports adc_it_dat_d_i] [get_bd_pins axi_mc_current_monitor_2/adc_it_dat_i]
|
||||
connect_bd_net -net axi_mc_current_monitor_2_adc_it_clk_o [get_bd_ports adc_it_clk_d_o] [get_bd_pins axi_mc_current_monitor_2/adc_it_clk_o]
|
||||
|
||||
connect_bd_net -net axi_mc_current_monitor_2_adc_clk [get_bd_pins axi_mc_current_monitor_2/adc_clk_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_clk]
|
||||
connect_bd_net -net axi_mc_current_monitor_2_adc_dwr [get_bd_pins axi_mc_current_monitor_2/adc_dwr_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_en]
|
||||
connect_bd_net -net axi_mc_current_monitor_2_adc_ddata [get_bd_pins axi_mc_current_monitor_2/adc_ddata_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_din]
|
||||
connect_bd_net -net axi_mc_current_monitor_2_adc_dsync [get_bd_pins axi_mc_current_monitor_2/adc_dsync_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_sync]
|
||||
connect_bd_net -net axi_mc_current_monitor_2_adc_dovf [get_bd_pins axi_mc_current_monitor_2/adc_dovf_i] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_overflow]
|
||||
|
||||
#interrupt
|
||||
|
||||
connect_bd_net -net axi_current_monitor_2_dma_irq [get_bd_pins axi_current_monitor_2_dma/irq] [get_bd_ports motcon1_c_m_2_irq]
|
||||
|
||||
# speed detector
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_speed_1/ref_clk] $sys_100m_clk_source
|
||||
|
||||
connect_bd_net -net axi_mc_speed_1_position_o [get_bd_pins axi_mc_speed_1/position_o] [get_bd_pins axi_mc_controller/position_i]
|
||||
|
||||
connect_bd_net -net speed_detector_adc_clk [get_bd_pins axi_mc_speed_1/adc_clk_o] [get_bd_pins axi_speed_detector_dma/fifo_wr_clk]
|
||||
connect_bd_net -net speed_detector_adc_dwr [get_bd_pins axi_mc_speed_1/adc_dwr_o] [get_bd_pins axi_speed_detector_dma/fifo_wr_en]
|
||||
connect_bd_net -net speed_detector_adc_ddata [get_bd_pins axi_mc_speed_1/adc_ddata_o] [get_bd_pins axi_speed_detector_dma/fifo_wr_din]
|
||||
connect_bd_net -net speed_detector_adc_dovf [get_bd_pins axi_mc_speed_1/adc_dovf_i] [get_bd_pins axi_speed_detector_dma/fifo_wr_overflow]
|
||||
|
||||
# interrupt
|
||||
|
||||
connect_bd_net -net axi_speed_detector_dma_irq [get_bd_pins axi_speed_detector_dma/irq] [get_bd_ports motcon1_s_d_irq]
|
||||
|
||||
# controller
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_controller/ref_clk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_controller/ctrl_data_clk] $sys_100m_clk_source
|
||||
|
||||
connect_bd_net -net axi_mc_controller_fmc_m1_en_o [get_bd_ports fmc_m1_en_o] [get_bd_pins axi_mc_controller/fmc_m1_en_o]
|
||||
connect_bd_net -net axi_mc_controller_pwm_al_o [get_bd_ports pwm_al_o] [get_bd_pins axi_mc_controller/pwm_al_o]
|
||||
connect_bd_net -net axi_mc_controller_pwm_ah_o [get_bd_ports pwm_ah_o] [get_bd_pins axi_mc_controller/pwm_ah_o]
|
||||
connect_bd_net -net axi_mc_controller_pwm_cl_o [get_bd_ports pwm_cl_o] [get_bd_pins axi_mc_controller/pwm_cl_o]
|
||||
connect_bd_net -net axi_mc_controller_pwm_ch_o [get_bd_ports pwm_ch_o] [get_bd_pins axi_mc_controller/pwm_ch_o]
|
||||
connect_bd_net -net axi_mc_controller_pwm_bl_o [get_bd_ports pwm_bl_o] [get_bd_pins axi_mc_controller/pwm_bl_o]
|
||||
connect_bd_net -net axi_mc_controller_pwm_bh_o [get_bd_ports pwm_bh_o] [get_bd_pins axi_mc_controller/pwm_bh_o]
|
||||
connect_bd_net -net axi_mc_controller_gpo_o [get_bd_ports gpo_o] [get_bd_pins axi_mc_controller/gpo_o]
|
||||
connect_bd_net -net axi_mc_controller_sensors_o [get_bd_pins axi_mc_controller/sensors_o] [get_bd_pins axi_mc_speed_1/hall_bemf_i]
|
||||
connect_bd_net -net axi_mc_controller_fault [get_bd_pins /axi_mc_controller/fmc_m1_fault_i] [get_bd_ports /fmc_m1_fault_i]
|
||||
|
||||
connect_bd_net -net axi_mc_controller_adc_clk_o [get_bd_pins axi_mc_controller/adc_clk_o] [get_bd_pins util_adc_pack_0/clk]
|
||||
connect_bd_net -net axi_mc_controller_adc_data_c0 [get_bd_pins axi_mc_controller/adc_data_c0] [get_bd_pins util_adc_pack_0/chan_data_0]
|
||||
connect_bd_net -net axi_mc_controller_adc_data_c1 [get_bd_pins axi_mc_controller/adc_data_c1] [get_bd_pins util_adc_pack_0/chan_data_1]
|
||||
connect_bd_net -net axi_mc_controller_adc_data_c2 [get_bd_pins axi_mc_controller/adc_data_c2] [get_bd_pins util_adc_pack_0/chan_data_2]
|
||||
connect_bd_net -net axi_mc_controller_adc_data_c3 [get_bd_pins axi_mc_controller/adc_data_c3] [get_bd_pins util_adc_pack_0/chan_data_3]
|
||||
connect_bd_net -net axi_mc_controller_adc_data_c4 [get_bd_pins axi_mc_controller/adc_data_c4] [get_bd_pins util_adc_pack_0/chan_data_4]
|
||||
connect_bd_net -net axi_mc_controller_adc_data_c5 [get_bd_pins axi_mc_controller/adc_data_c5] [get_bd_pins util_adc_pack_0/chan_data_5]
|
||||
connect_bd_net -net axi_mc_controller_adc_data_c6 [get_bd_pins axi_mc_controller/adc_data_c6] [get_bd_pins util_adc_pack_0/chan_data_6]
|
||||
connect_bd_net -net axi_mc_controller_adc_data_c7 [get_bd_pins axi_mc_controller/adc_data_c7] [get_bd_pins util_adc_pack_0/chan_data_7]
|
||||
connect_bd_net -net axi_mc_controller_adc_enable_c0 [get_bd_pins axi_mc_controller/adc_enable_c0] [get_bd_pins util_adc_pack_0/chan_enable_0]
|
||||
connect_bd_net -net axi_mc_controller_adc_enable_c1 [get_bd_pins axi_mc_controller/adc_enable_c1] [get_bd_pins util_adc_pack_0/chan_enable_1]
|
||||
connect_bd_net -net axi_mc_controller_adc_enable_c2 [get_bd_pins axi_mc_controller/adc_enable_c2] [get_bd_pins util_adc_pack_0/chan_enable_2]
|
||||
connect_bd_net -net axi_mc_controller_adc_enable_c3 [get_bd_pins axi_mc_controller/adc_enable_c3] [get_bd_pins util_adc_pack_0/chan_enable_3]
|
||||
connect_bd_net -net axi_mc_controller_adc_enable_c4 [get_bd_pins axi_mc_controller/adc_enable_c4] [get_bd_pins util_adc_pack_0/chan_enable_4]
|
||||
connect_bd_net -net axi_mc_controller_adc_enable_c5 [get_bd_pins axi_mc_controller/adc_enable_c5] [get_bd_pins util_adc_pack_0/chan_enable_5]
|
||||
connect_bd_net -net axi_mc_controller_adc_enable_c6 [get_bd_pins axi_mc_controller/adc_enable_c6] [get_bd_pins util_adc_pack_0/chan_enable_6]
|
||||
connect_bd_net -net axi_mc_controller_adc_enable_c7 [get_bd_pins axi_mc_controller/adc_enable_c7] [get_bd_pins util_adc_pack_0/chan_enable_7]
|
||||
connect_bd_net -net axi_mc_controller_adc_valid_c0 [get_bd_pins axi_mc_controller/adc_valid_c0] [get_bd_pins util_adc_pack_0/chan_valid_0]
|
||||
connect_bd_net -net axi_mc_controller_adc_valid_c1 [get_bd_pins axi_mc_controller/adc_valid_c1] [get_bd_pins util_adc_pack_0/chan_valid_1]
|
||||
connect_bd_net -net axi_mc_controller_adc_valid_c2 [get_bd_pins axi_mc_controller/adc_valid_c2] [get_bd_pins util_adc_pack_0/chan_valid_2]
|
||||
connect_bd_net -net axi_mc_controller_adc_valid_c3 [get_bd_pins axi_mc_controller/adc_valid_c3] [get_bd_pins util_adc_pack_0/chan_valid_3]
|
||||
connect_bd_net -net axi_mc_controller_adc_valid_c4 [get_bd_pins axi_mc_controller/adc_valid_c4] [get_bd_pins util_adc_pack_0/chan_valid_4]
|
||||
connect_bd_net -net axi_mc_controller_adc_valid_c5 [get_bd_pins axi_mc_controller/adc_valid_c5] [get_bd_pins util_adc_pack_0/chan_valid_5]
|
||||
connect_bd_net -net axi_mc_controller_adc_valid_c6 [get_bd_pins axi_mc_controller/adc_valid_c6] [get_bd_pins util_adc_pack_0/chan_valid_6]
|
||||
connect_bd_net -net axi_mc_controller_adc_valid_c7 [get_bd_pins axi_mc_controller/adc_valid_c7] [get_bd_pins util_adc_pack_0/chan_valid_7]
|
||||
|
||||
connect_bd_net -net axi_mc_controller_adc_clk_o [get_bd_pins axi_controller_dma/fifo_wr_clk]
|
||||
connect_bd_net -net axi_mc_controller_adc_ddata [get_bd_pins axi_controller_dma/fifo_wr_din] [get_bd_pins util_adc_pack_0/ddata]
|
||||
connect_bd_net -net axi_mc_controller_adc_dovf [get_bd_pins axi_controller_dma/fifo_wr_overflow] [get_bd_pins axi_mc_controller/adc_dovf_i]
|
||||
connect_bd_net -net axi_mc_controller_adc_dwr [get_bd_pins axi_controller_dma/fifo_wr_en] [get_bd_pins util_adc_pack_0/dvalid]
|
||||
connect_bd_net -net util_adc_pack_0_dsync [get_bd_pins axi_controller_dma/fifo_wr_sync] [get_bd_pins util_adc_pack_0/dsync]
|
||||
|
||||
#foc_controller
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins foc_controller/s_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_ps7_FCLK_CLK2 [get_bd_pins foc_controller/IPCORE_CLK] [get_bd_pins sys_ps7/FCLK_CLK2]
|
||||
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins foc_controller/s_axi_aresetn] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins foc_controller/IPCORE_RESETN] $sys_100m_resetn_source
|
||||
|
||||
connect_bd_net -net foc_controller_mon_d_current [get_bd_pins axi_mc_controller/ctrl_data6_i]
|
||||
connect_bd_net -net foc_controller_mon_d_current [get_bd_pins foc_controller/mon_d_current]
|
||||
|
||||
connect_bd_net -net foc_controller_pwm_a [get_bd_pins axi_mc_controller/pwm_a_i] [get_bd_pins foc_controller/pwm_a]
|
||||
connect_bd_net -net foc_controller_pwm_b [get_bd_pins axi_mc_controller/pwm_b_i] [get_bd_pins foc_controller/pwm_b]
|
||||
connect_bd_net -net foc_controller_pwm_c [get_bd_pins axi_mc_controller/pwm_c_i] [get_bd_pins foc_controller/pwm_c]
|
||||
connect_bd_net -net xlslice_0_Dout [get_bd_pins foc_controller/encoder_a] [get_bd_pins xlslice_0/Dout]
|
||||
connect_bd_net -net xlslice_1_Dout [get_bd_pins foc_controller/encoder_b] [get_bd_pins xlslice_1/Dout]
|
||||
connect_bd_net -net xlslice_2_Dout [get_bd_pins foc_controller/encoder_index] [get_bd_pins xlslice_2/Dout]
|
||||
connect_bd_net -net position_i_1 [get_bd_pins xlslice_1/Din]
|
||||
connect_bd_net -net position_i_1 [get_bd_pins xlslice_0/Din]
|
||||
connect_bd_net -net position_i_1 [get_bd_pins xlslice_2/Din]
|
||||
|
||||
#ILA
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins ila_controller/clk] $sys_100m_clk_source
|
||||
connect_bd_net -net foc_controller_mon_phase_voltage_a [get_bd_pins axi_mc_controller/ctrl_data0_i] [get_bd_pins foc_controller/mon_phase_voltage_a] [get_bd_pins ila_controller/probe0]
|
||||
connect_bd_net -net foc_controller_mon_phase_voltage_b [get_bd_pins axi_mc_controller/ctrl_data1_i] [get_bd_pins foc_controller/mon_phase_voltage_b] [get_bd_pins ila_controller/probe1]
|
||||
connect_bd_net -net foc_controller_mon_phase_current_a [get_bd_pins axi_mc_controller/ctrl_data2_i] [get_bd_pins foc_controller/mon_phase_current_a] [get_bd_pins ila_controller/probe2]
|
||||
connect_bd_net -net foc_controller_mon_phase_current_b [get_bd_pins axi_mc_controller/ctrl_data3_i] [get_bd_pins foc_controller/mon_phase_current_b] [get_bd_pins ila_controller/probe3]
|
||||
connect_bd_net -net foc_controller_mon_rotor_position [get_bd_pins foc_controller/mon_rotor_position] [get_bd_pins ila_controller/probe4]
|
||||
connect_bd_net -net foc_controller_mon_electrical_position [get_bd_pins axi_mc_controller/ctrl_data4_i] [get_bd_pins foc_controller/mon_electrical_position] [get_bd_pins ila_controller/probe5]
|
||||
connect_bd_net -net foc_controller_mon_rotor_velocity [get_bd_pins axi_mc_controller/ctrl_data5_i] [get_bd_pins foc_controller/mon_rotor_velocity] [get_bd_pins ila_controller/probe6]
|
||||
connect_bd_net -net foc_controller_mon_d_current [get_bd_pins ila_controller/probe7]
|
||||
connect_bd_net -net foc_controller_mon_q_current [get_bd_pins axi_mc_controller/ctrl_data7_i] [get_bd_pins foc_controller/mon_q_current] [get_bd_pins ila_controller/probe8]
|
||||
connect_bd_net -net axi_mc_current_monitor_1_i_ready_o [get_bd_pins ila_controller/probe9]
|
||||
|
||||
# interrupt
|
||||
|
||||
connect_bd_net -net axi_controller_dma_irq [get_bd_pins axi_controller_dma/irq] [get_bd_ports motcon1_ctrl_irq]
|
||||
|
||||
# xadc
|
||||
|
||||
# connect_bd_net -net sys_100m_clk [get_bd_pins xadc_wiz_1/s_axi_aclk] $sys_100m_clk_source
|
||||
# connect_bd_net -net sys_100m_resetn [get_bd_pins xadc_wiz_1/s_axi_aresetn] $sys_100m_resetn_source
|
||||
|
||||
# connect_bd_intf_net [get_bd_intf_pins xadc_wiz_1/Vp_Vn] [get_bd_intf_ports Vp_Vn]
|
||||
# connect_bd_intf_net [get_bd_intf_pins xadc_wiz_1/Vaux0] [get_bd_intf_ports Vaux0]
|
||||
# connect_bd_intf_net [get_bd_intf_pins xadc_wiz_1/Vaux8] [get_bd_intf_ports Vaux8]
|
||||
# connect_bd_net -net xadc_wiz_1_muxaddr_out [get_bd_ports muxaddr_out] [get_bd_pins xadc_wiz_1/muxaddr_out]
|
||||
|
||||
# interconnect (cpu)
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_mc_current_monitor_1/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_mc_speed_1/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_mc_controller/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_mc_current_monitor_2/s_axi]
|
||||
# connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins xadc_wiz_1/s_axi_lite]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_speed_detector_dma/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_current_monitor_1_dma/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_current_monitor_2_dma/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m15_axi [get_bd_intf_pins axi_cpu_interconnect/M15_AXI] [get_bd_intf_pins axi_controller_dma/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m16_axi [get_bd_intf_pins axi_cpu_interconnect/M16_AXI] [get_bd_intf_pins foc_controller/s_axi]
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M15_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M16_ACLK] $sys_100m_clk_source
|
||||
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M15_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M16_ARESETN] $sys_100m_resetn_source
|
||||
|
||||
#inteconnects (current monitor 1)
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_current_monitor_1/s_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mc_current_monitor_1/s_axi_aresetn] $sys_100m_resetn_source
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_current_monitor_1_dma/s_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_current_monitor_1_dma/s_axi_aresetn] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_current_monitor_1_dma/m_dest_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_current_monitor_1_dma/m_dest_axi_aresetn] $sys_100m_resetn_source
|
||||
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s01_axi [get_bd_intf_pins axi_mem_interconnect/S01_AXI] [get_bd_intf_pins axi_current_monitor_1_dma/m_dest_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S01_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S01_ARESETN] $sys_100m_resetn_source
|
||||
|
||||
#interconnect (current monitor 2)
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_current_monitor_2/s_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mc_current_monitor_2/s_axi_aresetn] $sys_100m_resetn_source
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_current_monitor_2_dma/s_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_current_monitor_2_dma/s_axi_aresetn] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_current_monitor_2_dma/m_dest_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_current_monitor_2_dma/m_dest_axi_aresetn] $sys_100m_resetn_source
|
||||
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s02_axi [get_bd_intf_pins axi_mem_interconnect/S02_AXI] [get_bd_intf_pins axi_current_monitor_2_dma/m_dest_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S02_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S02_ARESETN] $sys_100m_resetn_source
|
||||
|
||||
# interconnect (speed detector)
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_speed_1/s_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mc_speed_1/s_axi_aresetn] $sys_100m_resetn_source
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_speed_detector_dma/m_dest_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_speed_detector_dma/s_axi_aresetn] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_speed_detector_dma/s_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_speed_detector_dma/m_dest_axi_aresetn] $sys_100m_resetn_source
|
||||
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s00_axi [get_bd_intf_pins axi_mem_interconnect/S00_AXI] [get_bd_intf_pins axi_speed_detector_dma/m_dest_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S00_ARESETN] $sys_100m_resetn_source
|
||||
|
||||
# interconnect (controller)
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_controller/s_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mc_controller/s_axi_aresetn] $sys_100m_resetn_source
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_controller_dma/s_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_controller_dma/s_axi_aresetn] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_controller_dma/m_dest_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_controller_dma/m_dest_axi_aresetn] $sys_100m_resetn_source
|
||||
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s03_axi [get_bd_intf_pins axi_mem_interconnect/S03_AXI] [get_bd_intf_pins axi_controller_dma/m_dest_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S03_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S03_ARESETN] $sys_100m_resetn_source
|
||||
|
||||
# interconnect (dmas)
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/M00_ACLK] $sys_100m_clk_source
|
||||
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/M00_ARESETN] $sys_100m_resetn_source
|
||||
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_m00_axi [get_bd_intf_pins axi_mem_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1]
|
||||
|
||||
# address map
|
||||
|
||||
create_bd_addr_seg -range 0x10000 -offset 0x40400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_current_monitor_1_dma/s_axi/axi_lite] SEG_data_c_m_1_dma
|
||||
create_bd_addr_seg -range 0x10000 -offset 0x40410000 $sys_addr_cntrl_space [get_bd_addr_segs axi_speed_detector_dma/s_axi/axi_lite] SEG_data_s_d_dma
|
||||
create_bd_addr_seg -range 0x10000 -offset 0x40420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_controller_dma/s_axi/axi_lite] SEG_data_t_c_dma
|
||||
create_bd_addr_seg -range 0x10000 -offset 0x40430000 $sys_addr_cntrl_space [get_bd_addr_segs axi_current_monitor_2_dma/s_axi/axi_lite] SEG_data_c_m_2_dma
|
||||
create_bd_addr_seg -range 0x10000 -offset 0x40500000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_current_monitor_1/s_axi/axi_lite] SEG_data_c_m_1
|
||||
create_bd_addr_seg -range 0x10000 -offset 0x40510000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_speed_1/s_axi/axi_lite] SEG_data_s_d
|
||||
create_bd_addr_seg -range 0x10000 -offset 0x40520000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_controller/s_axi/axi_lite] SEG_data_t_c
|
||||
create_bd_addr_seg -range 0x10000 -offset 0x40530000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_current_monitor_2/s_axi/axi_lite] SEG_data_c_m_2
|
||||
# create_bd_addr_seg -range 0x10000 -offset 0x43200000 $sys_addr_cntrl_space [get_bd_addr_segs xadc_wiz_1/s_axi_lite/Reg] SEG_data_xadc
|
||||
create_bd_addr_seg -range 0x4000000 -offset 0x7C000000 $sys_addr_cntrl_space [get_bd_addr_segs foc_controller/s_axi/axi_lite] SEG_foc_controller_f_c
|
||||
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_current_monitor_1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_speed_detector_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_controller_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_current_monitor_2_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
|
||||
|
|
@ -1,86 +0,0 @@
|
|||
# Motor Control
|
||||
|
||||
set_property PACKAGE_PIN J16 [get_ports {position_i[0]}]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports {position_i[0]}]
|
||||
set_property PACKAGE_PIN J17 [get_ports {position_i[1]}]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports {position_i[1]}]
|
||||
set_property PACKAGE_PIN G15 [get_ports {position_i[2]}]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports {position_i[2]}]
|
||||
|
||||
set_property PACKAGE_PIN A16 [get_ports pwm_ah_o]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports pwm_ah_o]
|
||||
set_property PACKAGE_PIN A17 [get_ports pwm_al_o]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports pwm_al_o]
|
||||
set_property PACKAGE_PIN C15 [get_ports pwm_bh_o]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports pwm_bh_o]
|
||||
set_property PACKAGE_PIN B15 [get_ports pwm_bl_o]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports pwm_bl_o]
|
||||
set_property PACKAGE_PIN A21 [get_ports pwm_ch_o]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports pwm_ch_o]
|
||||
set_property PACKAGE_PIN A22 [get_ports pwm_cl_o]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports pwm_cl_o]
|
||||
set_property PACKAGE_PIN L21 [get_ports fmc_m1_en_o]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports fmc_m1_en_o]
|
||||
set_property PACKAGE_PIN L22 [get_ports fmc_m1_fault_i]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports fmc_m1_fault_i]
|
||||
|
||||
set_property PACKAGE_PIN T16 [get_ports adc_ia_dat_i]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports adc_ia_dat_i]
|
||||
set_property PACKAGE_PIN T17 [get_ports adc_ib_dat_i]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports adc_ib_dat_i]
|
||||
set_property PACKAGE_PIN N17 [get_ports adc_it_dat_i]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports adc_it_dat_i]
|
||||
set_property PACKAGE_PIN N18 [get_ports adc_vbus_dat_i]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports adc_vbus_dat_i]
|
||||
|
||||
set_property PACKAGE_PIN P17 [get_ports adc_ia_clk_o]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports adc_ia_clk_o]
|
||||
set_property PACKAGE_PIN P18 [get_ports adc_ib_clk_o]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports adc_ib_clk_o]
|
||||
set_property PACKAGE_PIN M21 [get_ports adc_it_clk_o]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports adc_it_clk_o]
|
||||
set_property PACKAGE_PIN M22 [get_ports adc_vbus_clk_o]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports adc_vbus_clk_o]
|
||||
|
||||
set_property PACKAGE_PIN A18 [get_ports {gpo_o[0]}]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports {gpo_o[0]}]
|
||||
set_property PACKAGE_PIN A19 [get_ports {gpo_o[1]}]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports {gpo_o[1]}]
|
||||
set_property PACKAGE_PIN R19 [get_ports {gpo_o[2]}]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports {gpo_o[2]}]
|
||||
set_property PACKAGE_PIN T19 [get_ports {gpo_o[3]}]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports {gpo_o[3]}]
|
||||
set_property PACKAGE_PIN D21 [get_ports {gpo_o[4]}]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports {gpo_o[4]}]
|
||||
set_property PACKAGE_PIN J22 [get_ports {gpo_o[5]}]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports {gpo_o[5]}]
|
||||
set_property PACKAGE_PIN G16 [get_ports {gpo_o[6]}]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports {gpo_o[6]}]
|
||||
set_property PACKAGE_PIN M19 [get_ports {gpo_o[7]}]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports {gpo_o[7]}]
|
||||
|
||||
set_property PACKAGE_PIN B17 [get_ports adc_ia_dat_d_i]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports adc_ia_dat_d_i]
|
||||
set_property PACKAGE_PIN B21 [get_ports adc_ib_dat_d_i]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports adc_ib_dat_d_i]
|
||||
set_property PACKAGE_PIN B22 [get_ports adc_it_dat_d_i]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports adc_it_dat_d_i]
|
||||
|
||||
set_property PACKAGE_PIN D20 [get_ports adc_ia_clk_d_o]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports adc_ia_clk_d_o]
|
||||
set_property PACKAGE_PIN C20 [get_ports adc_ib_clk_d_o]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports adc_ib_clk_d_o]
|
||||
set_property PACKAGE_PIN E21 [get_ports adc_it_clk_d_o]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports adc_it_clk_d_o]
|
||||
|
||||
|
||||
#set_property PACKAGE_PIN H15 [get_ports {muxaddr_out[0]}]
|
||||
#set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[0]}]
|
||||
#set_property PACKAGE_PIN R15 [get_ports {muxaddr_out[1]}]
|
||||
#set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[1]}]
|
||||
#set_property PACKAGE_PIN K15 [get_ports {muxaddr_out[2]}]
|
||||
#set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[2]}]
|
||||
#set_property PACKAGE_PIN J15 [get_ports {muxaddr_out[3]}]
|
||||
#set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[3]}]
|
||||
|
||||
set_false_path -through [get_pins {i_system_wrapper/system_i/foc_controller/inst*/*/*/*}]
|
||||
|
|
@ -0,0 +1,706 @@
|
|||
|
||||
# motor control
|
||||
|
||||
|
||||
# port definition
|
||||
|
||||
|
||||
# gpio
|
||||
set_property LEFT 34 [get_bd_ports GPIO_I]
|
||||
set_property LEFT 34 [get_bd_ports GPIO_O]
|
||||
set_property LEFT 34 [get_bd_ports GPIO_T]
|
||||
|
||||
# position detection interface
|
||||
set position_m1_i [ create_bd_port -dir I -from 2 -to 0 position_m1_i ]
|
||||
set position_m2_i [ create_bd_port -dir I -from 2 -to 0 position_m2_i ]
|
||||
|
||||
# current monitor interface
|
||||
# clock
|
||||
set adc_clk_o [ create_bd_port -dir O adc_clk_o ]
|
||||
# data motor 1
|
||||
set adc_m1_ia_dat_i [ create_bd_port -dir I adc_m1_ia_dat_i ]
|
||||
set adc_m1_ib_dat_i [ create_bd_port -dir I adc_m1_ib_dat_i ]
|
||||
set adc_m1_vbus_dat_i [ create_bd_port -dir I adc_m1_vbus_dat_i ]
|
||||
# data motor 2
|
||||
set adc_m2_ia_dat_i [ create_bd_port -dir I adc_m2_ia_dat_i ]
|
||||
set adc_m2_ib_dat_i [ create_bd_port -dir I adc_m2_ib_dat_i ]
|
||||
set adc_m2_vbus_dat_i [ create_bd_port -dir I adc_m2_vbus_dat_i ]
|
||||
|
||||
# motor control interface
|
||||
set gpo_o [ create_bd_port -dir o -from 3 -to 0 gpo_o]
|
||||
# motor 1
|
||||
set fmc_m1_en_o [ create_bd_port -dir O fmc_m1_en_o]
|
||||
set pwm_m1_al_o [ create_bd_port -dir O pwm_m1_al_o]
|
||||
set pwm_m1_ah_o [ create_bd_port -dir O pwm_m1_ah_o]
|
||||
set pwm_m1_cl_o [ create_bd_port -dir O pwm_m1_cl_o]
|
||||
set pwm_m1_ch_o [ create_bd_port -dir O pwm_m1_ch_o]
|
||||
set pwm_m1_bl_o [ create_bd_port -dir O pwm_m1_bl_o]
|
||||
set pwm_m1_bh_o [ create_bd_port -dir O pwm_m1_bh_o]
|
||||
# motor 2
|
||||
set fmc_m2_en_o [ create_bd_port -dir O fmc_m2_en_o]
|
||||
set pwm_m2_al_o [ create_bd_port -dir O pwm_m2_al_o]
|
||||
set pwm_m2_ah_o [ create_bd_port -dir O pwm_m2_ah_o]
|
||||
set pwm_m2_cl_o [ create_bd_port -dir O pwm_m2_cl_o]
|
||||
set pwm_m2_ch_o [ create_bd_port -dir O pwm_m2_ch_o]
|
||||
set pwm_m2_bl_o [ create_bd_port -dir O pwm_m2_bl_o]
|
||||
set pwm_m2_bh_o [ create_bd_port -dir O pwm_m2_bh_o]
|
||||
|
||||
# interrupts
|
||||
set motcon2_c_m1_intr [create_bd_port -dir O motcon2_c_m1_intr]
|
||||
set motcon2_c_m2_intr [create_bd_port -dir O motcon2_c_m2_intr]
|
||||
set motcon2_s_d1_intr [create_bd_port -dir O motcon2_s_d1_intr]
|
||||
set motcon2_s_d2_intr [create_bd_port -dir O motcon2_s_d2_intr]
|
||||
set motcon2_ctrl_m1_intr [ create_bd_port -dir O -type intr motcon2_ctrl_m1_intr ]
|
||||
set motcon2_ctrl_m2_intr [ create_bd_port -dir O -type intr motcon2_ctrl_m2_intr ]
|
||||
|
||||
# Ethernet
|
||||
# phy 1
|
||||
set eth1_rgmii [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rgmii_rtl:1.0 eth1_rgmii ]
|
||||
# phy 2
|
||||
set eth2_rgmii [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rgmii_rtl:1.0 eth2_rgmii ]
|
||||
#common mdio interface
|
||||
set eth_mdio_mdc [ create_bd_port -dir O eth_mdio_mdc ]
|
||||
set eth_mdio_o [ create_bd_port -dir O eth_mdio_o ]
|
||||
set eth_mdio_t [ create_bd_port -dir O eth_mdio_t ]
|
||||
set eth_mdio_i [ create_bd_port -dir I eth_mdio_i ]
|
||||
#common reset
|
||||
set eth_phy_rst_n [ create_bd_port -dir O eth_phy_rst_n ]
|
||||
# reference clock for the delay interface used for the gmii to rgmii conversion
|
||||
set refclk [ create_bd_port -dir o -type clk refclk ]
|
||||
set refclk_rst [ create_bd_port -dir o -from 0 -to 0 -type rst refclk_rst ]
|
||||
|
||||
# iic
|
||||
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_ee2
|
||||
set iic_ee2_intr [create_bd_port -dir O iic_ee2_intr]
|
||||
|
||||
# spi
|
||||
set spi_csn_i [create_bd_port -dir I spi_csn_i]
|
||||
set spi_csn_o [create_bd_port -dir O spi_csn_o]
|
||||
set spi_sclk_i [create_bd_port -dir I spi_sclk_i]
|
||||
set spi_sclk_o [create_bd_port -dir O spi_sclk_o]
|
||||
set spi_mosi_i [create_bd_port -dir I spi_mosi_i]
|
||||
set spi_mosi_o [create_bd_port -dir O spi_mosi_o]
|
||||
set spi_miso_i [create_bd_port -dir I spi_miso_i]
|
||||
|
||||
# xadc interface
|
||||
#create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0
|
||||
#create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8
|
||||
#create_bd_port -dir O -from 4 -to 0 muxaddr_out
|
||||
|
||||
|
||||
# core instantiation and configuration
|
||||
|
||||
|
||||
# additions to default configuration
|
||||
# increase cpu interconnect to accomodate new cores
|
||||
set_property -dict [list CONFIG.NUM_MI {21}] $axi_cpu_interconnect
|
||||
# Enable additional peripherals from the PS7 block
|
||||
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1} ] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_ENET0_ENET0_IO {EMIO} ] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {1} ] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {35}] $sys_ps7
|
||||
|
||||
# Add additional clocks to be used by gmii to rgmii modules and current monitoring modules
|
||||
set_property -dict [ list CONFIG.CLKOUT2_USED {true} ] $sys_audio_clkgen
|
||||
set_property -dict [ list CONFIG.CLKOUT3_USED {true} ] $sys_audio_clkgen
|
||||
set_property -dict [ list CONFIG.CLKOUT4_USED {true} ] $sys_audio_clkgen
|
||||
set_property -dict [ list CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {125} ] $sys_audio_clkgen
|
||||
set_property -dict [ list CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {25} ] $sys_audio_clkgen
|
||||
set_property -dict [ list CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {20} ] $sys_audio_clkgen
|
||||
|
||||
# speed detectors
|
||||
# speed detector core motor 1
|
||||
set speed_detector_m1 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_speed:1.0 speed_detector_m1 ]
|
||||
# dma motor 1
|
||||
set speed_detector_m1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 speed_detector_m1_dma]
|
||||
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $speed_detector_m1_dma
|
||||
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $speed_detector_m1_dma
|
||||
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $speed_detector_m1_dma
|
||||
set_property -dict [list CONFIG.C_CYCLIC {0}] $speed_detector_m1_dma
|
||||
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $speed_detector_m1_dma
|
||||
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {32}] $speed_detector_m1_dma
|
||||
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $speed_detector_m1_dma
|
||||
set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {0}] $speed_detector_m1_dma
|
||||
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $speed_detector_m1_dma
|
||||
# speed detector core motor 2
|
||||
set speed_detector_m2 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_speed:1.0 speed_detector_m2 ]
|
||||
# dma motor 2
|
||||
set speed_detector_m2_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 speed_detector_m2_dma]
|
||||
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $speed_detector_m2_dma
|
||||
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $speed_detector_m2_dma
|
||||
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $speed_detector_m2_dma
|
||||
set_property -dict [list CONFIG.C_CYCLIC {0}] $speed_detector_m2_dma
|
||||
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $speed_detector_m2_dma
|
||||
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {32}] $speed_detector_m2_dma
|
||||
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $speed_detector_m2_dma
|
||||
set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {0}] $speed_detector_m2_dma
|
||||
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $speed_detector_m2_dma
|
||||
|
||||
# current monitor peripherals
|
||||
# current monitor core motor 1
|
||||
set current_monitor_m1 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_current_monitor:1.0 current_monitor_m1 ]
|
||||
# dma motor 1
|
||||
set current_monitor_m1_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 current_monitor_m1_dma ]
|
||||
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $current_monitor_m1_dma
|
||||
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $current_monitor_m1_dma
|
||||
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $current_monitor_m1_dma
|
||||
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $current_monitor_m1_dma
|
||||
set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {0}] $current_monitor_m1_dma
|
||||
set_property -dict [list CONFIG.C_CYCLIC {0}] $current_monitor_m1_dma
|
||||
# data packer motor 1
|
||||
#
|
||||
set current_monitor_m1_apack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 current_monitor_m1_apack]
|
||||
set_property -dict [list CONFIG.CHANNELS {4}] $current_monitor_m1_apack
|
||||
# set current_monitor_m1_pack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 current_monitor_m1_pack ]
|
||||
# set_property -dict [ list CONFIG.CH_CNT {4} ] $current_monitor_m1_pack
|
||||
# set_property -dict [ list CONFIG.CH_DW {16} ] $current_monitor_m1_pack
|
||||
|
||||
# current monitor core motor 2
|
||||
set current_monitor_m2 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_current_monitor:1.0 current_monitor_m2 ]
|
||||
# dma motor 2
|
||||
set current_monitor_m2_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 current_monitor_m2_dma ]
|
||||
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $current_monitor_m2_dma
|
||||
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $current_monitor_m2_dma
|
||||
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $current_monitor_m2_dma
|
||||
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $current_monitor_m2_dma
|
||||
set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {0}] $current_monitor_m2_dma
|
||||
set_property -dict [list CONFIG.C_CYCLIC {0}] $current_monitor_m2_dma
|
||||
# data packer motor 2
|
||||
set current_monitor_m2_apack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 current_monitor_m2_apack]
|
||||
set_property -dict [list CONFIG.CHANNELS {4}] $current_monitor_m2_apack
|
||||
#set current_monitor_m2_pack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 current_monitor_m2_pack ]
|
||||
#set_property -dict [ list CONFIG.CH_CNT {4} ] $current_monitor_m2_pack
|
||||
#set_property -dict [ list CONFIG.CH_DW {16} ] $current_monitor_m2_pack
|
||||
|
||||
#controller
|
||||
# controller core motor 1
|
||||
set controller_m1 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_controller:1.0 controller_m1 ]
|
||||
# dma motor 1
|
||||
set controller_m1_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 controller_m1_dma ]
|
||||
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $controller_m1_dma
|
||||
set_property -dict [list CONFIG.C_CYCLIC {0}] $controller_m1_dma
|
||||
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {256}] $controller_m1_dma
|
||||
# data packer motor 1
|
||||
set controller_m1_apack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 controller_m1_apack]
|
||||
set_property -dict [list CONFIG.CHANNELS {8}] $controller_m1_apack
|
||||
set_property -dict [list CONFIG.DATA_WIDTH {32}] $controller_m1_apack
|
||||
|
||||
#set controller_m1_pack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 controller_m1_pack ]
|
||||
#set_property -dict [ list CONFIG.CH_CNT {8} ] $controller_m1_pack
|
||||
#set_property -dict [ list CONFIG.CH_DW {32} ] $controller_m1_pack
|
||||
# controller core motor 2
|
||||
set controller_m2 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_controller:1.0 controller_m2 ]
|
||||
# dma motor 2
|
||||
set controller_m2_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 controller_m2_dma ]
|
||||
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $controller_m2_dma
|
||||
set_property -dict [list CONFIG.C_CYCLIC {0}] $controller_m2_dma
|
||||
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {256}] $controller_m2_dma
|
||||
# data packer motor 2
|
||||
#set controller_m2_pack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 controller_m2_pack ]
|
||||
#set_property -dict [ list CONFIG.CH_CNT {8} ] $controller_m2_pack
|
||||
set controller_m2_apack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 controller_m2_apack]
|
||||
set_property -dict [list CONFIG.CHANNELS {8}] $controller_m2_apack
|
||||
set_property -dict [list CONFIG.DATA_WIDTH {32}] $controller_m2_apack
|
||||
|
||||
#ethernet gmii to rgmii converters
|
||||
# phy 1
|
||||
set gmii_to_rgmii_eth1 [ create_bd_cell -type ip -vlnv analog.com:user:util_gmii_to_rgmii:1.0 gmii_to_rgmii_eth1 ]
|
||||
set_property -dict [list CONFIG.PHY_AD {"00000"}] [get_bd_cells gmii_to_rgmii_eth1]
|
||||
# phy 2
|
||||
set gmii_to_rgmii_eth2 [ create_bd_cell -type ip -vlnv analog.com:user:util_gmii_to_rgmii:1.0 gmii_to_rgmii_eth2 ]
|
||||
set_property -dict [list CONFIG.PHY_AD {"00001"}] [get_bd_cells gmii_to_rgmii_eth2]
|
||||
|
||||
# iic
|
||||
set iic_ee2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 iic_ee2 ]
|
||||
|
||||
# xadc
|
||||
#set xadc_core [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.0 xadc_core ]
|
||||
#set_property -dict [ list CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} ] $xadc_core
|
||||
#set_property -dict [ list CONFIG.ENABLE_EXTERNAL_MUX {true} ] $xadc_core
|
||||
#set_property -dict [ list CONFIG.EXTERNAL_MUX_CHANNEL {VAUXP0_VAUXN0} ] $xadc_core
|
||||
#set_property -dict [ list CONFIG.OT_ALARM {false} ] $xadc_core
|
||||
#set_property -dict [ list CONFIG.USER_TEMP_ALARM {false} ] $xadc_core
|
||||
#set_property -dict [ list CONFIG.VCCAUX_ALARM {false} ] $xadc_core
|
||||
#set_property -dict [ list CONFIG.VCCINT_ALARM {false} ] $xadc_core
|
||||
|
||||
# additional interconnect
|
||||
set axi_mem_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_interconnect ]
|
||||
set_property -dict [ list CONFIG.NUM_SI {6} CONFIG.NUM_MI {1} ] $axi_mem_interconnect
|
||||
|
||||
|
||||
# connections
|
||||
|
||||
|
||||
# speed detector
|
||||
# motor 1
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m1/s_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m1/ref_clk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins speed_detector_m1/s_axi_aresetn] $sys_100m_resetn_source
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m1_dma/s_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m1_dma/m_dest_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m1_dma/fifo_wr_clk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins speed_detector_m1_dma/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins speed_detector_m1_dma/m_dest_axi_aresetn]
|
||||
|
||||
connect_bd_net -net position_m1_i_1 [get_bd_ports position_m1_i] [get_bd_pins speed_detector_m1/position_i]
|
||||
connect_bd_net -net speed_detector_adc_new_speed_m1 [get_bd_pins speed_detector_m1/new_speed_o] [get_bd_pins speed_detector_m1_dma/fifo_wr_en]
|
||||
connect_bd_net -net speed_detector_adc_speed_m1 [get_bd_pins speed_detector_m1/speed_o] [get_bd_pins speed_detector_m1_dma/fifo_wr_din]
|
||||
# motor 2
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m2/s_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m2/ref_clk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins speed_detector_m2/s_axi_aresetn] $sys_100m_resetn_source
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m2_dma/s_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m2_dma/m_dest_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m2_dma/fifo_wr_clk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins speed_detector_m2_dma/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins speed_detector_m2_dma/m_dest_axi_aresetn]
|
||||
|
||||
connect_bd_net -net position_m2_i_1 [get_bd_ports position_m2_i] [get_bd_pins speed_detector_m2/position_i]
|
||||
connect_bd_net -net speed_detector_adc_new_speed_m2 [get_bd_pins speed_detector_m2/new_speed_o] [get_bd_pins speed_detector_m2_dma/fifo_wr_en]
|
||||
connect_bd_net -net speed_detector_adc_speed_m2 [get_bd_pins speed_detector_m2/speed_o] [get_bd_pins speed_detector_m2_dma/fifo_wr_din]
|
||||
|
||||
# interrupt
|
||||
connect_bd_net -net speed_detector_m1_dma_intr [get_bd_pins speed_detector_m1_dma/irq] [get_bd_ports motcon2_s_d1_intr]
|
||||
connect_bd_net -net speed_detector_m2_dma_intr [get_bd_pins speed_detector_m2_dma/irq] [get_bd_ports motcon2_s_d2_intr]
|
||||
|
||||
# current monitor
|
||||
connect_bd_net -net current_monitor_m1_adc_clk_o [get_bd_ports adc_clk_o] [get_bd_pins current_monitor_m1/adc_clk_o]
|
||||
# motor 1
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m1/ref_clk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m1/s_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m1/s_axi_aresetn] $sys_100m_resetn_source
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m1_dma/s_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m1_dma/m_dest_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m1_dma/fifo_wr_clk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m1_dma/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m1_dma/m_dest_axi_aresetn]
|
||||
|
||||
connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins current_monitor_m1/adc_clk_i] [get_bd_pins sys_audio_clkgen/clk_out4]
|
||||
connect_bd_net -net adc_m1_ia_dat_i_1 [get_bd_ports adc_m1_ia_dat_i] [get_bd_pins current_monitor_m1/adc_ia_dat_i]
|
||||
connect_bd_net -net adc_m1_ib_dat_i_1 [get_bd_ports adc_m1_ib_dat_i] [get_bd_pins current_monitor_m1/adc_ib_dat_i]
|
||||
connect_bd_net -net adc_m1_vbus_dat_i_1 [get_bd_ports adc_m1_vbus_dat_i] [get_bd_pins current_monitor_m1/adc_vbus_dat_i]
|
||||
|
||||
connect_bd_net -net [get_bd_nets sys_100m_clk] [get_bd_pins current_monitor_m1_apack/clk] [get_bd_pins sys_ps7/FCLK_CLK0]
|
||||
connect_bd_net -net current_monitor_m1_adc_enable_ia [get_bd_pins current_monitor_m1/adc_enable_ia] [get_bd_pins current_monitor_m1_apack/chan_enable_0]
|
||||
connect_bd_net -net current_monitor_m1_adc_enable_ib [get_bd_pins current_monitor_m1/adc_enable_ib] [get_bd_pins current_monitor_m1_apack/chan_enable_1]
|
||||
connect_bd_net -net current_monitor_m1_adc_enable_vbus [get_bd_pins current_monitor_m1/adc_enable_vbus] [get_bd_pins current_monitor_m1_apack/chan_enable_2]
|
||||
connect_bd_net -net current_monitor_m1_adc_enable_stub [get_bd_pins current_monitor_m1/adc_enable_stub] [get_bd_pins current_monitor_m1_apack/chan_enable_3]
|
||||
connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_apack/chan_valid_0] [get_bd_pins current_monitor_m1/i_ready_o]
|
||||
connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_apack/chan_valid_1] [get_bd_pins current_monitor_m1/i_ready_o]
|
||||
connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_apack/chan_valid_2] [get_bd_pins current_monitor_m1/i_ready_o]
|
||||
connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_apack/chan_valid_3] [get_bd_pins current_monitor_m1/i_ready_o]
|
||||
connect_bd_net [get_bd_pins current_monitor_m1/ia_o] [get_bd_pins current_monitor_m1_apack/chan_data_0]
|
||||
connect_bd_net [get_bd_pins current_monitor_m1/ib_o] [get_bd_pins current_monitor_m1_apack/chan_data_1]
|
||||
connect_bd_net [get_bd_pins current_monitor_m1/vbus_o] [get_bd_pins current_monitor_m1_apack/chan_data_2]
|
||||
connect_bd_net [get_bd_pins current_monitor_m1/vbus_o] [get_bd_pins current_monitor_m1_apack/chan_data_3]
|
||||
connect_bd_net [get_bd_pins current_monitor_m1_apack/ddata] [get_bd_pins current_monitor_m1_dma/fifo_wr_din]
|
||||
connect_bd_net [get_bd_pins current_monitor_m1_apack/dvalid] [get_bd_pins current_monitor_m1_dma/fifo_wr_en]
|
||||
|
||||
# connect_bd_net -net [get_bd_nets sys_100m_clk] [get_bd_pins current_monitor_m1_pack/adc_clk] [get_bd_pins sys_ps7/FCLK_CLK0]
|
||||
# connect_bd_net -net [get_bd_nets sys_rstgen_peripheral_reset] [get_bd_pins current_monitor_m1_pack/adc_rst] [get_bd_pins sys_rstgen/peripheral_reset]
|
||||
# connect_bd_net -net current_monitor_m1_adc_enable_ia [get_bd_pins current_monitor_m1/adc_enable_ia] [get_bd_pins current_monitor_m1_pack/adc_enable_0]
|
||||
# connect_bd_net -net current_monitor_m1_adc_enable_ib [get_bd_pins current_monitor_m1/adc_enable_ib] [get_bd_pins current_monitor_m1_pack/adc_enable_1]
|
||||
# connect_bd_net -net current_monitor_m1_adc_enable_vbus [get_bd_pins current_monitor_m1/adc_enable_vbus] [get_bd_pins current_monitor_m1_pack/adc_enable_2]
|
||||
# connect_bd_net -net current_monitor_m1_adc_enable_stub [get_bd_pins current_monitor_m1/adc_enable_stub] [get_bd_pins current_monitor_m1_pack/adc_enable_3]
|
||||
# connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_pack/adc_valid_0] [get_bd_pins current_monitor_m1/i_ready_o]
|
||||
# connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_pack/adc_valid_1] [get_bd_pins current_monitor_m1/i_ready_o]
|
||||
# connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_pack/adc_valid_2] [get_bd_pins current_monitor_m1/i_ready_o]
|
||||
# connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_pack/adc_valid_3] [get_bd_pins current_monitor_m1/i_ready_o]
|
||||
# connect_bd_net [get_bd_pins current_monitor_m1/ia_o] [get_bd_pins current_monitor_m1_pack/adc_data_0]
|
||||
# connect_bd_net [get_bd_pins current_monitor_m1/ib_o] [get_bd_pins current_monitor_m1_pack/adc_data_1]
|
||||
# connect_bd_net [get_bd_pins current_monitor_m1/vbus_o] [get_bd_pins current_monitor_m1_pack/adc_data_2]
|
||||
# connect_bd_net [get_bd_pins current_monitor_m1/vbus_o] [get_bd_pins current_monitor_m1_pack/adc_data_3]
|
||||
# connect_bd_net [get_bd_pins current_monitor_m1_pack/adc_data] [get_bd_pins current_monitor_m1_dma/fifo_wr_din]
|
||||
# connect_bd_net [get_bd_pins current_monitor_m1_pack/adc_valid] [get_bd_pins current_monitor_m1_dma/fifo_wr_en]
|
||||
|
||||
# motor 2
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m2/ref_clk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m2/s_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m2/s_axi_aresetn] $sys_100m_resetn_source
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m2_dma/m_dest_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m2_dma/fifo_wr_clk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m2_dma/s_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m2_dma/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m2_dma/m_dest_axi_aresetn]
|
||||
|
||||
connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins current_monitor_m2/adc_clk_i] [get_bd_pins sys_audio_clkgen/clk_out4]
|
||||
connect_bd_net -net adc_m2_ia_dat_i_1 [get_bd_ports adc_m2_ia_dat_i] [get_bd_pins current_monitor_m2/adc_ia_dat_i]
|
||||
connect_bd_net -net adc_m2_ib_dat_i_1 [get_bd_ports adc_m2_ib_dat_i] [get_bd_pins current_monitor_m2/adc_ib_dat_i]
|
||||
connect_bd_net -net adc_m2_vbus_dat_i_1 [get_bd_ports adc_m2_vbus_dat_i] [get_bd_pins current_monitor_m2/adc_vbus_dat_i]
|
||||
|
||||
connect_bd_net -net [get_bd_nets sys_100m_clk] [get_bd_pins current_monitor_m2_apack/clk] [get_bd_pins sys_ps7/FCLK_CLK0]
|
||||
connect_bd_net -net current_monitor_m2_adc_enable_ia [get_bd_pins current_monitor_m2/adc_enable_ia] [get_bd_pins current_monitor_m2_apack/chan_enable_0]
|
||||
connect_bd_net -net current_monitor_m2_adc_enable_ib [get_bd_pins current_monitor_m2/adc_enable_ib] [get_bd_pins current_monitor_m2_apack/chan_enable_1]
|
||||
connect_bd_net -net current_monitor_m2_adc_enable_vbus [get_bd_pins current_monitor_m2/adc_enable_vbus] [get_bd_pins current_monitor_m2_apack/chan_enable_2]
|
||||
connect_bd_net -net current_monitor_m2_adc_enable_stub [get_bd_pins current_monitor_m2/adc_enable_stub] [get_bd_pins current_monitor_m2_apack/chan_enable_3]
|
||||
connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_apack/chan_valid_0] [get_bd_pins current_monitor_m2/i_ready_o]
|
||||
connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_apack/chan_valid_1] [get_bd_pins current_monitor_m2/i_ready_o]
|
||||
connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_apack/chan_valid_2] [get_bd_pins current_monitor_m2/i_ready_o]
|
||||
connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_apack/chan_valid_3] [get_bd_pins current_monitor_m2/i_ready_o]
|
||||
connect_bd_net [get_bd_pins current_monitor_m2/ia_o] [get_bd_pins current_monitor_m2_apack/chan_data_0]
|
||||
connect_bd_net [get_bd_pins current_monitor_m2/ib_o] [get_bd_pins current_monitor_m2_apack/chan_data_1]
|
||||
connect_bd_net [get_bd_pins current_monitor_m2/vbus_o] [get_bd_pins current_monitor_m2_apack/chan_data_2]
|
||||
connect_bd_net [get_bd_pins current_monitor_m2/vbus_o] [get_bd_pins current_monitor_m2_apack/chan_data_3]
|
||||
connect_bd_net [get_bd_pins current_monitor_m2_apack/ddata] [get_bd_pins current_monitor_m2_dma/fifo_wr_din]
|
||||
connect_bd_net [get_bd_pins current_monitor_m2_apack/dvalid] [get_bd_pins current_monitor_m2_dma/fifo_wr_en]
|
||||
# connect_bd_net -net [get_bd_nets sys_100m_clk] [get_bd_pins current_monitor_m2_pack/adc_clk] [get_bd_pins sys_ps7/FCLK_CLK0]
|
||||
# connect_bd_net -net [get_bd_nets sys_rstgen_peripheral_reset] [get_bd_pins current_monitor_m2_pack/adc_rst] [get_bd_pins sys_rstgen/peripheral_reset]
|
||||
# connect_bd_net -net current_monitor_m2_adc_enable_ia [get_bd_pins current_monitor_m2/adc_enable_ia] [get_bd_pins current_monitor_m2_pack/adc_enable_0]
|
||||
# connect_bd_net -net current_monitor_m2_adc_enable_ib [get_bd_pins current_monitor_m2/adc_enable_ib] [get_bd_pins current_monitor_m2_pack/adc_enable_1]
|
||||
# connect_bd_net -net current_monitor_m2_adc_enable_vbus [get_bd_pins current_monitor_m2/adc_enable_vbus] [get_bd_pins current_monitor_m2_pack/adc_enable_2]
|
||||
# connect_bd_net -net current_monitor_m2_adc_enable_stub [get_bd_pins current_monitor_m2/adc_enable_stub] [get_bd_pins current_monitor_m2_pack/adc_enable_3]
|
||||
# connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_pack/adc_valid_0] [get_bd_pins current_monitor_m2/i_ready_o]
|
||||
# connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_pack/adc_valid_1] [get_bd_pins current_monitor_m2/i_ready_o]
|
||||
# connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_pack/adc_valid_2] [get_bd_pins current_monitor_m2/i_ready_o]
|
||||
# connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_pack/adc_valid_3] [get_bd_pins current_monitor_m2/i_ready_o]
|
||||
# connect_bd_net [get_bd_pins current_monitor_m2/ia_o] [get_bd_pins current_monitor_m2_pack/adc_data_0]
|
||||
# connect_bd_net [get_bd_pins current_monitor_m2/ib_o] [get_bd_pins current_monitor_m2_pack/adc_data_1]
|
||||
# connect_bd_net [get_bd_pins current_monitor_m2/vbus_o] [get_bd_pins current_monitor_m2_pack/adc_data_2]
|
||||
# connect_bd_net [get_bd_pins current_monitor_m2/vbus_o] [get_bd_pins current_monitor_m2_pack/adc_data_3]
|
||||
# connect_bd_net [get_bd_pins current_monitor_m2_pack/adc_valid] [get_bd_pins current_monitor_m2_dma/fifo_wr_en]
|
||||
# connect_bd_net [get_bd_pins current_monitor_m2_pack/adc_data] [get_bd_pins current_monitor_m2_dma/fifo_wr_din]
|
||||
|
||||
# interrupts
|
||||
connect_bd_net -net axi_current_monitor_1_dma_intr [get_bd_pins current_monitor_m1_dma/irq] [get_bd_ports motcon2_c_m1_intr]
|
||||
connect_bd_net -net axi_current_monitor_2_dma_intr [get_bd_pins current_monitor_m2_dma/irq] [get_bd_ports motcon2_c_m2_intr]
|
||||
|
||||
#controller
|
||||
# motor 1
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1/ref_clk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1/s_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins controller_m1/ctrl_data_clk] [get_bd_pins sys_audio_clkgen/clk_out4]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins controller_m1/s_axi_aresetn] $sys_100m_resetn_source
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1_dma/s_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1_dma/m_dest_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1_dma/fifo_wr_clk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins controller_m1_dma/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins controller_m1_dma/m_dest_axi_aresetn]
|
||||
|
||||
connect_bd_net -net axi_mc_controller_fmc_m1_en_o [get_bd_ports fmc_m1_en_o] [get_bd_pins controller_m1/fmc_m1_en_o]
|
||||
connect_bd_net -net axi_mc_controller_m1_pwm_al_o [get_bd_ports pwm_m1_al_o] [get_bd_pins controller_m1/pwm_al_o]
|
||||
connect_bd_net -net axi_mc_controller_m1_pwm_ah_o [get_bd_ports pwm_m1_ah_o] [get_bd_pins controller_m1/pwm_ah_o]
|
||||
connect_bd_net -net axi_mc_controller_m1_pwm_bl_o [get_bd_ports pwm_m1_bl_o] [get_bd_pins controller_m1/pwm_bl_o]
|
||||
connect_bd_net -net axi_mc_controller_m1_pwm_bh_o [get_bd_ports pwm_m1_bh_o] [get_bd_pins controller_m1/pwm_bh_o]
|
||||
connect_bd_net -net axi_mc_controller_m1_pwm_cl_o [get_bd_ports pwm_m1_cl_o] [get_bd_pins controller_m1/pwm_cl_o]
|
||||
connect_bd_net -net axi_mc_controller_m1_pwm_ch_o [get_bd_ports pwm_m1_ch_o] [get_bd_pins controller_m1/pwm_ch_o]
|
||||
|
||||
connect_bd_net -net axi_mc_controller_m1_sensors_o [get_bd_pins controller_m1/sensors_o] [get_bd_pins speed_detector_m1/hall_bemf_i]
|
||||
connect_bd_net -net axi_mc_speed_1_position_o [get_bd_pins controller_m1/position_i] [get_bd_pins speed_detector_m1/position_o]
|
||||
connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins controller_m1/ctrl_data_valid_i] [get_bd_pins current_monitor_m1/i_ready_o]
|
||||
|
||||
#connect_bd_net -net controller_m1_adc_clk_o [get_bd_pins controller_m1_pack/adc_clk] [get_bd_pins controller_m1/adc_clk_o]
|
||||
#connect_bd_net -net [get_bd_nets sys_rstgen_peripheral_reset] [get_bd_pins controller_m1_pack/adc_rst] [get_bd_pins sys_rstgen/peripheral_reset]
|
||||
|
||||
#connect_bd_net -net controller_m1_adc_enable_c0 [get_bd_pins controller_m1/adc_enable_c0] [get_bd_pins controller_m1_pack/adc_enable_0]
|
||||
#connect_bd_net -net controller_m1_adc_enable_c1 [get_bd_pins controller_m1/adc_enable_c1] [get_bd_pins controller_m1_pack/adc_enable_1]
|
||||
#connect_bd_net -net controller_m1_adc_enable_c2 [get_bd_pins controller_m1/adc_enable_c2] [get_bd_pins controller_m1_pack/adc_enable_2]
|
||||
#connect_bd_net -net controller_m1_adc_enable_c3 [get_bd_pins controller_m1/adc_enable_c3] [get_bd_pins controller_m1_pack/adc_enable_3]
|
||||
#connect_bd_net -net controller_m1_adc_enable_c4 [get_bd_pins controller_m1/adc_enable_c4] [get_bd_pins controller_m1_pack/adc_enable_4]
|
||||
#connect_bd_net -net controller_m1_adc_enable_c5 [get_bd_pins controller_m1/adc_enable_c5] [get_bd_pins controller_m1_pack/adc_enable_5]
|
||||
#connect_bd_net -net controller_m1_adc_enable_c6 [get_bd_pins controller_m1/adc_enable_c6] [get_bd_pins controller_m1_pack/adc_enable_6]
|
||||
#connect_bd_net -net controller_m1_adc_enable_c7 [get_bd_pins controller_m1/adc_enable_c7] [get_bd_pins controller_m1_pack/adc_enable_7]
|
||||
|
||||
#connect_bd_net -net controller_m1_adc_valid_c0 [get_bd_pins controller_m1/adc_valid_c0] [get_bd_pins controller_m1_pack/adc_valid_0]
|
||||
#connect_bd_net -net controller_m1_adc_valid_c1 [get_bd_pins controller_m1/adc_valid_c1] [get_bd_pins controller_m1_pack/adc_valid_1]
|
||||
#connect_bd_net -net controller_m1_adc_valid_c2 [get_bd_pins controller_m1/adc_valid_c2] [get_bd_pins controller_m1_pack/adc_valid_2]
|
||||
#connect_bd_net -net controller_m1_adc_valid_c3 [get_bd_pins controller_m1/adc_valid_c3] [get_bd_pins controller_m1_pack/adc_valid_3]
|
||||
#connect_bd_net -net controller_m1_adc_valid_c4 [get_bd_pins controller_m1/adc_valid_c4] [get_bd_pins controller_m1_pack/adc_valid_4]
|
||||
#connect_bd_net -net controller_m1_adc_valid_c5 [get_bd_pins controller_m1/adc_valid_c5] [get_bd_pins controller_m1_pack/adc_valid_5]
|
||||
#connect_bd_net -net controller_m1_adc_valid_c6 [get_bd_pins controller_m1/adc_valid_c6] [get_bd_pins controller_m1_pack/adc_valid_6]
|
||||
#connect_bd_net -net controller_m1_adc_valid_c7 [get_bd_pins controller_m1/adc_valid_c7] [get_bd_pins controller_m1_pack/adc_valid_7]
|
||||
|
||||
#connect_bd_net -net controller_m1_data_c0 [get_bd_pins controller_m1/adc_data_c0] [get_bd_pins controller_m1_pack/adc_data_0]
|
||||
#connect_bd_net -net controller_m1_data_c1 [get_bd_pins controller_m1/adc_data_c1] [get_bd_pins controller_m1_pack/adc_data_1]
|
||||
#connect_bd_net -net controller_m1_data_c2 [get_bd_pins controller_m1/adc_data_c2] [get_bd_pins controller_m1_pack/adc_data_2]
|
||||
#connect_bd_net -net controller_m1_data_c3 [get_bd_pins controller_m1/adc_data_c3] [get_bd_pins controller_m1_pack/adc_data_3]
|
||||
#connect_bd_net -net controller_m1_data_c4 [get_bd_pins controller_m1/adc_data_c4] [get_bd_pins controller_m1_pack/adc_data_4]
|
||||
#connect_bd_net -net controller_m1_data_c5 [get_bd_pins controller_m1/adc_data_c5] [get_bd_pins controller_m1_pack/adc_data_5]
|
||||
#connect_bd_net -net controller_m1_data_c6 [get_bd_pins controller_m1/adc_data_c6] [get_bd_pins controller_m1_pack/adc_data_6]
|
||||
#connect_bd_net -net controller_m1_data_c7 [get_bd_pins controller_m1/adc_data_c7] [get_bd_pins controller_m1_pack/adc_data_7]
|
||||
|
||||
#connect_bd_net [get_bd_pins controller_m1_pack/adc_data] [get_bd_pins controller_m1_dma/fifo_wr_din]
|
||||
#connect_bd_net [get_bd_pins controller_m1_pack/adc_valid] [get_bd_pins controller_m1_dma/fifo_wr_en]
|
||||
|
||||
connect_bd_net -net [get_bd_nets sys_100m_clk] [get_bd_pins controller_m1_apack/clk] [get_bd_pins sys_ps7/FCLK_CLK0]
|
||||
|
||||
connect_bd_net -net controller_m1_adc_enable_c0 [get_bd_pins controller_m1/adc_enable_c0] [get_bd_pins controller_m1_apack/chan_enable_0]
|
||||
connect_bd_net -net controller_m1_adc_enable_c1 [get_bd_pins controller_m1/adc_enable_c1] [get_bd_pins controller_m1_apack/chan_enable_1]
|
||||
connect_bd_net -net controller_m1_adc_enable_c2 [get_bd_pins controller_m1/adc_enable_c2] [get_bd_pins controller_m1_apack/chan_enable_2]
|
||||
connect_bd_net -net controller_m1_adc_enable_c3 [get_bd_pins controller_m1/adc_enable_c3] [get_bd_pins controller_m1_apack/chan_enable_3]
|
||||
connect_bd_net -net controller_m1_adc_enable_c4 [get_bd_pins controller_m1/adc_enable_c4] [get_bd_pins controller_m1_apack/chan_enable_4]
|
||||
connect_bd_net -net controller_m1_adc_enable_c5 [get_bd_pins controller_m1/adc_enable_c5] [get_bd_pins controller_m1_apack/chan_enable_5]
|
||||
connect_bd_net -net controller_m1_adc_enable_c6 [get_bd_pins controller_m1/adc_enable_c6] [get_bd_pins controller_m1_apack/chan_enable_6]
|
||||
connect_bd_net -net controller_m1_adc_enable_c7 [get_bd_pins controller_m1/adc_enable_c7] [get_bd_pins controller_m1_apack/chan_enable_7]
|
||||
|
||||
connect_bd_net -net controller_m1_adc_valid_c0 [get_bd_pins controller_m1/adc_valid_c0] [get_bd_pins controller_m1_apack/chan_valid_0]
|
||||
connect_bd_net -net controller_m1_adc_valid_c1 [get_bd_pins controller_m1/adc_valid_c1] [get_bd_pins controller_m1_apack/chan_valid_1]
|
||||
connect_bd_net -net controller_m1_adc_valid_c2 [get_bd_pins controller_m1/adc_valid_c2] [get_bd_pins controller_m1_apack/chan_valid_2]
|
||||
connect_bd_net -net controller_m1_adc_valid_c3 [get_bd_pins controller_m1/adc_valid_c3] [get_bd_pins controller_m1_apack/chan_valid_3]
|
||||
connect_bd_net -net controller_m1_adc_valid_c4 [get_bd_pins controller_m1/adc_valid_c4] [get_bd_pins controller_m1_apack/chan_valid_4]
|
||||
connect_bd_net -net controller_m1_adc_valid_c5 [get_bd_pins controller_m1/adc_valid_c5] [get_bd_pins controller_m1_apack/chan_valid_5]
|
||||
connect_bd_net -net controller_m1_adc_valid_c6 [get_bd_pins controller_m1/adc_valid_c6] [get_bd_pins controller_m1_apack/chan_valid_6]
|
||||
connect_bd_net -net controller_m1_adc_valid_c7 [get_bd_pins controller_m1/adc_valid_c7] [get_bd_pins controller_m1_apack/chan_valid_7]
|
||||
|
||||
connect_bd_net -net controller_m1_data_c0 [get_bd_pins controller_m1/adc_data_c0] [get_bd_pins controller_m1_apack/chan_data_0]
|
||||
connect_bd_net -net controller_m1_data_c1 [get_bd_pins controller_m1/adc_data_c1] [get_bd_pins controller_m1_apack/chan_data_1]
|
||||
connect_bd_net -net controller_m1_data_c2 [get_bd_pins controller_m1/adc_data_c2] [get_bd_pins controller_m1_apack/chan_data_2]
|
||||
connect_bd_net -net controller_m1_data_c3 [get_bd_pins controller_m1/adc_data_c3] [get_bd_pins controller_m1_apack/chan_data_3]
|
||||
connect_bd_net -net controller_m1_data_c4 [get_bd_pins controller_m1/adc_data_c4] [get_bd_pins controller_m1_apack/chan_data_4]
|
||||
connect_bd_net -net controller_m1_data_c5 [get_bd_pins controller_m1/adc_data_c5] [get_bd_pins controller_m1_apack/chan_data_5]
|
||||
connect_bd_net -net controller_m1_data_c6 [get_bd_pins controller_m1/adc_data_c6] [get_bd_pins controller_m1_apack/chan_data_6]
|
||||
connect_bd_net -net controller_m1_data_c7 [get_bd_pins controller_m1/adc_data_c7] [get_bd_pins controller_m1_apack/chan_data_7]
|
||||
|
||||
connect_bd_net [get_bd_pins controller_m1_apack/ddata] [get_bd_pins controller_m1_dma/fifo_wr_din]
|
||||
connect_bd_net [get_bd_pins controller_m1_apack/dvalid] [get_bd_pins controller_m1_dma/fifo_wr_en]
|
||||
|
||||
# motor 2
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins controller_m2/s_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins controller_m2/ref_clk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins controller_m2/ctrl_data_clk] [get_bd_pins sys_audio_clkgen/clk_out4]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins controller_m2/s_axi_aresetn] $sys_100m_resetn_source
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins controller_m2_dma/s_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins controller_m2_dma/m_dest_axi_aclk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins controller_m2_dma/fifo_wr_clk] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins controller_m2_dma/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins controller_m2_dma/m_dest_axi_aresetn]
|
||||
|
||||
connect_bd_net -net axi_mc_controller_m2_fmc_m1_en_o [get_bd_ports fmc_m2_en_o] [get_bd_pins controller_m2/fmc_m1_en_o]
|
||||
connect_bd_net -net axi_mc_controller_m2_pwm_al_o [get_bd_ports pwm_m2_al_o] [get_bd_pins controller_m2/pwm_al_o]
|
||||
connect_bd_net -net axi_mc_controller_m2_pwm_ah_o [get_bd_ports pwm_m2_ah_o] [get_bd_pins controller_m2/pwm_ah_o]
|
||||
connect_bd_net -net axi_mc_controller_m2_pwm_bl_o [get_bd_ports pwm_m2_bl_o] [get_bd_pins controller_m2/pwm_bl_o]
|
||||
connect_bd_net -net axi_mc_controller_m2_pwm_bh_o [get_bd_ports pwm_m2_bh_o] [get_bd_pins controller_m2/pwm_bh_o]
|
||||
connect_bd_net -net axi_mc_controller_m2_pwm_cl_o [get_bd_ports pwm_m2_cl_o] [get_bd_pins controller_m2/pwm_cl_o]
|
||||
connect_bd_net -net axi_mc_controller_m2_pwm_ch_o [get_bd_ports pwm_m2_ch_o] [get_bd_pins controller_m2/pwm_ch_o]
|
||||
|
||||
connect_bd_net -net axi_mc_controller_m2_sensors_o [get_bd_pins controller_m2/sensors_o] [get_bd_pins speed_detector_m2/hall_bemf_i]
|
||||
connect_bd_net -net axi_mc_speed_2_position_o [get_bd_pins controller_m2/position_i] [get_bd_pins speed_detector_m2/position_o]
|
||||
connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins controller_m2/ctrl_data_valid_i] [get_bd_pins current_monitor_m2/i_ready_o]
|
||||
|
||||
#connect_bd_net -net controller_m2_adc_clk_o [get_bd_pins controller_m2_pack/adc_clk] [get_bd_pins controller_m2/adc_clk_o]
|
||||
#connect_bd_net -net [get_bd_nets sys_rstgen_peripheral_reset] [get_bd_pins controller_m2_pack/adc_rst] [get_bd_pins sys_rstgen/peripheral_reset]
|
||||
|
||||
#connect_bd_net -net controller_m2_adc_enable_c0 [get_bd_pins controller_m2/adc_enable_c0] [get_bd_pins controller_m2_pack/adc_enable_0]
|
||||
#connect_bd_net -net controller_m2_adc_enable_c1 [get_bd_pins controller_m2/adc_enable_c1] [get_bd_pins controller_m2_pack/adc_enable_1]
|
||||
#connect_bd_net -net controller_m2_adc_enable_c2 [get_bd_pins controller_m2/adc_enable_c2] [get_bd_pins controller_m2_pack/adc_enable_2]
|
||||
#connect_bd_net -net controller_m2_adc_enable_c3 [get_bd_pins controller_m2/adc_enable_c3] [get_bd_pins controller_m2_pack/adc_enable_3]
|
||||
#connect_bd_net -net controller_m2_adc_enable_c4 [get_bd_pins controller_m2/adc_enable_c4] [get_bd_pins controller_m2_pack/adc_enable_4]
|
||||
#connect_bd_net -net controller_m2_adc_enable_c5 [get_bd_pins controller_m2/adc_enable_c5] [get_bd_pins controller_m2_pack/adc_enable_5]
|
||||
#connect_bd_net -net controller_m2_adc_enable_c6 [get_bd_pins controller_m2/adc_enable_c6] [get_bd_pins controller_m2_pack/adc_enable_6]
|
||||
#connect_bd_net -net controller_m2_adc_enable_c7 [get_bd_pins controller_m2/adc_enable_c7] [get_bd_pins controller_m2_pack/adc_enable_7]
|
||||
|
||||
#connect_bd_net -net controller_m2_adc_valid_c0 [get_bd_pins controller_m2/adc_valid_c0] [get_bd_pins controller_m2_pack/adc_valid_0]
|
||||
#connect_bd_net -net controller_m2_adc_valid_c1 [get_bd_pins controller_m2/adc_valid_c1] [get_bd_pins controller_m2_pack/adc_valid_1]
|
||||
#connect_bd_net -net controller_m2_adc_valid_c2 [get_bd_pins controller_m2/adc_valid_c2] [get_bd_pins controller_m2_pack/adc_valid_2]
|
||||
#connect_bd_net -net controller_m2_adc_valid_c3 [get_bd_pins controller_m2/adc_valid_c3] [get_bd_pins controller_m2_pack/adc_valid_3]
|
||||
#connect_bd_net -net controller_m2_adc_valid_c4 [get_bd_pins controller_m2/adc_valid_c4] [get_bd_pins controller_m2_pack/adc_valid_4]
|
||||
#connect_bd_net -net controller_m2_adc_valid_c5 [get_bd_pins controller_m2/adc_valid_c5] [get_bd_pins controller_m2_pack/adc_valid_5]
|
||||
#connect_bd_net -net controller_m2_adc_valid_c6 [get_bd_pins controller_m2/adc_valid_c6] [get_bd_pins controller_m2_pack/adc_valid_6]
|
||||
#connect_bd_net -net controller_m2_adc_valid_c7 [get_bd_pins controller_m2/adc_valid_c7] [get_bd_pins controller_m2_pack/adc_valid_7]
|
||||
|
||||
#connect_bd_net -net controller_m2_data_c0 [get_bd_pins controller_m2/adc_data_c0] [get_bd_pins controller_m2_pack/adc_data_0]
|
||||
#connect_bd_net -net controller_m2_data_c1 [get_bd_pins controller_m2/adc_data_c1] [get_bd_pins controller_m2_pack/adc_data_1]
|
||||
#connect_bd_net -net controller_m2_data_c2 [get_bd_pins controller_m2/adc_data_c2] [get_bd_pins controller_m2_pack/adc_data_2]
|
||||
#connect_bd_net -net controller_m2_data_c3 [get_bd_pins controller_m2/adc_data_c3] [get_bd_pins controller_m2_pack/adc_data_3]
|
||||
#connect_bd_net -net controller_m2_data_c4 [get_bd_pins controller_m2/adc_data_c4] [get_bd_pins controller_m2_pack/adc_data_4]
|
||||
#connect_bd_net -net controller_m2_data_c5 [get_bd_pins controller_m2/adc_data_c5] [get_bd_pins controller_m2_pack/adc_data_5]
|
||||
#connect_bd_net -net controller_m2_data_c6 [get_bd_pins controller_m2/adc_data_c6] [get_bd_pins controller_m2_pack/adc_data_6]
|
||||
#connect_bd_net -net controller_m2_data_c7 [get_bd_pins controller_m2/adc_data_c7] [get_bd_pins controller_m2_pack/adc_data_7]
|
||||
|
||||
#connect_bd_net [get_bd_pins controller_m2_pack/adc_data] [get_bd_pins controller_m2_dma/fifo_wr_din]
|
||||
#connect_bd_net [get_bd_pins controller_m2_pack/adc_valid] [get_bd_pins controller_m2_dma/fifo_wr_en]
|
||||
|
||||
connect_bd_net -net [get_bd_nets sys_100m_clk] [get_bd_pins controller_m2_apack/clk] [get_bd_pins sys_ps7/FCLK_CLK0]
|
||||
|
||||
connect_bd_net -net controller_m2_adc_enable_c0 [get_bd_pins controller_m2/adc_enable_c0] [get_bd_pins controller_m2_apack/chan_enable_0]
|
||||
connect_bd_net -net controller_m2_adc_enable_c1 [get_bd_pins controller_m2/adc_enable_c1] [get_bd_pins controller_m2_apack/chan_enable_1]
|
||||
connect_bd_net -net controller_m2_adc_enable_c2 [get_bd_pins controller_m2/adc_enable_c2] [get_bd_pins controller_m2_apack/chan_enable_2]
|
||||
connect_bd_net -net controller_m2_adc_enable_c3 [get_bd_pins controller_m2/adc_enable_c3] [get_bd_pins controller_m2_apack/chan_enable_3]
|
||||
connect_bd_net -net controller_m2_adc_enable_c4 [get_bd_pins controller_m2/adc_enable_c4] [get_bd_pins controller_m2_apack/chan_enable_4]
|
||||
connect_bd_net -net controller_m2_adc_enable_c5 [get_bd_pins controller_m2/adc_enable_c5] [get_bd_pins controller_m2_apack/chan_enable_5]
|
||||
connect_bd_net -net controller_m2_adc_enable_c6 [get_bd_pins controller_m2/adc_enable_c6] [get_bd_pins controller_m2_apack/chan_enable_6]
|
||||
connect_bd_net -net controller_m2_adc_enable_c7 [get_bd_pins controller_m2/adc_enable_c7] [get_bd_pins controller_m2_apack/chan_enable_7]
|
||||
|
||||
connect_bd_net -net controller_m2_adc_valid_c0 [get_bd_pins controller_m2/adc_valid_c0] [get_bd_pins controller_m2_apack/chan_valid_0]
|
||||
connect_bd_net -net controller_m2_adc_valid_c1 [get_bd_pins controller_m2/adc_valid_c1] [get_bd_pins controller_m2_apack/chan_valid_1]
|
||||
connect_bd_net -net controller_m2_adc_valid_c2 [get_bd_pins controller_m2/adc_valid_c2] [get_bd_pins controller_m2_apack/chan_valid_2]
|
||||
connect_bd_net -net controller_m2_adc_valid_c3 [get_bd_pins controller_m2/adc_valid_c3] [get_bd_pins controller_m2_apack/chan_valid_3]
|
||||
connect_bd_net -net controller_m2_adc_valid_c4 [get_bd_pins controller_m2/adc_valid_c4] [get_bd_pins controller_m2_apack/chan_valid_4]
|
||||
connect_bd_net -net controller_m2_adc_valid_c5 [get_bd_pins controller_m2/adc_valid_c5] [get_bd_pins controller_m2_apack/chan_valid_5]
|
||||
connect_bd_net -net controller_m2_adc_valid_c6 [get_bd_pins controller_m2/adc_valid_c6] [get_bd_pins controller_m2_apack/chan_valid_6]
|
||||
connect_bd_net -net controller_m2_adc_valid_c7 [get_bd_pins controller_m2/adc_valid_c7] [get_bd_pins controller_m2_apack/chan_valid_7]
|
||||
|
||||
connect_bd_net -net controller_m2_data_c0 [get_bd_pins controller_m2/adc_data_c0] [get_bd_pins controller_m2_apack/chan_data_0]
|
||||
connect_bd_net -net controller_m2_data_c1 [get_bd_pins controller_m2/adc_data_c1] [get_bd_pins controller_m2_apack/chan_data_1]
|
||||
connect_bd_net -net controller_m2_data_c2 [get_bd_pins controller_m2/adc_data_c2] [get_bd_pins controller_m2_apack/chan_data_2]
|
||||
connect_bd_net -net controller_m2_data_c3 [get_bd_pins controller_m2/adc_data_c3] [get_bd_pins controller_m2_apack/chan_data_3]
|
||||
connect_bd_net -net controller_m2_data_c4 [get_bd_pins controller_m2/adc_data_c4] [get_bd_pins controller_m2_apack/chan_data_4]
|
||||
connect_bd_net -net controller_m2_data_c5 [get_bd_pins controller_m2/adc_data_c5] [get_bd_pins controller_m2_apack/chan_data_5]
|
||||
connect_bd_net -net controller_m2_data_c6 [get_bd_pins controller_m2/adc_data_c6] [get_bd_pins controller_m2_apack/chan_data_6]
|
||||
connect_bd_net -net controller_m2_data_c7 [get_bd_pins controller_m2/adc_data_c7] [get_bd_pins controller_m2_apack/chan_data_7]
|
||||
|
||||
connect_bd_net [get_bd_pins controller_m2_apack/ddata] [get_bd_pins controller_m2_dma/fifo_wr_din]
|
||||
connect_bd_net [get_bd_pins controller_m2_apack/dvalid] [get_bd_pins controller_m2_dma/fifo_wr_en]
|
||||
# interrupts
|
||||
connect_bd_net -net controller_m1_dma_intr [get_bd_pins controller_m1_dma/irq] [get_bd_ports motcon2_ctrl_m1_intr]
|
||||
connect_bd_net -net controller_m2_dma_intr [get_bd_pins controller_m2_dma/irq] [get_bd_ports motcon2_ctrl_m2_intr]
|
||||
|
||||
# ethernet
|
||||
|
||||
|
||||
connect_bd_net -net sys_200m_clk [get_bd_ports refclk] [get_bd_pins sys_ps7/FCLK_CLK1]
|
||||
connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_ports refclk_rst] [get_bd_pins sys_rstgen/peripheral_reset]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_ports eth_phy_rst_n]
|
||||
connect_bd_net [get_bd_pins /sys_ps7/ENET0_MDIO_MDC] [get_bd_ports eth_mdio_mdc]
|
||||
connect_bd_net [get_bd_pins /sys_ps7/ENET0_MDIO_O] [get_bd_ports eth_mdio_o]
|
||||
connect_bd_net [get_bd_pins /sys_ps7/ENET0_MDIO_T] [get_bd_ports eth_mdio_t]
|
||||
connect_bd_net [get_bd_pins /sys_ps7/ENET0_MDIO_I] [get_bd_ports eth_mdio_i]
|
||||
# phy 1
|
||||
connect_bd_intf_net -intf_net sys_ps7_GMII_ETHERNET_1 [get_bd_intf_pins gmii_to_rgmii_eth1/gmii] [get_bd_intf_pins sys_ps7/GMII_ETHERNET_0]
|
||||
connect_bd_intf_net -intf_net gmii_to_rgmii_eth1_rgmii [get_bd_intf_ports eth1_rgmii] [get_bd_intf_pins gmii_to_rgmii_eth1/rgmii]
|
||||
connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_pins gmii_to_rgmii_eth1/reset] [get_bd_pins sys_rstgen/peripheral_reset]
|
||||
|
||||
connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth1/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4]
|
||||
connect_bd_net -net sys_audio_clkgen_clk_out3 [get_bd_pins gmii_to_rgmii_eth1/clk_25m] [get_bd_pins sys_audio_clkgen/clk_out3]
|
||||
connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth1/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2]
|
||||
connect_bd_net [get_bd_ports eth_mdio_mdc] [get_bd_pins gmii_to_rgmii_eth1/mdio_mdc]
|
||||
connect_bd_net [get_bd_ports eth_mdio_o] [get_bd_pins gmii_to_rgmii_eth1/mdio_in_w]
|
||||
connect_bd_net [get_bd_ports eth_mdio_i] [get_bd_pins gmii_to_rgmii_eth1/mdio_in_r]
|
||||
# phy 2
|
||||
connect_bd_intf_net -intf_net sys_ps7_GMII_ETHERNET_2 [get_bd_intf_pins gmii_to_rgmii_eth2/gmii] [get_bd_intf_pins sys_ps7/GMII_ETHERNET_1]
|
||||
connect_bd_intf_net -intf_net gmii_to_rgmii_eth2_rgmii [get_bd_intf_ports eth2_rgmii] [get_bd_intf_pins gmii_to_rgmii_eth2/rgmii]
|
||||
connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_pins gmii_to_rgmii_eth2/reset] [get_bd_pins sys_rstgen/peripheral_reset]
|
||||
connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth2/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4]
|
||||
connect_bd_net -net sys_audio_clkgen_clk_out3 [get_bd_pins gmii_to_rgmii_eth2/clk_25m] [get_bd_pins sys_audio_clkgen/clk_out3]
|
||||
connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth2/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2]
|
||||
|
||||
connect_bd_net [get_bd_ports eth_mdio_mdc] [get_bd_pins gmii_to_rgmii_eth2/mdio_mdc]
|
||||
connect_bd_net [get_bd_ports eth_mdio_o] [get_bd_pins gmii_to_rgmii_eth2/mdio_in_w]
|
||||
connect_bd_net [get_bd_ports eth_mdio_i] [get_bd_pins gmii_to_rgmii_eth2/mdio_in_r]
|
||||
|
||||
# xadc
|
||||
#connect_bd_net -net sys_100m_clk [get_bd_pins xadc_core/s_axi_aclk] $sys_100m_clk_source
|
||||
#connect_bd_net -net sys_100m_resetn [get_bd_pins xadc_core/s_axi_aresetn] $sys_100m_resetn_source
|
||||
#connect_bd_intf_net -intf_net Vaux0_1 [get_bd_intf_pins xadc_core/Vaux0] [get_bd_intf_ports Vaux0]
|
||||
#connect_bd_intf_net -intf_net Vaux8_1 [get_bd_intf_pins xadc_core/Vaux8] [get_bd_intf_ports Vaux8]
|
||||
#connect_bd_net -net xadc_muxout [get_bd_pins /xadc_core/muxaddr_out] [get_bd_ports muxaddr_out]
|
||||
|
||||
# iic
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins iic_ee2/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins iic_ee2/s_axi_aresetn]
|
||||
connect_bd_intf_net [get_bd_intf_pins iic_ee2/IIC] [get_bd_intf_ports iic_ee2]
|
||||
connect_bd_net -net iic_ee2_irq [get_bd_pins iic_ee2/iic2intc_irpt] [get_bd_ports iic_ee2_intr]
|
||||
|
||||
# spi
|
||||
connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I]
|
||||
connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins sys_ps7/SPI0_SS_O]
|
||||
connect_bd_net -net spi_sclk_i [get_bd_ports spi_sclk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I]
|
||||
connect_bd_net -net spi_sclk_o [get_bd_ports spi_sclk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O]
|
||||
connect_bd_net -net spi_mosi_i [get_bd_ports spi_mosi_i] [get_bd_pins sys_ps7/SPI0_MOSI_I]
|
||||
connect_bd_net -net spi_mosi_o [get_bd_ports spi_mosi_o] [get_bd_pins sys_ps7/SPI0_MOSI_O]
|
||||
connect_bd_net -net spi_miso_i [get_bd_ports spi_miso_i] [get_bd_pins sys_ps7/SPI0_MISO_I]
|
||||
|
||||
# cpu interconnect
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M15_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M16_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M17_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M18_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M19_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M20_ACLK] $sys_100m_clk_source
|
||||
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M15_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M16_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M17_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M18_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M19_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M20_ARESETN] $sys_100m_resetn_source
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins iic_ee2/S_AXI] -boundary_type upper [get_bd_intf_pins axi_cpu_interconnect/M07_AXI]
|
||||
# connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins xadc_core/s_axi_lite]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins speed_detector_m1/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins speed_detector_m1_dma/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins speed_detector_m2/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins speed_detector_m2_dma/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins current_monitor_m1/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins current_monitor_m1_dma/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m15_axi [get_bd_intf_pins axi_cpu_interconnect/M15_AXI] [get_bd_intf_pins current_monitor_m2/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m16_axi [get_bd_intf_pins axi_cpu_interconnect/M16_AXI] [get_bd_intf_pins current_monitor_m2_dma/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m17_axi [get_bd_intf_pins axi_cpu_interconnect/M17_AXI] [get_bd_intf_pins controller_m1/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m18_axi [get_bd_intf_pins axi_cpu_interconnect/M18_AXI] [get_bd_intf_pins controller_m1_dma/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m19_axi [get_bd_intf_pins axi_cpu_interconnect/M19_AXI] [get_bd_intf_pins controller_m2/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m20_axi [get_bd_intf_pins axi_cpu_interconnect/M20_AXI] [get_bd_intf_pins controller_m2_dma/s_axi]
|
||||
|
||||
# mem interconnect
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/M00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S01_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S02_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S03_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S04_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S05_ACLK] $sys_100m_clk_source
|
||||
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/M00_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S00_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S01_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S02_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S03_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S04_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S05_ARESETN] $sys_100m_resetn_source
|
||||
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_m00_axi [get_bd_intf_pins axi_mem_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1]
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s00_axi [get_bd_intf_pins axi_mem_interconnect/S00_AXI] [get_bd_intf_pins speed_detector_m1_dma/m_dest_axi]
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s01_axi [get_bd_intf_pins axi_mem_interconnect/S01_AXI] [get_bd_intf_pins speed_detector_m2_dma/m_dest_axi]
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s02_axi [get_bd_intf_pins axi_mem_interconnect/S02_AXI] [get_bd_intf_pins current_monitor_m1_dma/m_dest_axi]
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s03_axi [get_bd_intf_pins axi_mem_interconnect/S03_AXI] [get_bd_intf_pins current_monitor_m2_dma/m_dest_axi]
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s04_axi [get_bd_intf_pins axi_mem_interconnect/S04_AXI] [get_bd_intf_pins controller_m1_dma/m_dest_axi]
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s05_axi [get_bd_intf_pins axi_mem_interconnect/S05_AXI] [get_bd_intf_pins controller_m2_dma/m_dest_axi]
|
||||
|
||||
# address map
|
||||
create_bd_addr_seg -range 0x10000 -offset 0x40410000 $sys_addr_cntrl_space [get_bd_addr_segs speed_detector_m1/s_axi/axi_lite] SEG_data_s_d1
|
||||
create_bd_addr_seg -range 0x10000 -offset 0x40420000 $sys_addr_cntrl_space [get_bd_addr_segs current_monitor_m1/s_axi/axi_lite] SEG_data_c_m1
|
||||
create_bd_addr_seg -range 0x10000 -offset 0x40430000 $sys_addr_cntrl_space [get_bd_addr_segs controller_m1/s_axi/axi_lite] SEG_data_c1
|
||||
create_bd_addr_seg -range 0x10000 -offset 0x40440000 $sys_addr_cntrl_space [get_bd_addr_segs speed_detector_m2/s_axi/axi_lite] SEG_data_s_d2
|
||||
create_bd_addr_seg -range 0x10000 -offset 0x40450000 $sys_addr_cntrl_space [get_bd_addr_segs current_monitor_m2/s_axi/axi_lite] SEG_data_c_m2
|
||||
create_bd_addr_seg -range 0x10000 -offset 0x40460000 $sys_addr_cntrl_space [get_bd_addr_segs controller_m2/s_axi/axi_lite] SEG_data_c2
|
||||
create_bd_addr_seg -range 0x10000 -offset 0x40510000 $sys_addr_cntrl_space [get_bd_addr_segs speed_detector_m1_dma/s_axi/axi_lite] SEG_data_s_d1_dma
|
||||
create_bd_addr_seg -range 0x10000 -offset 0x40520000 $sys_addr_cntrl_space [get_bd_addr_segs current_monitor_m1_dma/s_axi/axi_lite] SEG_data_c_m1_dma
|
||||
create_bd_addr_seg -range 0x10000 -offset 0x40530000 $sys_addr_cntrl_space [get_bd_addr_segs controller_m1_dma/s_axi/axi_lite] SEG_data_c1_dma
|
||||
create_bd_addr_seg -range 0x10000 -offset 0x40540000 $sys_addr_cntrl_space [get_bd_addr_segs speed_detector_m2_dma/s_axi/axi_lite] SEG_data_s_d2_dma
|
||||
create_bd_addr_seg -range 0x10000 -offset 0x40550000 $sys_addr_cntrl_space [get_bd_addr_segs current_monitor_m2_dma/s_axi/axi_lite] SEG_data_c_m2_dma
|
||||
create_bd_addr_seg -range 0x10000 -offset 0x40560000 $sys_addr_cntrl_space [get_bd_addr_segs controller_m2_dma/s_axi/axi_lite] SEG_data_c2_dma
|
||||
# create_bd_addr_seg -range 0x10000 -offset 0x43200000 $sys_addr_cntrl_space [get_bd_addr_segs xadc_core/s_axi_lite/Reg] SEG_data_xadc
|
||||
create_bd_addr_seg -range 0x10000 -offset 0x41510000 $sys_addr_cntrl_space [get_bd_addr_segs iic_ee2/S_AXI/Reg] SEG_iic_ee2_Reg
|
||||
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x0 [get_bd_addr_spaces speed_detector_m1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x0 [get_bd_addr_spaces speed_detector_m2_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x0 [get_bd_addr_spaces current_monitor_m1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x0 [get_bd_addr_spaces current_monitor_m2_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x0 [get_bd_addr_spaces controller_m1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x0 [get_bd_addr_spaces controller_m2_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
|
||||
|
|
@ -1,5 +1,4 @@
|
|||
|
||||
|
||||
source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
|
||||
source ../common/motcon1_fmc_bd.tcl
|
||||
source ../common/motcon2_fmc_bd.tcl
|
||||
|
||||
|
|
@ -0,0 +1,198 @@
|
|||
|
||||
#DEBUG
|
||||
|
||||
# Motor Control
|
||||
#set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports gpio_bd[27]] ; ## XADC-GIO0
|
||||
#set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[28]] ; ## XADC-GIO1
|
||||
#set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[29]] ; ## XADC-GIO2
|
||||
#set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS33} [get_ports gpio_bd[30]] ; ## XADC-GIO3
|
||||
|
||||
set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS25 } [get_ports {position_m1_i[0]}]
|
||||
set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS25 } [get_ports {position_m1_i[1]}]
|
||||
set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS25 } [get_ports {position_m1_i[2]}]
|
||||
|
||||
set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS25} [get_ports {position_m2_i[0]}] ; #M2_SENSOR_A
|
||||
set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS25} [get_ports {position_m2_i[1]}] ; #M2_SENSOR_B
|
||||
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS25} [get_ports {position_m2_i[2]}] ; #M2_SENSOR_C
|
||||
|
||||
set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS25} [get_ports vt_enable]
|
||||
|
||||
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports fmc_m1_en_o]
|
||||
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports pwm_m1_ah_o]
|
||||
set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS25} [get_ports pwm_m1_al_o]
|
||||
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports pwm_m1_bh_o]
|
||||
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports pwm_m1_bl_o]
|
||||
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports pwm_m1_ch_o]
|
||||
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports pwm_m1_cl_o]
|
||||
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports pwm_m1_dh_o]
|
||||
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports pwm_m1_dl_o]
|
||||
|
||||
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports fmc_m2_en_o]
|
||||
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS25} [get_ports pwm_m2_ah_o]
|
||||
set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS25} [get_ports pwm_m2_al_o]
|
||||
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS25} [get_ports pwm_m2_bh_o]
|
||||
set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS25} [get_ports pwm_m2_bl_o]
|
||||
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports pwm_m2_ch_o]
|
||||
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports pwm_m2_cl_o]
|
||||
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25} [get_ports pwm_m2_dh_o]
|
||||
set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS25} [get_ports pwm_m2_dl_o]
|
||||
set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25 } [get_ports adc_clk_o]
|
||||
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25 } [get_ports adc_m1_vbus_dat_i]
|
||||
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25 } [get_ports adc_m2_vbus_dat_i]
|
||||
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25 } [get_ports adc_m1_ia_dat_i]
|
||||
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25 } [get_ports adc_m1_ib_dat_i]
|
||||
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS25 } [get_ports adc_m2_ia_dat_i]
|
||||
set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS25 } [get_ports adc_m2_ib_dat_i]
|
||||
|
||||
# GPO
|
||||
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25 } [get_ports {gpo[0]}]
|
||||
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS25 } [get_ports {gpo[1]}]
|
||||
set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS25 } [get_ports {gpo[2]}]
|
||||
set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS25 } [get_ports {gpo[3]}]
|
||||
|
||||
# GPI
|
||||
set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS25} [get_ports {gpi[0]}]
|
||||
set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS25} [get_ports {gpi[1]}]
|
||||
|
||||
|
||||
#set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[0]}]
|
||||
#set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[1]}]
|
||||
#set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[2]}]
|
||||
#set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[3]}]
|
||||
|
||||
#set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS25} [get_ports vauxn0]
|
||||
#set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS25} [get_ports vauxn8]
|
||||
#set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS25} [get_ports vauxp0]
|
||||
#set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS25} [get_ports vauxp8]
|
||||
|
||||
# SPI
|
||||
set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS25} [get_ports fmc_spi1_sel1_rdc ]
|
||||
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports fmc_spi1_miso ]
|
||||
set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS25} [get_ports fmc_spi1_mosi ]
|
||||
set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS25} [get_ports fmc_spi1_sck ]
|
||||
|
||||
#FMC_SAMPLE_N
|
||||
set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS25} [get_ports fmc_sample_n]
|
||||
|
||||
# IIC
|
||||
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_ee2_scl_io]
|
||||
set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_ee2_sda_io]
|
||||
|
||||
# Ethernet common
|
||||
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25} [get_ports eth_mdio_mdc]
|
||||
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25 PULLUP true} [get_ports eth_mdio_io]
|
||||
set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS25} [get_ports eth_phy_rst_n]
|
||||
|
||||
# Ethernet 1
|
||||
set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_rxc]
|
||||
set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_rx_ctl]
|
||||
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[0]}]
|
||||
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[1]}]
|
||||
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[2]}]
|
||||
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[3]}]
|
||||
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_txc]
|
||||
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_tx_ctl]
|
||||
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[0]}]
|
||||
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[1]}]
|
||||
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[2]}]
|
||||
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[3]}]
|
||||
|
||||
# Ethernet 2
|
||||
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_rxc]
|
||||
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_rx_ctl]
|
||||
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[0]}]
|
||||
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[1]}]
|
||||
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[2]}]
|
||||
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[3]}]
|
||||
set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_txc]
|
||||
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_tx_ctl]
|
||||
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[0]}]
|
||||
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[1]}]
|
||||
set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[2]}]
|
||||
set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[3]}]
|
||||
|
||||
# Ethernet common
|
||||
|
||||
set_property IODELAY_GROUP eth_idelay_grp [get_cells dlyctrl]
|
||||
|
||||
set_false_path -from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -to [get_clocks clk_out3_system_sys_audio_clkgen_0_1]
|
||||
set_false_path -from [get_clocks clk_out3_system_sys_audio_clkgen_0_1] -to [get_clocks clk_out2_system_sys_audio_clkgen_0_1]
|
||||
set_false_path -from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -to [get_clocks clk_2_5m_2]
|
||||
set_false_path -from [get_clocks clk_out3_system_sys_audio_clkgen_0_1] -to [get_clocks clk_2_5m_2]
|
||||
set_false_path -from [get_clocks clk_2_5m_2] -to [get_clocks clk_out2_system_sys_audio_clkgen_0_1]
|
||||
set_false_path -from [get_clocks clk_2_5m_2] -to [get_clocks clk_out3_system_sys_audio_clkgen_0_1]
|
||||
set_false_path -from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -to [get_clocks clk_2_5m_3]
|
||||
set_false_path -from [get_clocks clk_out3_system_sys_audio_clkgen_0_1] -to [get_clocks clk_2_5m_3]
|
||||
set_false_path -from [get_clocks clk_2_5m_3] -to [get_clocks clk_out2_system_sys_audio_clkgen_0_1]
|
||||
set_false_path -from [get_clocks clk_2_5m_3] -to [get_clocks clk_out3_system_sys_audio_clkgen_0_1]
|
||||
|
||||
# Ethernet 1
|
||||
|
||||
# Clock Period Constraints
|
||||
create_clock -period 8.000 -name rgmii_rxc1 [get_ports eth1_rgmii_rxc]
|
||||
#set_clock_latency -source -early 0.5 [get_clocks rgmii_rxc1]
|
||||
#set_clock_latency -source -late 0.5 [get_clocks rgmii_rxc1]
|
||||
|
||||
create_clock -name eth1_rx_clk_vir -period 8
|
||||
|
||||
set_property IDELAY_VALUE 18 [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl]
|
||||
set_property IDELAY_VALUE 18 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth1*/*delay_rgmii_rd*}]
|
||||
set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl]
|
||||
set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth1*/*delay_rgmii_rd*}]
|
||||
|
||||
set_input_delay -clock [get_clocks eth1_rx_clk_vir] -max -1.2 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}]
|
||||
set_input_delay -clock [get_clocks eth1_rx_clk_vir] -min -2.8 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}]
|
||||
set_input_delay -clock [get_clocks eth1_rx_clk_vir] -clock_fall -max -1.2 -add_delay [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}]
|
||||
set_input_delay -clock [get_clocks eth1_rx_clk_vir] -clock_fall -min -2.8 -add_delay [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}]
|
||||
|
||||
set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -fall_to rgmii_rxc1 -setup
|
||||
set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -rise_to rgmii_rxc1 -setup
|
||||
set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -rise_to rgmii_rxc1 -hold
|
||||
set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -fall_to rgmii_rxc1 -hold
|
||||
|
||||
set_multicycle_path -from [get_clocks eth1_rx_clk_vir] -to rgmii_rxc1 -setup 0
|
||||
set_multicycle_path -from [get_clocks eth1_rx_clk_vir] -to rgmii_rxc1 -hold -1
|
||||
|
||||
set_output_delay -max -0.9 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth1_rgmii_td[*] eth1_rgmii_tx_ctl}]
|
||||
set_output_delay -min 2.7 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth1_rgmii_td[*] eth1_rgmii_tx_ctl}]
|
||||
set_output_delay -max -0.9 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth1_rgmii_td[*] eth1_rgmii_tx_ctl}] -clock_fall -add_delay
|
||||
set_output_delay -min 2.7 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth1_rgmii_td[*] eth1_rgmii_tx_ctl}] -clock_fall -add_delay
|
||||
|
||||
# Ethernet 2
|
||||
|
||||
# Clock Period Constraints
|
||||
create_clock -period 8.000 -name rgmii_rxc2 [get_ports eth2_rgmii_rxc]
|
||||
#set_clock_latency -source -early 0.5 [get_clocks rgmii_rxc1]
|
||||
#set_clock_latency -source -late 0.5 [get_clocks rgmii_rxc1]
|
||||
|
||||
create_clock -name eth2_rx_clk_vir -period 8
|
||||
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/gmii_to_rgmii_eth2/inst/clk_100msps]
|
||||
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_out3]
|
||||
|
||||
set_property IDELAY_VALUE 18 [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl]
|
||||
set_property IDELAY_VALUE 18 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth2*/*delay_rgmii_rd*}]
|
||||
set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl]
|
||||
set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth2*/*delay_rgmii_rd*}]
|
||||
|
||||
set_input_delay -clock [get_clocks eth2_rx_clk_vir] -max -1.2 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}]
|
||||
set_input_delay -clock [get_clocks eth2_rx_clk_vir] -min -2.8 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}]
|
||||
set_input_delay -clock [get_clocks eth2_rx_clk_vir] -clock_fall -max -1.2 -add_delay [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}]
|
||||
set_input_delay -clock [get_clocks eth2_rx_clk_vir] -clock_fall -min -2.8 -add_delay [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}]
|
||||
|
||||
set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -fall_to rgmii_rxc2 -setup
|
||||
set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -rise_to rgmii_rxc2 -setup
|
||||
set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -rise_to rgmii_rxc2 -hold
|
||||
set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -fall_to rgmii_rxc2 -hold
|
||||
|
||||
set_multicycle_path -from [get_clocks eth2_rx_clk_vir] -to rgmii_rxc2 -setup 0
|
||||
set_multicycle_path -from [get_clocks eth2_rx_clk_vir] -to rgmii_rxc2 -hold -1
|
||||
|
||||
set_false_path -rise_from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -fall_to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -setup
|
||||
set_false_path -fall_from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -rise_to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -setup
|
||||
set_false_path -rise_from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -rise_to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -hold
|
||||
set_false_path -fall_from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -fall_to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -hold
|
||||
|
||||
set_output_delay -max -0.9 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}]
|
||||
set_output_delay -min 2.7 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}]
|
||||
set_output_delay -max -0.9 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}] -clock_fall -add_delay
|
||||
set_output_delay -min 2.7 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}] -clock_fall -add_delay
|
||||
|
|
@ -2,13 +2,11 @@
|
|||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_project.tcl
|
||||
|
||||
adi_project_create motcon1_fmc_zed
|
||||
adi_project_files motcon1_fmc_zed [list \
|
||||
adi_project_create motcon2_fmc_zed
|
||||
adi_project_files motcon2_fmc_zed [list \
|
||||
"system_top.v" \
|
||||
"system_constr.xdc" \
|
||||
"$ad_hdl_dir/library/common/ad_iobuf.v" \
|
||||
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ]
|
||||
|
||||
adi_project_run motcon1_fmc_zed
|
||||
|
||||
|
||||
adi_project_run motcon2_fmc_zed
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014(c) Analog Devices, Inc.
|
||||
// Copyright 2015(c) Analog Devices, Inc.
|
||||
//
|
||||
// All rights reserved.
|
||||
//
|
||||
|
|
@ -57,6 +57,24 @@ module system_top (
|
|||
DDR_reset_n,
|
||||
DDR_we_n,
|
||||
|
||||
eth1_rgmii_rd,
|
||||
eth1_rgmii_rx_ctl,
|
||||
eth1_rgmii_rxc,
|
||||
eth1_rgmii_td,
|
||||
eth1_rgmii_tx_ctl,
|
||||
eth1_rgmii_txc,
|
||||
|
||||
eth2_rgmii_rd,
|
||||
eth2_rgmii_rx_ctl,
|
||||
eth2_rgmii_rxc,
|
||||
eth2_rgmii_td,
|
||||
eth2_rgmii_tx_ctl,
|
||||
eth2_rgmii_txc,
|
||||
|
||||
eth_mdio_io,
|
||||
eth_mdio_mdc,
|
||||
eth_phy_rst_n,
|
||||
|
||||
FIXED_IO_ddr_vrn,
|
||||
FIXED_IO_ddr_vrp,
|
||||
FIXED_IO_mio,
|
||||
|
|
@ -72,38 +90,39 @@ module system_top (
|
|||
hdmi_data_e,
|
||||
hdmi_data,
|
||||
|
||||
adc_ia_clk_d_o,
|
||||
adc_ia_clk_o,
|
||||
adc_ia_dat_d_i,
|
||||
adc_ia_dat_i,
|
||||
adc_ib_clk_d_o,
|
||||
adc_ib_clk_o,
|
||||
adc_ib_dat_d_i,
|
||||
adc_ib_dat_i,
|
||||
adc_it_clk_d_o,
|
||||
adc_it_clk_o,
|
||||
adc_it_dat_d_i,
|
||||
adc_it_dat_i,
|
||||
adc_vbus_clk_o,
|
||||
adc_vbus_dat_i,
|
||||
position_m1_i,
|
||||
position_m2_i,
|
||||
adc_clk_o,
|
||||
adc_m1_ia_dat_i,
|
||||
adc_m1_ib_dat_i,
|
||||
adc_m1_vbus_dat_i,
|
||||
fmc_m1_en_o,
|
||||
fmc_m1_fault_i,
|
||||
gpo_o,
|
||||
position_i,
|
||||
pwm_ah_o,
|
||||
pwm_al_o,
|
||||
pwm_bh_o,
|
||||
pwm_bl_o,
|
||||
pwm_ch_o,
|
||||
pwm_cl_o,
|
||||
|
||||
//vauxn0,
|
||||
//vauxn8,
|
||||
//vauxp0,
|
||||
//vauxp8,
|
||||
//vn_in,
|
||||
//vp_in,
|
||||
//muxaddr_out,
|
||||
fmc_m2_en_o,
|
||||
adc_m2_ia_dat_i,
|
||||
adc_m2_ib_dat_i,
|
||||
adc_m2_vbus_dat_i,
|
||||
pwm_m1_ah_o,
|
||||
pwm_m1_al_o,
|
||||
pwm_m1_bh_o,
|
||||
pwm_m1_bl_o,
|
||||
pwm_m1_ch_o,
|
||||
pwm_m1_cl_o,
|
||||
pwm_m1_dh_o,
|
||||
pwm_m1_dl_o,
|
||||
pwm_m2_ah_o,
|
||||
pwm_m2_al_o,
|
||||
pwm_m2_bh_o,
|
||||
pwm_m2_bl_o,
|
||||
pwm_m2_ch_o,
|
||||
pwm_m2_cl_o,
|
||||
pwm_m2_dh_o,
|
||||
pwm_m2_dl_o,
|
||||
vt_enable,
|
||||
/* vauxn0,
|
||||
vauxn8,
|
||||
vauxp0,
|
||||
vauxp8,
|
||||
muxaddr_out,*/
|
||||
|
||||
i2s_mclk,
|
||||
i2s_bclk,
|
||||
|
|
@ -118,6 +137,17 @@ module system_top (
|
|||
iic_mux_scl,
|
||||
iic_mux_sda,
|
||||
|
||||
iic_ee2_scl_io,
|
||||
iic_ee2_sda_io,
|
||||
|
||||
fmc_spi1_sel1_rdc,
|
||||
fmc_spi1_miso,
|
||||
fmc_spi1_mosi,
|
||||
fmc_spi1_sck,
|
||||
fmc_sample_n,
|
||||
gpo,
|
||||
gpi,
|
||||
|
||||
otg_vbusoc);
|
||||
|
||||
inout [14:0] DDR_addr;
|
||||
|
|
@ -136,6 +166,24 @@ module system_top (
|
|||
inout DDR_reset_n;
|
||||
inout DDR_we_n;
|
||||
|
||||
input [3:0] eth1_rgmii_rd;
|
||||
input eth1_rgmii_rx_ctl;
|
||||
input eth1_rgmii_rxc;
|
||||
output [3:0] eth1_rgmii_td;
|
||||
output eth1_rgmii_tx_ctl;
|
||||
output eth1_rgmii_txc;
|
||||
|
||||
input [3:0] eth2_rgmii_rd;
|
||||
input eth2_rgmii_rx_ctl;
|
||||
input eth2_rgmii_rxc;
|
||||
output [3:0] eth2_rgmii_td;
|
||||
output eth2_rgmii_tx_ctl;
|
||||
output eth2_rgmii_txc;
|
||||
|
||||
inout eth_mdio_io;
|
||||
output eth_mdio_mdc;
|
||||
output eth_phy_rst_n;
|
||||
|
||||
inout FIXED_IO_ddr_vrn;
|
||||
inout FIXED_IO_ddr_vrp;
|
||||
inout [53:0] FIXED_IO_mio;
|
||||
|
|
@ -151,38 +199,41 @@ module system_top (
|
|||
output hdmi_data_e;
|
||||
output [15:0] hdmi_data;
|
||||
|
||||
output adc_ia_clk_d_o;
|
||||
output adc_ia_clk_o;
|
||||
input adc_ia_dat_d_i;
|
||||
input adc_ia_dat_i;
|
||||
output adc_ib_clk_d_o;
|
||||
output adc_ib_clk_o;
|
||||
input adc_ib_dat_d_i;
|
||||
input adc_ib_dat_i;
|
||||
output adc_it_clk_d_o;
|
||||
output adc_it_clk_o;
|
||||
input adc_it_dat_d_i;
|
||||
input adc_it_dat_i;
|
||||
output adc_vbus_clk_o;
|
||||
input adc_vbus_dat_i;
|
||||
input [2:0] position_m1_i;
|
||||
input [2:0] position_m2_i;
|
||||
output adc_clk_o;
|
||||
output fmc_m1_en_o;
|
||||
input fmc_m1_fault_i;
|
||||
output [7:0] gpo_o;
|
||||
input [2:0] position_i;
|
||||
output pwm_ah_o;
|
||||
output pwm_al_o;
|
||||
output pwm_bh_o;
|
||||
output pwm_bl_o;
|
||||
output pwm_ch_o;
|
||||
output pwm_cl_o;
|
||||
input adc_m1_ia_dat_i;
|
||||
input adc_m1_ib_dat_i;
|
||||
input adc_m1_vbus_dat_i;
|
||||
output fmc_m2_en_o;
|
||||
input adc_m2_ia_dat_i;
|
||||
input adc_m2_ib_dat_i;
|
||||
input adc_m2_vbus_dat_i;
|
||||
output pwm_m1_ah_o;
|
||||
output pwm_m1_al_o;
|
||||
output pwm_m1_bh_o;
|
||||
output pwm_m1_bl_o;
|
||||
output pwm_m1_ch_o;
|
||||
output pwm_m1_cl_o;
|
||||
output pwm_m1_dh_o;
|
||||
output pwm_m1_dl_o;
|
||||
output pwm_m2_ah_o;
|
||||
output pwm_m2_al_o;
|
||||
output pwm_m2_bh_o;
|
||||
output pwm_m2_bl_o;
|
||||
output pwm_m2_ch_o;
|
||||
output pwm_m2_cl_o;
|
||||
output pwm_m2_dh_o;
|
||||
output pwm_m2_dl_o;
|
||||
|
||||
output vt_enable;
|
||||
|
||||
//input vauxn0;
|
||||
//input vauxn8;
|
||||
//input vauxp0;
|
||||
//input vauxp8;
|
||||
//input vn_in;
|
||||
//input vp_in;
|
||||
//output [3:0] muxaddr_out;
|
||||
/* input vauxn0;
|
||||
input vauxn8;
|
||||
input vauxp0;
|
||||
input vauxp8;
|
||||
output [ 3:0] muxaddr_out;*/
|
||||
|
||||
output spdif;
|
||||
|
||||
|
|
@ -198,13 +249,24 @@ module system_top (
|
|||
inout [ 1:0] iic_mux_scl;
|
||||
inout [ 1:0] iic_mux_sda;
|
||||
|
||||
inout iic_ee2_scl_io;
|
||||
inout iic_ee2_sda_io;
|
||||
|
||||
output fmc_spi1_sel1_rdc;
|
||||
input fmc_spi1_miso;
|
||||
output fmc_spi1_mosi;
|
||||
output fmc_spi1_sck;
|
||||
output fmc_sample_n;
|
||||
output [ 3:0] gpo;
|
||||
input [ 1:0] gpi;
|
||||
|
||||
input otg_vbusoc;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [31:0] gpio_i;
|
||||
wire [31:0] gpio_o;
|
||||
wire [31:0] gpio_t;
|
||||
wire [34:0] gpio_i;
|
||||
wire [34:0] gpio_o;
|
||||
wire [34:0] gpio_t;
|
||||
wire [ 1:0] iic_mux_scl_i_s;
|
||||
wire [ 1:0] iic_mux_scl_o_s;
|
||||
wire iic_mux_scl_t_s;
|
||||
|
|
@ -213,14 +275,33 @@ module system_top (
|
|||
wire iic_mux_sda_t_s;
|
||||
wire [15:0] ps_intrs;
|
||||
|
||||
wire refclk;
|
||||
wire refclk_rst;
|
||||
|
||||
wire eth_mdio_o;
|
||||
wire eth_mdio_i;
|
||||
wire eth_mdio_t;
|
||||
|
||||
reg idelayctrl_reset;
|
||||
reg [ 3:0] idelay_reset_cnt;
|
||||
|
||||
// assignments
|
||||
|
||||
assign fmc_sample_n = gpio_o[32];
|
||||
assign gpio_i[34:33] = gpi[1:0];
|
||||
assign vt_enable = 1'b1;
|
||||
assign pwm_m1_dh_o = 1'b0;
|
||||
assign pwm_m1_dl_o = 1'b0;
|
||||
assign pwm_m2_dh_o = 1'b0;
|
||||
assign pwm_m2_dl_o = 1'b0;
|
||||
// instantiations
|
||||
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(32))
|
||||
i_gpio_bd (
|
||||
.dt(gpio_t),
|
||||
.di(gpio_o),
|
||||
.do(gpio_i),
|
||||
.dt(gpio_t[31:0]),
|
||||
.di(gpio_o[31:0]),
|
||||
.do(gpio_i[31:0]),
|
||||
.dio(gpio_bd));
|
||||
|
||||
ad_iobuf #(
|
||||
|
|
@ -239,6 +320,48 @@ module system_top (
|
|||
.do(iic_mux_sda_i_s),
|
||||
.dio(iic_mux_sda));
|
||||
|
||||
ad_iobuf #(
|
||||
.DATA_WIDTH(1))
|
||||
i_mdio_io (
|
||||
.dt(eth_mdio_t),
|
||||
.di(eth_mdio_o),
|
||||
.do(eth_mdio_i),
|
||||
.dio(eth_mdio_io));
|
||||
|
||||
always @(posedge refclk) begin
|
||||
if (refclk_rst == 1'b1) begin
|
||||
idelay_reset_cnt <= 4'h0;
|
||||
idelayctrl_reset <= 1'b1;
|
||||
end else begin
|
||||
idelayctrl_reset <= 1'b1;
|
||||
case (idelay_reset_cnt)
|
||||
4'h0: idelay_reset_cnt <= 4'h1;
|
||||
4'h1: idelay_reset_cnt <= 4'h2;
|
||||
4'h2: idelay_reset_cnt <= 4'h3;
|
||||
4'h3: idelay_reset_cnt <= 4'h4;
|
||||
4'h4: idelay_reset_cnt <= 4'h5;
|
||||
4'h5: idelay_reset_cnt <= 4'h6;
|
||||
4'h6: idelay_reset_cnt <= 4'h7;
|
||||
4'h7: idelay_reset_cnt <= 4'h8;
|
||||
4'h8: idelay_reset_cnt <= 4'h9;
|
||||
4'h9: idelay_reset_cnt <= 4'ha;
|
||||
4'ha: idelay_reset_cnt <= 4'hb;
|
||||
4'hb: idelay_reset_cnt <= 4'hc;
|
||||
4'hc: idelay_reset_cnt <= 4'hd;
|
||||
4'hd: idelay_reset_cnt <= 4'he;
|
||||
default: begin
|
||||
idelay_reset_cnt <= 4'he;
|
||||
idelayctrl_reset <= 1'b0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
IDELAYCTRL dlyctrl (
|
||||
.RDY(),
|
||||
.REFCLK(refclk),
|
||||
.RST(idelayctrl_reset));
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.DDR_addr (DDR_addr),
|
||||
.DDR_ba (DDR_ba),
|
||||
|
|
@ -264,42 +387,61 @@ module system_top (
|
|||
.GPIO_I (gpio_i),
|
||||
.GPIO_O (gpio_o),
|
||||
.GPIO_T (gpio_t),
|
||||
|
||||
.eth1_rgmii_rd(eth1_rgmii_rd),
|
||||
.eth1_rgmii_rx_ctl(eth1_rgmii_rx_ctl),
|
||||
.eth1_rgmii_rxc(eth1_rgmii_rxc),
|
||||
.eth1_rgmii_td(eth1_rgmii_td),
|
||||
.eth1_rgmii_tx_ctl(eth1_rgmii_tx_ctl),
|
||||
.eth1_rgmii_txc(eth1_rgmii_txc),
|
||||
|
||||
.eth2_rgmii_rd(eth2_rgmii_rd),
|
||||
.eth2_rgmii_rx_ctl(eth2_rgmii_rx_ctl),
|
||||
.eth2_rgmii_rxc(eth2_rgmii_rxc),
|
||||
.eth2_rgmii_td(eth2_rgmii_td),
|
||||
.eth2_rgmii_tx_ctl(eth2_rgmii_tx_ctl),
|
||||
.eth2_rgmii_txc(eth2_rgmii_txc),
|
||||
|
||||
.eth_phy_rst_n(eth_phy_rst_n),
|
||||
.eth_mdio_o(eth_mdio_o),
|
||||
.eth_mdio_t(eth_mdio_t),
|
||||
.eth_mdio_i(eth_mdio_i),
|
||||
.eth_mdio_mdc(eth_mdio_mdc),
|
||||
|
||||
.hdmi_data (hdmi_data),
|
||||
.hdmi_data_e (hdmi_data_e),
|
||||
.hdmi_hsync (hdmi_hsync),
|
||||
.hdmi_out_clk (hdmi_out_clk),
|
||||
.hdmi_vsync (hdmi_vsync),
|
||||
.adc_ia_clk_d_o(adc_ia_clk_d_o),
|
||||
.adc_ia_clk_o(adc_ia_clk_o),
|
||||
.adc_ia_dat_d_i(adc_ia_dat_d_i),
|
||||
.adc_ia_dat_i(adc_ia_dat_i),
|
||||
.adc_ib_clk_d_o(adc_ib_clk_d_o),
|
||||
.adc_ib_clk_o(adc_ib_clk_o),
|
||||
.adc_ib_dat_d_i(adc_ib_dat_d_i),
|
||||
.adc_ib_dat_i(adc_ib_dat_i),
|
||||
.adc_it_clk_d_o(adc_it_clk_d_o),
|
||||
.adc_it_clk_o(adc_it_clk_o),
|
||||
.adc_it_dat_d_i(adc_it_dat_d_i),
|
||||
.adc_it_dat_i(adc_it_dat_i),
|
||||
.adc_vbus_clk_o(adc_vbus_clk_o),
|
||||
.adc_vbus_dat_i(adc_vbus_dat_i),
|
||||
.position_m1_i(position_m1_i),
|
||||
.position_m2_i(position_m2_i),
|
||||
.adc_clk_o(adc_clk_o),
|
||||
.fmc_m1_en_o(fmc_m1_en_o),
|
||||
.fmc_m1_fault_i(fmc_m1_fault_i),
|
||||
.gpo_o(gpo_o),
|
||||
.position_i(position_i),
|
||||
.pwm_ah_o(pwm_ah_o),
|
||||
.pwm_al_o(pwm_al_o),
|
||||
.pwm_bh_o(pwm_bh_o),
|
||||
.pwm_bl_o(pwm_bl_o),
|
||||
.pwm_ch_o(pwm_ch_o),
|
||||
.pwm_cl_o(pwm_cl_o),
|
||||
//.Vaux0_v_n(vauxn0),
|
||||
//.Vaux0_v_p(vauxp0),
|
||||
//.vauxn8(vauxn8),
|
||||
//.vauxp8(vauxp8),
|
||||
//.Vp_Vn_v_n(vn_in),
|
||||
//.Vp_Vn_v_p(vp_in),
|
||||
//.muxaddr_out(muxaddr_out),
|
||||
.adc_m1_ia_dat_i(adc_m1_ia_dat_i),
|
||||
.adc_m1_ib_dat_i(adc_m1_ib_dat_i),
|
||||
.adc_m1_vbus_dat_i(adc_m1_vbus_dat_i),
|
||||
.fmc_m2_en_o(fmc_m2_en_o),
|
||||
.adc_m2_ia_dat_i(adc_m2_ia_dat_i),
|
||||
.adc_m2_ib_dat_i(adc_m2_ib_dat_i),
|
||||
.adc_m2_vbus_dat_i(adc_m2_vbus_dat_i),
|
||||
.gpo_o(gpo),
|
||||
.pwm_m1_ah_o(pwm_m1_ah_o),
|
||||
.pwm_m1_al_o(pwm_m1_al_o),
|
||||
.pwm_m1_bh_o(pwm_m1_bh_o),
|
||||
.pwm_m1_bl_o(pwm_m1_bl_o),
|
||||
.pwm_m1_ch_o(pwm_m1_ch_o),
|
||||
.pwm_m1_cl_o(pwm_m1_cl_o),
|
||||
.pwm_m2_ah_o(pwm_m2_ah_o),
|
||||
.pwm_m2_al_o(pwm_m2_al_o),
|
||||
.pwm_m2_bh_o(pwm_m2_bh_o),
|
||||
.pwm_m2_bl_o(pwm_m2_bl_o),
|
||||
.pwm_m2_ch_o(pwm_m2_ch_o),
|
||||
.pwm_m2_cl_o(pwm_m2_cl_o),
|
||||
/* .Vaux0_v_n(vauxn0),
|
||||
.Vaux0_v_p(vauxp0),
|
||||
.Vaux8_v_n(vauxn8),
|
||||
.Vaux8_v_p(vauxp8),
|
||||
.muxaddr_out(muxaddr_out),*/
|
||||
.i2s_bclk (i2s_bclk),
|
||||
.i2s_lrclk (i2s_lrclk),
|
||||
.i2s_mclk (i2s_mclk),
|
||||
|
|
@ -313,12 +455,12 @@ module system_top (
|
|||
.iic_mux_sda_I (iic_mux_sda_i_s),
|
||||
.iic_mux_sda_O (iic_mux_sda_o_s),
|
||||
.iic_mux_sda_T (iic_mux_sda_t_s),
|
||||
.ps_intr_0 (ps_intrs[0]),
|
||||
.ps_intr_1 (ps_intrs[1]),
|
||||
.ps_intr_10 (ps_intrs[10]),
|
||||
.ps_intr_11 (ps_intrs[11]),
|
||||
.ps_intr_12 (ps_intrs[12]),
|
||||
.ps_intr_13 (ps_intrs[13]),
|
||||
.ps_intr_0 (ps_intrs[0]),
|
||||
.ps_intr_1 (ps_intrs[1]),
|
||||
.ps_intr_2 (ps_intrs[2]),
|
||||
.ps_intr_3 (ps_intrs[3]),
|
||||
.ps_intr_4 (ps_intrs[4]),
|
||||
|
|
@ -327,11 +469,25 @@ module system_top (
|
|||
.ps_intr_7 (ps_intrs[7]),
|
||||
.ps_intr_8 (ps_intrs[8]),
|
||||
.ps_intr_9 (ps_intrs[9]),
|
||||
.iic_fmc_intr(ps_intrs[11]),
|
||||
.motcon1_c_m_1_irq(ps_intrs[13]),
|
||||
.motcon1_c_m_2_irq(ps_intrs[9]),
|
||||
.motcon1_s_d_irq(ps_intrs[12]),
|
||||
.motcon1_ctrl_irq(ps_intrs[10]),
|
||||
.iic_fmc_intr(ps_intrs[13]),
|
||||
.iic_ee2_intr(ps_intrs[12]),
|
||||
.motcon2_s_d1_intr(ps_intrs[11]),
|
||||
.motcon2_c_m1_intr(ps_intrs[10]),
|
||||
.motcon2_ctrl_m1_intr(ps_intrs[9]),
|
||||
.motcon2_s_d2_intr(ps_intrs[8]),
|
||||
.motcon2_c_m2_intr(ps_intrs[7]),
|
||||
.motcon2_ctrl_m2_intr(ps_intrs[6]),
|
||||
.iic_ee2_scl_io(iic_ee2_scl_io),
|
||||
.iic_ee2_sda_io(iic_ee2_sda_io),
|
||||
.spi_csn_i (1'b1),
|
||||
.spi_csn_o (fmc_spi1_sel1_rdc),
|
||||
.spi_miso_i (fmc_spi1_miso),
|
||||
.spi_mosi_i (1'b0),
|
||||
.spi_mosi_o (fmc_spi1_mosi),
|
||||
.spi_sclk_i (1'b0),
|
||||
.spi_sclk_o (fmc_spi1_sck),
|
||||
.refclk(refclk),
|
||||
.refclk_rst(refclk_rst),
|
||||
.otg_vbusoc (otg_vbusoc),
|
||||
.spdif (spdif));
|
||||
|
||||
Loading…
Reference in New Issue