daq3/zcu102: Initial commit
AndreiGrozav
parent
6b897dabe5
commit
febdbe8dcb
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####################################################################################
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####################################################################################
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## Copyright 2011(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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####################################################################################
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M_DEPS += system_top.v
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M_DEPS += system_project.tcl
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M_DEPS += system_constr.xdc
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M_DEPS += system_bd.tcl
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M_DEPS += ../common/daq3_spi.v
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M_DEPS += ../common/daq3_bd.tcl
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M_DEPS += ../../scripts/adi_project.tcl
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M_DEPS += ../../scripts/adi_env.tcl
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M_DEPS += ../../scripts/adi_board.tcl
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M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
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M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
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M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
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M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
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M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
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M_DEPS += ../../../library/axi_ad9152/axi_ad9152.xpr
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M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr
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M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr
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M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
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M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
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M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
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M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
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M_DEPS += ../../../library/jesd204/axi_jesd204_rx/axi_jesd204_rx.xpr
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M_DEPS += ../../../library/jesd204/axi_jesd204_tx/axi_jesd204_tx.xpr
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M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
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M_DEPS += ../../../library/jesd204/jesd204_rx/jesd204_rx.xpr
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M_DEPS += ../../../library/jesd204/jesd204_tx/jesd204_tx.xpr
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M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
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M_DEPS += ../../../library/util_cpack/util_cpack.xpr
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M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
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M_DEPS += ../../../library/util_upack/util_upack.xpr
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M_VIVADO := vivado -mode batch -source
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M_FLIST := *.cache
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M_FLIST += *.data
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M_FLIST += *.xpr
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M_FLIST += *.log
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M_FLIST += *.jou
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M_FLIST += xgui
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M_FLIST += *.runs
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M_FLIST += *.srcs
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M_FLIST += *.sdk
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M_FLIST += *.hw
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M_FLIST += *.sim
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M_FLIST += .Xil
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M_FLIST += *.ip_user_files
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.PHONY: all lib clean clean-all
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all: lib daq3_zcu102.sdk/system_top.hdf
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clean:
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rm -rf $(M_FLIST)
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clean-all:clean
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make -C ../../../library/axi_ad9152 clean
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make -C ../../../library/axi_ad9680 clean
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make -C ../../../library/xilinx/axi_adcfifo clean
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make -C ../../../library/xilinx/axi_adxcvr clean
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make -C ../../../library/axi_clkgen clean
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make -C ../../../library/axi_dmac clean
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make -C ../../../library/axi_hdmi_tx clean
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make -C ../../../library/jesd204/axi_jesd204_rx clean
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make -C ../../../library/jesd204/axi_jesd204_tx clean
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make -C ../../../library/axi_spdif_tx clean
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make -C ../../../library/jesd204/jesd204_rx clean
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make -C ../../../library/jesd204/jesd204_tx clean
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make -C ../../../library/xilinx/util_adxcvr clean
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make -C ../../../library/util_cpack clean
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make -C ../../../library/util_dacfifo clean
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make -C ../../../library/util_upack clean
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daq3_zcu102.sdk/system_top.hdf: $(M_DEPS)
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-rm -rf $(M_FLIST)
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$(M_VIVADO) system_project.tcl >> daq3_zcu102_vivado.log 2>&1
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lib:
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make -C ../../../library/axi_ad9152
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make -C ../../../library/axi_ad9680
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make -C ../../../library/xilinx/axi_adcfifo
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make -C ../../../library/xilinx/axi_adxcvr
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make -C ../../../library/axi_clkgen
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make -C ../../../library/axi_dmac
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make -C ../../../library/axi_hdmi_tx
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make -C ../../../library/jesd204/axi_jesd204_rx
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make -C ../../../library/jesd204/axi_jesd204_tx
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make -C ../../../library/axi_spdif_tx
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make -C ../../../library/jesd204/jesd204_rx
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make -C ../../../library/jesd204/jesd204_tx
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make -C ../../../library/xilinx/util_adxcvr
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make -C ../../../library/util_cpack
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make -C ../../../library/util_dacfifo
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make -C ../../../library/util_upack
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####################################################################################
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####################################################################################
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@ -0,0 +1,19 @@
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set adc_fifo_name axi_ad9680_fifo
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set adc_fifo_address_width 16
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set adc_data_width 128
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set adc_dma_data_width 64
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set dac_fifo_name axi_ad9152_fifo
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set dac_fifo_address_width 10
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set dac_data_width 128
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set dac_dma_data_width 128
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source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
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source ../common/daq3_bd.tcl
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ad_ip_parameter util_daq3_xcvr CONFIG.XCVR_TYPE 2
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ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_FBDIV 20
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ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_REFCLK_DIV 1
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# FMC_HPC 0
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# daq3
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set_property -dict {PACKAGE_PIN L8 } [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC0_GBTCLK1_M2C_C_P
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set_property -dict {PACKAGE_PIN L7 } [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC0_GBTCLK1_M2C_C_N
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set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVDS} [get_ports rx_sync_p] ; ## D08 FMC_HPC0_LA01_CC_P
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set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVDS} [get_ports rx_sync_n] ; ## D09 FMC_HPC0_LA01_CC_N
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set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G09 FMC_HPC0_LA03_P
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set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G10 FMC_HPC0_LA03_N
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set_property -dict {PACKAGE_PIN G8 } [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC0_GBTCLK0_M2C_C_P
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set_property -dict {PACKAGE_PIN G7 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC0_GBTCLK0_M2C_C_N
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set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC0_LA02_P
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set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC0_LA02_N
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set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## H10 FMC_HPC0_LA04_P
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set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sysref_n] ; ## H11 FMC_HPC0_LA04_N
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set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS18} [get_ports spi_csn_clk] ; ## D11 FMC_HPC0_LA05_P
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set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## D12 FMC_HPC0_LA05_N
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set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS18} [get_ports spi_csn_dac] ; ## C14 FMC_HPC0_LA10_P
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set_property -dict {PACKAGE_PIN AC4 IOSTANDARD LVCMOS18} [get_ports spi_csn_adc] ; ## D15 FMC_HPC0_LA09_N
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set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVCMOS18} [get_ports spi_sdio] ; ## D14 FMC_HPC0_LA09_P
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set_property -dict {PACKAGE_PIN AC1 IOSTANDARD LVCMOS18} [get_ports spi_dir] ; ## C11 FMC_HPC0_LA06_N
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set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVDS} [get_ports sysref_p] ; ## D17 FMC_HPC0_LA13_P
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set_property -dict {PACKAGE_PIN AC8 IOSTANDARD LVDS} [get_ports sysref_n] ; ## D18 FMC_HPC0_LA13_N
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set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS18} [get_ports dac_txen] ; ## G16 FMC_HPC0_LA12_N
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set_property -dict {PACKAGE_PIN AC2 IOSTANDARD LVCMOS18} [get_ports adc_pd] ; ## C10 FMC_HPC0_LA06_P
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set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS18} [get_ports clkd_status[0]] ; ## G12 FMC_HPC0_LA08_P
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set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVCMOS18} [get_ports clkd_status[1]] ; ## G13 FMC_HPC0_LA08_N
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set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS18} [get_ports dac_irq] ; ## G15 FMC_HPC0_LA12_P
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set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS18} [get_ports adc_fda] ; ## H16 FMC_HPC0_LA11_P
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set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS18} [get_ports adc_fdb] ; ## H17 FMC_HPC0_LA11_N
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set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports trig_p] ; ## H13 FMC_HPC0_LA07_P
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set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports trig_n] ; ## H14 FMC_HPC0_LA07_N
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set_property LOC GTHE4_CHANNEL_X1Y8 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_0/i_gthe4_channel}]
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set_property LOC GTHE4_CHANNEL_X1Y10 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_1/i_gthe4_channel}]
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set_property LOC GTHE4_CHANNEL_X1Y11 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_2/i_gthe4_channel}]
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set_property LOC GTHE4_CHANNEL_X1Y9 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_3/i_gthe4_channel}]
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# clocks
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create_clock -name tx_ref_clk -period 1.60 [get_ports tx_ref_clk_p]
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create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p]
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create_clock -name tx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe4_channel/TXOUTCLK]
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create_clock -name rx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe4_channel/RXOUTCLK]
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set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9680_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]
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set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9152_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]
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# gt pin assignments below are for reference only and are ignored by the tool!
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# set_property -dict {PACKAGE_PIN K2 } [get_ports rx_data_p[0]] ; ## A10 FMC_HPC0_DP3_M2C_P
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# set_property -dict {PACKAGE_PIN K1 } [get_ports rx_data_n[0]] ; ## A11 FMC_HPC0_DP3_M2C_N
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# set_property -dict {PACKAGE_PIN H2 } [get_ports rx_data_p[1]] ; ## C06 FMC_HPC0_DP0_M2C_P
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# set_property -dict {PACKAGE_PIN H1 } [get_ports rx_data_n[1]] ; ## C07 FMC_HPC0_DP0_M2C_N
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# set_property -dict {PACKAGE_PIN F2 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC0_DP2_M2C_P
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# set_property -dict {PACKAGE_PIN F1 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC0_DP2_M2C_N
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# set_property -dict {PACKAGE_PIN J4 } [get_ports rx_data_p[3]] ; ## A02 FMC_HPC0_DP1_M2C_P
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# set_property -dict {PACKAGE_PIN J3 } [get_ports rx_data_n[3]] ; ## A03 FMC_HPC0_DP1_M2C_N
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# set_property -dict {PACKAGE_PIN K6 } [get_ports tx_data_p[0]] ; ## A30 FMC_HPC0_DP3_C2M_P (tx_data_p[0])
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# set_property -dict {PACKAGE_PIN K5 } [get_ports tx_data_n[0]] ; ## A31 FMC_HPC0_DP3_C2M_N (tx_data_n[0])
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# set_property -dict {PACKAGE_PIN G4 } [get_ports tx_data_p[1]] ; ## C02 FMC_HPC0_DP0_C2M_P (tx_data_p[3])
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# set_property -dict {PACKAGE_PIN G3 } [get_ports tx_data_n[1]] ; ## C03 FMC_HPC0_DP0_C2M_N (tx_data_n[3])
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# set_property -dict {PACKAGE_PIN F6 } [get_ports tx_data_p[2]] ; ## A26 FMC_HPC0_DP2_C2M_P (tx_data_p[1])
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# set_property -dict {PACKAGE_PIN F5 } [get_ports tx_data_n[2]] ; ## A27 FMC_HPC0_DP2_C2M_N (tx_data_n[1])
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# set_property -dict {PACKAGE_PIN H6 } [get_ports tx_data_p[3]] ; ## A22 FMC_HPC0_DP1_C2M_P (tx_data_p[2])
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# set_property -dict {PACKAGE_PIN H5 } [get_ports tx_data_n[3]] ; ## A23 FMC_HPC0_DP1_C2M_N (tx_data_n[2])
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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adi_project_xilinx daq3_zcu102
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adi_project_files daq3_zcu102 [list \
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"../common/daq3_spi.v" \
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"system_top.v" \
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"system_constr.xdc"\
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"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
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"$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
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adi_project_run daq3_zcu102
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@ -0,0 +1,222 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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input [12:0] gpio_bd_i,
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output [ 7:0] gpio_bd_o,
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input rx_ref_clk_p,
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input rx_ref_clk_n,
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input rx_sysref_p,
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input rx_sysref_n,
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output rx_sync_p,
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output rx_sync_n,
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input [ 3:0] rx_data_p,
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input [ 3:0] rx_data_n,
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input tx_ref_clk_p,
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input tx_ref_clk_n,
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input tx_sysref_p,
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input tx_sysref_n,
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input tx_sync_p,
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input tx_sync_n,
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output [ 3:0] tx_data_p,
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output [ 3:0] tx_data_n,
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input trig_p,
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input trig_n,
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inout adc_fdb,
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inout adc_fda,
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inout dac_irq,
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inout [ 1:0] clkd_status,
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inout adc_pd,
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inout dac_txen,
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output sysref_p,
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output sysref_n,
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output spi_csn_clk,
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output spi_csn_dac,
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output spi_csn_adc,
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output spi_clk,
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inout spi_sdio,
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output spi_dir);
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// internal signals
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wire [94:0] gpio_i;
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wire [94:0] gpio_o;
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wire [ 2:0] spi_csn;
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wire spi_mosi;
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wire spi_miso;
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wire trig;
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wire rx_ref_clk;
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wire rx_sysref;
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wire rx_sync;
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wire tx_ref_clk;
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wire tx_sysref;
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wire tx_sync;
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// spi
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assign spi_csn_adc = spi_csn[2];
|
||||
assign spi_csn_dac = spi_csn[1];
|
||||
assign spi_csn_clk = spi_csn[0];
|
||||
|
||||
// instantiations
|
||||
|
||||
IBUFDS_GTE4 i_ibufds_rx_ref_clk (
|
||||
.CEB (1'd0),
|
||||
.I (rx_ref_clk_p),
|
||||
.IB (rx_ref_clk_n),
|
||||
.O (rx_ref_clk),
|
||||
.ODIV2 ());
|
||||
|
||||
IBUFDS i_ibufds_rx_sysref (
|
||||
.I (rx_sysref_p),
|
||||
.IB (rx_sysref_n),
|
||||
.O (rx_sysref));
|
||||
|
||||
OBUFDS i_obufds_rx_sync (
|
||||
.I (rx_sync),
|
||||
.O (rx_sync_p),
|
||||
.OB (rx_sync_n));
|
||||
|
||||
IBUFDS_GTE4 i_ibufds_tx_ref_clk (
|
||||
.CEB (1'd0),
|
||||
.I (tx_ref_clk_p),
|
||||
.IB (tx_ref_clk_n),
|
||||
.O (tx_ref_clk),
|
||||
.ODIV2 ());
|
||||
|
||||
IBUFDS i_ibufds_tx_sysref (
|
||||
.I (tx_sysref_p),
|
||||
.IB (tx_sysref_n),
|
||||
.O (tx_sysref));
|
||||
|
||||
IBUFDS i_ibufds_tx_sync (
|
||||
.I (tx_sync_p),
|
||||
.IB (tx_sync_n),
|
||||
.O (tx_sync));
|
||||
|
||||
daq3_spi i_spi (
|
||||
.spi_csn (spi_csn),
|
||||
.spi_clk (spi_clk),
|
||||
.spi_mosi (spi_mosi),
|
||||
.spi_miso (spi_miso),
|
||||
.spi_sdio (spi_sdio),
|
||||
.spi_dir (spi_dir));
|
||||
|
||||
OBUFDS i_obufds_sysref (
|
||||
.I (gpio_o[43]),
|
||||
.O (sysref_p),
|
||||
.OB (sysref_n));
|
||||
|
||||
IBUFDS i_ibufds_trig (
|
||||
.I (trig_p),
|
||||
.IB (trig_n),
|
||||
.O (trig));
|
||||
|
||||
assign adc_pd = gpio_o[42];
|
||||
assign dac_txen = gpio_o[41];
|
||||
assign dac_reset = gpio_o[40];
|
||||
assign clkd_sync = gpio_o[38];
|
||||
assign gpio_bd_o = gpio_o[7:0];
|
||||
|
||||
assign gpio_i[94:44] = gpio_o[94:44];
|
||||
assign gpio_i[43:43] = trig;
|
||||
assign gpio_i[42:37] = gpio_o[42:37];
|
||||
assign gpio_i[36:36] = adc_fdb;
|
||||
assign gpio_i[35:35] = adc_fda;
|
||||
assign gpio_i[34:34] = dac_irq;
|
||||
assign gpio_i[33:32] = clkd_status;
|
||||
assign gpio_i[31:21] = gpio_o[31:21];
|
||||
assign gpio_i[20: 8] = gpio_bd_i;
|
||||
assign gpio_i[ 7: 0] = gpio_o[7:0];
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.ps_intr_00 (1'd0),
|
||||
.ps_intr_01 (1'd0),
|
||||
.ps_intr_02 (1'd0),
|
||||
.ps_intr_03 (1'd0),
|
||||
.ps_intr_04 (1'd0),
|
||||
.ps_intr_05 (1'd0),
|
||||
.ps_intr_06 (1'd0),
|
||||
.ps_intr_07 (1'd0),
|
||||
.ps_intr_08 (1'd0),
|
||||
.ps_intr_09 (1'd0),
|
||||
.ps_intr_14 (1'd0),
|
||||
.ps_intr_15 (1'd0),
|
||||
.rx_data_0_n (rx_data_n[0]),
|
||||
.rx_data_0_p (rx_data_p[0]),
|
||||
.rx_data_1_n (rx_data_n[1]),
|
||||
.rx_data_1_p (rx_data_p[1]),
|
||||
.rx_data_2_n (rx_data_n[2]),
|
||||
.rx_data_2_p (rx_data_p[2]),
|
||||
.rx_data_3_n (rx_data_n[3]),
|
||||
.rx_data_3_p (rx_data_p[3]),
|
||||
.rx_ref_clk_0 (rx_ref_clk),
|
||||
.rx_sync_0 (rx_sync),
|
||||
.rx_sysref_0 (rx_sysref),
|
||||
.spi0_csn (spi_csn),
|
||||
.spi0_miso (spi_miso),
|
||||
.spi0_mosi (spi_mosi),
|
||||
.spi0_sclk (spi_clk),
|
||||
.spi1_csn (),
|
||||
.spi1_miso (1'd0),
|
||||
.spi1_mosi (),
|
||||
.spi1_sclk (),
|
||||
.tx_data_0_n (tx_data_n[0]),
|
||||
.tx_data_0_p (tx_data_p[0]),
|
||||
.tx_data_1_n (tx_data_n[1]),
|
||||
.tx_data_1_p (tx_data_p[1]),
|
||||
.tx_data_2_n (tx_data_n[2]),
|
||||
.tx_data_2_p (tx_data_p[2]),
|
||||
.tx_data_3_n (tx_data_n[3]),
|
||||
.tx_data_3_p (tx_data_p[3]),
|
||||
.tx_ref_clk_0 (tx_ref_clk),
|
||||
.tx_sync_0 (tx_sync),
|
||||
.tx_sysref_0 (tx_sysref));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
Loading…
Reference in New Issue