diff --git a/projects/daq3/zcu102/Makefile b/projects/daq3/zcu102/Makefile new file mode 100644 index 000000000..a33c128f2 --- /dev/null +++ b/projects/daq3/zcu102/Makefile @@ -0,0 +1,108 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += system_top.v +M_DEPS += system_project.tcl +M_DEPS += system_constr.xdc +M_DEPS += system_bd.tcl +M_DEPS += ../common/daq3_spi.v +M_DEPS += ../common/daq3_bd.tcl +M_DEPS += ../../scripts/adi_project.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_board.tcl +M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc +M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl +M_DEPS += ../../common/xilinx/dacfifo_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl +M_DEPS += ../../../library/axi_ad9152/axi_ad9152.xpr +M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr +M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr +M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr +M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr +M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr +M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr +M_DEPS += ../../../library/jesd204/axi_jesd204_rx/axi_jesd204_rx.xpr +M_DEPS += ../../../library/jesd204/axi_jesd204_tx/axi_jesd204_tx.xpr +M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr +M_DEPS += ../../../library/jesd204/jesd204_rx/jesd204_rx.xpr +M_DEPS += ../../../library/jesd204/jesd204_tx/jesd204_tx.xpr +M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr +M_DEPS += ../../../library/util_cpack/util_cpack.xpr +M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr +M_DEPS += ../../../library/util_upack/util_upack.xpr + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.runs +M_FLIST += *.srcs +M_FLIST += *.sdk +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil +M_FLIST += *.ip_user_files + + + +.PHONY: all lib clean clean-all +all: lib daq3_zcu102.sdk/system_top.hdf + + +clean: + rm -rf $(M_FLIST) + + +clean-all:clean + make -C ../../../library/axi_ad9152 clean + make -C ../../../library/axi_ad9680 clean + make -C ../../../library/xilinx/axi_adcfifo clean + make -C ../../../library/xilinx/axi_adxcvr clean + make -C ../../../library/axi_clkgen clean + make -C ../../../library/axi_dmac clean + make -C ../../../library/axi_hdmi_tx clean + make -C ../../../library/jesd204/axi_jesd204_rx clean + make -C ../../../library/jesd204/axi_jesd204_tx clean + make -C ../../../library/axi_spdif_tx clean + make -C ../../../library/jesd204/jesd204_rx clean + make -C ../../../library/jesd204/jesd204_tx clean + make -C ../../../library/xilinx/util_adxcvr clean + make -C ../../../library/util_cpack clean + make -C ../../../library/util_dacfifo clean + make -C ../../../library/util_upack clean + + +daq3_zcu102.sdk/system_top.hdf: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) system_project.tcl >> daq3_zcu102_vivado.log 2>&1 + + +lib: + make -C ../../../library/axi_ad9152 + make -C ../../../library/axi_ad9680 + make -C ../../../library/xilinx/axi_adcfifo + make -C ../../../library/xilinx/axi_adxcvr + make -C ../../../library/axi_clkgen + make -C ../../../library/axi_dmac + make -C ../../../library/axi_hdmi_tx + make -C ../../../library/jesd204/axi_jesd204_rx + make -C ../../../library/jesd204/axi_jesd204_tx + make -C ../../../library/axi_spdif_tx + make -C ../../../library/jesd204/jesd204_rx + make -C ../../../library/jesd204/jesd204_tx + make -C ../../../library/xilinx/util_adxcvr + make -C ../../../library/util_cpack + make -C ../../../library/util_dacfifo + make -C ../../../library/util_upack + +#################################################################################### +#################################################################################### diff --git a/projects/daq3/zcu102/system_bd.tcl b/projects/daq3/zcu102/system_bd.tcl new file mode 100644 index 000000000..7b61f5fe6 --- /dev/null +++ b/projects/daq3/zcu102/system_bd.tcl @@ -0,0 +1,19 @@ + +set adc_fifo_name axi_ad9680_fifo +set adc_fifo_address_width 16 +set adc_data_width 128 +set adc_dma_data_width 64 + +set dac_fifo_name axi_ad9152_fifo +set dac_fifo_address_width 10 +set dac_data_width 128 +set dac_dma_data_width 128 + +source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl +source ../common/daq3_bd.tcl + +ad_ip_parameter util_daq3_xcvr CONFIG.XCVR_TYPE 2 +ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_FBDIV 20 +ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_REFCLK_DIV 1 \ No newline at end of file diff --git a/projects/daq3/zcu102/system_constr.xdc b/projects/daq3/zcu102/system_constr.xdc new file mode 100644 index 000000000..cb1f5ecec --- /dev/null +++ b/projects/daq3/zcu102/system_constr.xdc @@ -0,0 +1,74 @@ +# FMC_HPC 0 + +# daq3 + +set_property -dict {PACKAGE_PIN L8 } [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC0_GBTCLK1_M2C_C_P +set_property -dict {PACKAGE_PIN L7 } [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC0_GBTCLK1_M2C_C_N +set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVDS} [get_ports rx_sync_p] ; ## D08 FMC_HPC0_LA01_CC_P +set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVDS} [get_ports rx_sync_n] ; ## D09 FMC_HPC0_LA01_CC_N +set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G09 FMC_HPC0_LA03_P +set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G10 FMC_HPC0_LA03_N + +set_property -dict {PACKAGE_PIN G8 } [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC0_GBTCLK0_M2C_C_P +set_property -dict {PACKAGE_PIN G7 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC0_GBTCLK0_M2C_C_N +set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC0_LA02_P +set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC0_LA02_N +set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## H10 FMC_HPC0_LA04_P +set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sysref_n] ; ## H11 FMC_HPC0_LA04_N + +set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS18} [get_ports spi_csn_clk] ; ## D11 FMC_HPC0_LA05_P +set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## D12 FMC_HPC0_LA05_N +set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS18} [get_ports spi_csn_dac] ; ## C14 FMC_HPC0_LA10_P +set_property -dict {PACKAGE_PIN AC4 IOSTANDARD LVCMOS18} [get_ports spi_csn_adc] ; ## D15 FMC_HPC0_LA09_N +set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVCMOS18} [get_ports spi_sdio] ; ## D14 FMC_HPC0_LA09_P +set_property -dict {PACKAGE_PIN AC1 IOSTANDARD LVCMOS18} [get_ports spi_dir] ; ## C11 FMC_HPC0_LA06_N + +set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVDS} [get_ports sysref_p] ; ## D17 FMC_HPC0_LA13_P +set_property -dict {PACKAGE_PIN AC8 IOSTANDARD LVDS} [get_ports sysref_n] ; ## D18 FMC_HPC0_LA13_N +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS18} [get_ports dac_txen] ; ## G16 FMC_HPC0_LA12_N +set_property -dict {PACKAGE_PIN AC2 IOSTANDARD LVCMOS18} [get_ports adc_pd] ; ## C10 FMC_HPC0_LA06_P + +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS18} [get_ports clkd_status[0]] ; ## G12 FMC_HPC0_LA08_P +set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVCMOS18} [get_ports clkd_status[1]] ; ## G13 FMC_HPC0_LA08_N +set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS18} [get_ports dac_irq] ; ## G15 FMC_HPC0_LA12_P +set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS18} [get_ports adc_fda] ; ## H16 FMC_HPC0_LA11_P +set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS18} [get_ports adc_fdb] ; ## H17 FMC_HPC0_LA11_N + +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports trig_p] ; ## H13 FMC_HPC0_LA07_P +set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports trig_n] ; ## H14 FMC_HPC0_LA07_N + + +set_property LOC GTHE4_CHANNEL_X1Y8 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_0/i_gthe4_channel}] +set_property LOC GTHE4_CHANNEL_X1Y10 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_1/i_gthe4_channel}] +set_property LOC GTHE4_CHANNEL_X1Y11 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_2/i_gthe4_channel}] +set_property LOC GTHE4_CHANNEL_X1Y9 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_3/i_gthe4_channel}] + +# clocks + +create_clock -name tx_ref_clk -period 1.60 [get_ports tx_ref_clk_p] +create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p] +create_clock -name tx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe4_channel/TXOUTCLK] +create_clock -name rx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe4_channel/RXOUTCLK] + +set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9680_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*] +set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9152_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*] + +# gt pin assignments below are for reference only and are ignored by the tool! + +# set_property -dict {PACKAGE_PIN K2 } [get_ports rx_data_p[0]] ; ## A10 FMC_HPC0_DP3_M2C_P +# set_property -dict {PACKAGE_PIN K1 } [get_ports rx_data_n[0]] ; ## A11 FMC_HPC0_DP3_M2C_N +# set_property -dict {PACKAGE_PIN H2 } [get_ports rx_data_p[1]] ; ## C06 FMC_HPC0_DP0_M2C_P +# set_property -dict {PACKAGE_PIN H1 } [get_ports rx_data_n[1]] ; ## C07 FMC_HPC0_DP0_M2C_N +# set_property -dict {PACKAGE_PIN F2 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC0_DP2_M2C_P +# set_property -dict {PACKAGE_PIN F1 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC0_DP2_M2C_N +# set_property -dict {PACKAGE_PIN J4 } [get_ports rx_data_p[3]] ; ## A02 FMC_HPC0_DP1_M2C_P +# set_property -dict {PACKAGE_PIN J3 } [get_ports rx_data_n[3]] ; ## A03 FMC_HPC0_DP1_M2C_N + +# set_property -dict {PACKAGE_PIN K6 } [get_ports tx_data_p[0]] ; ## A30 FMC_HPC0_DP3_C2M_P (tx_data_p[0]) +# set_property -dict {PACKAGE_PIN K5 } [get_ports tx_data_n[0]] ; ## A31 FMC_HPC0_DP3_C2M_N (tx_data_n[0]) +# set_property -dict {PACKAGE_PIN G4 } [get_ports tx_data_p[1]] ; ## C02 FMC_HPC0_DP0_C2M_P (tx_data_p[3]) +# set_property -dict {PACKAGE_PIN G3 } [get_ports tx_data_n[1]] ; ## C03 FMC_HPC0_DP0_C2M_N (tx_data_n[3]) +# set_property -dict {PACKAGE_PIN F6 } [get_ports tx_data_p[2]] ; ## A26 FMC_HPC0_DP2_C2M_P (tx_data_p[1]) +# set_property -dict {PACKAGE_PIN F5 } [get_ports tx_data_n[2]] ; ## A27 FMC_HPC0_DP2_C2M_N (tx_data_n[1]) +# set_property -dict {PACKAGE_PIN H6 } [get_ports tx_data_p[3]] ; ## A22 FMC_HPC0_DP1_C2M_P (tx_data_p[2]) +# set_property -dict {PACKAGE_PIN H5 } [get_ports tx_data_n[3]] ; ## A23 FMC_HPC0_DP1_C2M_N (tx_data_n[2]) diff --git a/projects/daq3/zcu102/system_project.tcl b/projects/daq3/zcu102/system_project.tcl new file mode 100644 index 000000000..bc347415c --- /dev/null +++ b/projects/daq3/zcu102/system_project.tcl @@ -0,0 +1,18 @@ + + + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project_xilinx daq3_zcu102 +adi_project_files daq3_zcu102 [list \ + "../common/daq3_spi.v" \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ] + +adi_project_run daq3_zcu102 + + diff --git a/projects/daq3/zcu102/system_top.v b/projects/daq3/zcu102/system_top.v new file mode 100644 index 000000000..84104b240 --- /dev/null +++ b/projects/daq3/zcu102/system_top.v @@ -0,0 +1,222 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + input [12:0] gpio_bd_i, + output [ 7:0] gpio_bd_o, + + input rx_ref_clk_p, + input rx_ref_clk_n, + input rx_sysref_p, + input rx_sysref_n, + output rx_sync_p, + output rx_sync_n, + input [ 3:0] rx_data_p, + input [ 3:0] rx_data_n, + + input tx_ref_clk_p, + input tx_ref_clk_n, + input tx_sysref_p, + input tx_sysref_n, + input tx_sync_p, + input tx_sync_n, + output [ 3:0] tx_data_p, + output [ 3:0] tx_data_n, + + input trig_p, + input trig_n, + + inout adc_fdb, + inout adc_fda, + inout dac_irq, + inout [ 1:0] clkd_status, + + inout adc_pd, + inout dac_txen, + output sysref_p, + output sysref_n, + + output spi_csn_clk, + output spi_csn_dac, + output spi_csn_adc, + output spi_clk, + inout spi_sdio, + output spi_dir); + + // internal signals + + wire [94:0] gpio_i; + wire [94:0] gpio_o; + wire [ 2:0] spi_csn; + wire spi_mosi; + wire spi_miso; + wire trig; + wire rx_ref_clk; + wire rx_sysref; + wire rx_sync; + wire tx_ref_clk; + wire tx_sysref; + wire tx_sync; + + // spi + + assign spi_csn_adc = spi_csn[2]; + assign spi_csn_dac = spi_csn[1]; + assign spi_csn_clk = spi_csn[0]; + + // instantiations + + IBUFDS_GTE4 i_ibufds_rx_ref_clk ( + .CEB (1'd0), + .I (rx_ref_clk_p), + .IB (rx_ref_clk_n), + .O (rx_ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_rx_sysref ( + .I (rx_sysref_p), + .IB (rx_sysref_n), + .O (rx_sysref)); + + OBUFDS i_obufds_rx_sync ( + .I (rx_sync), + .O (rx_sync_p), + .OB (rx_sync_n)); + + IBUFDS_GTE4 i_ibufds_tx_ref_clk ( + .CEB (1'd0), + .I (tx_ref_clk_p), + .IB (tx_ref_clk_n), + .O (tx_ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_tx_sysref ( + .I (tx_sysref_p), + .IB (tx_sysref_n), + .O (tx_sysref)); + + IBUFDS i_ibufds_tx_sync ( + .I (tx_sync_p), + .IB (tx_sync_n), + .O (tx_sync)); + + daq3_spi i_spi ( + .spi_csn (spi_csn), + .spi_clk (spi_clk), + .spi_mosi (spi_mosi), + .spi_miso (spi_miso), + .spi_sdio (spi_sdio), + .spi_dir (spi_dir)); + + OBUFDS i_obufds_sysref ( + .I (gpio_o[43]), + .O (sysref_p), + .OB (sysref_n)); + + IBUFDS i_ibufds_trig ( + .I (trig_p), + .IB (trig_n), + .O (trig)); + + assign adc_pd = gpio_o[42]; + assign dac_txen = gpio_o[41]; + assign dac_reset = gpio_o[40]; + assign clkd_sync = gpio_o[38]; + assign gpio_bd_o = gpio_o[7:0]; + + assign gpio_i[94:44] = gpio_o[94:44]; + assign gpio_i[43:43] = trig; + assign gpio_i[42:37] = gpio_o[42:37]; + assign gpio_i[36:36] = adc_fdb; + assign gpio_i[35:35] = adc_fda; + assign gpio_i[34:34] = dac_irq; + assign gpio_i[33:32] = clkd_status; + assign gpio_i[31:21] = gpio_o[31:21]; + assign gpio_i[20: 8] = gpio_bd_i; + assign gpio_i[ 7: 0] = gpio_o[7:0]; + + system_wrapper i_system_wrapper ( + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .ps_intr_00 (1'd0), + .ps_intr_01 (1'd0), + .ps_intr_02 (1'd0), + .ps_intr_03 (1'd0), + .ps_intr_04 (1'd0), + .ps_intr_05 (1'd0), + .ps_intr_06 (1'd0), + .ps_intr_07 (1'd0), + .ps_intr_08 (1'd0), + .ps_intr_09 (1'd0), + .ps_intr_14 (1'd0), + .ps_intr_15 (1'd0), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_data_2_n (rx_data_n[2]), + .rx_data_2_p (rx_data_p[2]), + .rx_data_3_n (rx_data_n[3]), + .rx_data_3_p (rx_data_p[3]), + .rx_ref_clk_0 (rx_ref_clk), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (rx_sysref), + .spi0_csn (spi_csn), + .spi0_miso (spi_miso), + .spi0_mosi (spi_mosi), + .spi0_sclk (spi_clk), + .spi1_csn (), + .spi1_miso (1'd0), + .spi1_mosi (), + .spi1_sclk (), + .tx_data_0_n (tx_data_n[0]), + .tx_data_0_p (tx_data_p[0]), + .tx_data_1_n (tx_data_n[1]), + .tx_data_1_p (tx_data_p[1]), + .tx_data_2_n (tx_data_n[2]), + .tx_data_2_p (tx_data_p[2]), + .tx_data_3_n (tx_data_n[3]), + .tx_data_3_p (tx_data_p[3]), + .tx_ref_clk_0 (tx_ref_clk), + .tx_sync_0 (tx_sync), + .tx_sysref_0 (tx_sysref)); + +endmodule + +// *************************************************************************** +// ***************************************************************************