From ff2e1021827f8a4f19b3777ed9dad0e1c1cceb52 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 30 Sep 2014 10:46:27 +0200 Subject: [PATCH] axi_dmac: Add clock signal spec for m_axis/s_axis bus This silences warnings from the tools about having no clock assigned to the bus. Also fix the name of the TVALID signal. Signed-off-by: Lars-Peter Clausen --- library/axi_dmac/axi_dmac_ip.tcl | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/library/axi_dmac/axi_dmac_ip.tcl b/library/axi_dmac/axi_dmac_ip.tcl index 4bc9d5672..6307edf26 100644 --- a/library/axi_dmac/axi_dmac_ip.tcl +++ b/library/axi_dmac/axi_dmac_ip.tcl @@ -38,17 +38,17 @@ set_property physical_name {s_axi_aclk} [ipx::get_port_map CLK \ [ipx::get_bus_interface s_axi_signal_clock [ipx::current_core]]] adi_add_bus "s_axis" "axis" "slave" \ - [list {"s_axis_aclk" "ACLK"} \ - {"s_axis_ready" "TREADY"} \ - {"s_axis_valid" "VALID"} \ + [list {"s_axis_ready" "TREADY"} \ + {"s_axis_valid" "TVALID"} \ {"s_axis_data" "TDATA"} \ {"s_axis_user" "TUSER"} ] +adi_add_bus_clock "s_axis_aclk" "s_axis" adi_add_bus "m_axis" "axis" "master" \ - [list {"m_axis_aclk" "ACLK"} \ - {"m_axis_ready" "TREADY"} \ - {"m_axis_valid" "VALID"} \ + [list {"m_axis_ready" "TREADY"} \ + {"m_axis_valid" "TVALID"} \ {"m_axis_data" "TDATA"} ] +adi_add_bus_clock "m_axis_aclk" "m_axis" adi_set_bus_dependency "m_src_axi" "m_src_axi" \ "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE_SRC')) = 0)"