Import documentation from the IP library and wiki page.
Make the background of the clock images less opaque so it's easier to
read.
Don't split roles, even though are valid, are a nightmare to
regex-match, if necessary.
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
SPI Engine: create inverted CS mode
Add a CS Invert Mask instruction for selecting the polarity of
the Chip Select pins.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Rename "idle bus" to "bus available" per specification:
* Tune it to require < 1us.
Rename "IBI auto" to "IBI listen":
* Clarify that the controller is listening for IBI's:
* Explain that this field should be set.
* Fix for known IBI's DA with IBI disabled.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
This commit implements Cache Coherency through dedicated parameters.
The AxCACHE/AxPROT parameters are automatically set to the most commonly
used values unless otherwise specified. Their default values are:
AxCACHE = CACHE_COHERENT ? 4'b1111 : 4'b0011
AxPROT = CACHE_COHERENT ? 3'b010 : 3'b000
If Cache Coherency is enabled, the AxCACHE/AxPROT values can be changed
to support systems with different caching policies.
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
Unified the ad7606x_fmc project, where both the serial and the parallel interface are implemented.
---------
Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
1. Add intermediary data_src_select register to control output selection
between DMA and RAW. The switch RAW->DMA is not made until DMA has valid
data; the switch DMA->RAW is not made until overwrite_enable is 1
regardless of dac_valid.
2. When overwrite is enabled, set the intermediary DMA register data_r
to the RAW value.
This fixes an issue of the logic analizer that caused the last sample of a DMA
transfer to be visible at the next DMA transfer.
Signed-off-by: dumitruceclan <dumitru.ceclan@analog.com>
This change will fix the timing closure for designs where the external
clock is not a submultiple of the s_axi_clk.
Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
New features:
1. External sync force the phase align. The external sync was used to align
the phases of enabled pwms, but only after being armed by a
load_config signal toggle.
This feature lets the user decide between using load_config to
arm and wait for a neg-edge of sync or automatic phase align trigger
on the ext_sync neg-edge.
2. Force align. Lets the user chose between immediately stopping the
active pulses and realigning them, or waiting for all running pulse
periods end, before realigning.
3. Start at sync. When this feature is activated, the pulses will start immediately
after the trigger event. Otherwise, each pulse will start after a period
equal to the one for which it is set.
4. Use parameters to set the default status after reset of the
- soft reset
- start at sync
- force align
- ext sync align
Update regmap.
Fixes:
1. The polarity on disabled channels was staying high instead of low.
2. Fix 0 and 100 proc duty cycle configuration.
Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
Signed-off-by: Alin-Tudor Sferle <Alin-Tudor.Sferle@analog.com>
Intermittently DAC channel data is 0 after multiple new buffers.
Due to the low sampling rate and DMA flushing, it happens that the
transfer SM gets stuck in flushing mode right before the transmission
should start.
Another frequent issue happens when a new transmission is started.
A buffer must be pushed independently for each channel because of
separate DMAs.
After the first buffer is pushed the Linux driver deactivates the
start_sync flag. Not knowing if the other channel/buffer will be
active/pushed. The start_sync will be re-enabled with the second buffer.
The issue was that the SM of the first buffer went one step further
before the push if the second buffer,not being stopped by the
start_sync.
Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
Add I3C Controller IP with required I3C features support.
Uses IRQ based DAA.
Supports speeds at 100MHz clk: 12.50MHz, 6.25MHz, 3.12MHz, 1.56MHz
Basic IBI support with/without MDB.
Compatible with AMD Xilinx and Altera FPGAs.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
With the new make -jX support flock is used but shells out sometimes.
This assumes a bash like shell which isn't always the case. This fix
forces flock to use sh.
Signed-off-by: Travis F. Collins <travis.collins@analog.com>
Lattice tools give error for using blocking assignments at one side
and non blocking in the other.
Signed-off-by: Villyam <Vilmoscsaba.Jozsa@analog.com>
docs: Add JESD204 documentation in sphinx
Fixes several semantic issues from the original doc in wiki
Implicit path to library when the doc is hierarchically coherent with the
library.
Signed-off-by: Carlos Souza <carlos.souza@analog.com>
Co-authored-by: Jorge Marques <jorge.marques@analog.com>
Alin-Tudor Sferle
podgori
Iulia Moldovan
Jorge Marques
PopPaul2021
Jorge Marques
LBFFilho
Ionut Podgoreanu
AndreiGrozav
LIacob106
bluncan
PIoandan
dumitruceclan
IstvanZsSzekely
ladace
Villyam
Stanca Pop
caosjr