Commit Graph

7 Commits (main)

Author SHA1 Message Date
Jorge Marques 8e32f0e21d
docs: Intermediary for IP Cores import, user guide, regmap (#1321)
Use interref (doctools cross-repository) to link the docs guidelines
Add user guide pages, update IP references
Add axi_adc/dac, up_if, "Use ADI IPs", "Creating new IP",
Update AXI DMAC, JESD204, I3C Controller, SPI Engines
Minor fixes in the frameworks and register maps,
the latter following the discussed guidelines.
Update AXI terms to manager and subordinate.

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
2024-05-13 10:05:12 -03:00
Jorge Marques 940c3ccd35 docs: Add component diagram generator
Replaces Symbolator with custom component diagram generator for more
reliable diagrams.
It uses the IP-XACT file, if it is not found, a placeholder is added
instead.

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-12-13 10:38:29 -03:00
Jorge Marques c66cc5e79a
docs: links, drop part, fixups, codeowners
Drop part role, use generic adi instead for root adi domain links.
For future reference, the snipped used was:
find ./docs/projects -type f -exec sed -i 's/:part:/:adi:/g' {} \;
Drop Containerfile.
Add option to validate links status (e.g. 200, 404), intended mostly for CI
use to check if a page has disappeared from the internet.
Validate links uses coroutines to launch multiple tasks concurrently,
but do it in bundles to avoid being rate limited.
Fixup regmap styling.
Add imoldovan, jmarques, spop, lbarbosa as docs codeowners.
Remove branch field for links to the hdl repo.
Change git role to display full path.
Fixup ZedBoard link label, remove IP List, add SYSID_ROM dokuwiki link
in ad716_sdz project.

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-11-13 15:42:46 +00:00
Jorge Marques 468d02ea50 docs: update link roles, .gitignore
Update link roles to use the "text <link>" standard sphinx syntax.
Add __pycache__ and _build to .gitignore

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-09-27 14:36:34 -03:00
Jorge Marques cf056cf81c docs: add regmap directive
Automate table generation for register maps.
Based on tfcollins' vger python scripts.
There are docs/adi_regmap_*.txt with more than one regmap per file,
so the logic changed to allow that.
Using title tool as the unique identifier now.
It has a global option to set the default state (hidden or visible)
for the collpasible tables.
Also remove CSVs.

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-09-27 14:36:34 -03:00
Jorge Marques 83d2bf9603 docs: automate parameters and interfaces tables
Uses Vivado generated components.xml files.
If the file is not found/generated, there is a fallback method.
Also, define bibliography per project, not globally.

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-09-27 14:36:34 -03:00
Jorge Marques ef9c98f9b9 docs: Include sphinx documentation
The parameters directive allows to almost automatically generate the
parameters table.
It allows to add rich descriptions to the parameters, such as references,
while checking if they exist in the *_hw.tcl file a obtaining the types
and default values.
However, it cannot obtain parameters generated from a foreach loop yet,
making it incompatible with the axi_dmac_hw.tcl file for example.
This commit also joins the other extensions into a single adi_links
extension.

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-09-27 14:36:34 -03:00