Commit Graph

263 Commits (main)

Author SHA1 Message Date
Lars-Peter Clausen c372064302 Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
Istvan Csomortani 4744fca18e axi_ad9361: Bring up the tdd_enable bit
This line will be the selection bit of the GPIO/TDD_FSM mux for ENABLE/TXNRX control
2015-07-01 14:59:32 +03:00
Istvan Csomortani a497dcabb5 axi_ad9361: Bring up the tdd_enable bit
This line will be the selection bit of the GPIO/TDD_FSM mux for ENABLE/TXNRX control
2015-07-01 13:52:00 +03:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
Adrian Costina fcc185d769 Makefile: Updated makefiles
- removed up_drp_control, up_delay_control dependencies where not needed
- added axi_jesd_gt core in the library makefile
- fixed timing tcl dependency for altera projects
2015-06-25 14:59:34 +03:00
Istvan Csomortani 4b08df9ed6 ad9361/tdd: Fix generation of tx_valid_* signals
In FDD mode the tx_valid_* signals are generated inside the axi_ad9361_tx module, in function of
the selected dac data rate. In TDD mode, these signals are gated by the tdd_enable and tdd_tx_dp_en signals.
In other words, the tx_valid_* signals will be valid just when tdd_enable and tdd_tx_dp_en is active.
2015-06-08 16:23:32 +03:00
Istvan Csomortani c926daca3a ad9361/tdd: Fix generation of tx_valid_* signals
In FDD mode the tx_valid_* signals are generated inside the axi_ad9361_tx module, in function of
the selected dac data rate. In TDD mode, these signals are gated by the tdd_enable and tdd_tx_dp_en signals.
In other words, the tx_valid_* signals will be valid just when tdd_enable and tdd_tx_dp_en is active.
2015-06-08 16:22:21 +03:00
Rejeesh Kutty 6338dfd8b7 ad9361: ip defaults & rst output 2015-06-05 09:19:39 -04:00
Istvan Csomortani 2e877389b2 ad9361_tdd: Some naming and hierarchical changes 2015-06-04 18:09:49 +03:00
Istvan Csomortani 3b1ea7e528 axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch
598ece4c8d
2015-06-04 18:09:47 +03:00
Rejeesh Kutty e02273781f ad_rst- non lpm version 2015-06-04 10:53:12 -04:00
Rejeesh Kutty 91b0f70972 library: remove drp cntrl 2015-06-02 09:58:57 -04:00
Rejeesh Kutty 297e885981 library- drp moved to up-clock domain 2015-06-01 14:52:52 -04:00
Rejeesh Kutty 2bad47cf4f delay-cntrl: up-clk, direct access + tx 2015-05-18 14:28:20 -04:00
Adrian Costina c19749361d Makefiles: Updated makefiles to have as a result the programming file instead of the project file.
Also fixed altera projects dependencies
2015-05-18 17:22:46 +03:00
Istvan Csomortani a07d11c3e9 axi_ad9361_tdd: Define control bits for continuous receive/transmit 2015-05-14 17:21:32 +03:00
Istvan Csomortani 7c9bc40c75 axi_ad9361&TDD: Update TDD
+ Delete unnecessary registers
+ Add the module ad_addsub.v to resolve additions and subtractions inside TDD control
+ Redefine the burst logic
+ Redesign the control signal generations
+ Note: This patch fix the TDD related timing violations
2015-05-13 14:03:01 +03:00
Rejeesh Kutty 4553de3ffa ad9361- align hold 2015-05-11 11:55:01 -04:00
Istvan Csomortani 2e7135c3c2 axi_ad9361_tdd: Initial commit.
Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 12:20:44 +03:00
Adrian Costina 14e23b106c axi_ad9361: changed device interface module for Altera to have the same inputs as the one for Xilinx 2015-05-08 17:43:10 +03:00
Rejeesh Kutty 12ed393d39 ad9361- framing modifications 2015-05-07 15:13:18 -04:00
Rejeesh Kutty a68539edf1 ad9361- framing modifications 2015-05-07 15:13:17 -04:00
Rejeesh Kutty 176a4a4b76 ad9361: add ddr-edgesel 2015-05-06 16:58:50 -04:00
Rejeesh Kutty a8534a9c02 ad9361: add ddr-edgesel 2015-05-06 16:58:49 -04:00
Rejeesh Kutty 32f7e98afd ad9361: add ddr-edgesel 2015-05-06 16:58:47 -04:00
Adrian Costina a61a195e3f Makefiles: Updated makefiles to add the new constraints as dependecies 2015-04-23 11:16:39 +03:00
Lars-Peter Clausen 988bf60747 axi_ad9361: Add ASYNC_REG properties to CDC regs and add missing -datapath_only
Set the ASYNC_REG property on the bit synchronizer CDC control regs. This
hint to Vivado that the registers are used for CDC purposes.

Also use -datapath_only for the set_max_delay constraints on the CDC data
path to remove the hold time requirement.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-21 10:15:02 +02:00
Lars-Peter Clausen e3b834ea02 axi_ad9361: Add CDC constraints
Add proper constraints for all the CDC synchronizer paths to the axi_ad9361
core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 20:12:06 +02:00
Adrian Costina dc2b37bd0c Makefile: Added top level Makefile. Modified behavior of clean and clean-all
Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.

The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
2015-04-17 17:22:38 +03:00
Adrian Costina 374f82e7de makefiles: The clean command for library won't remove the xml files, except for component.xml.
Updated also the dmac dependencies
2015-04-16 11:53:27 +03:00
Rejeesh Kutty 5f8e9a74ea makefile: updated 2015-04-07 16:32:01 -04:00
Adrian Costina f79a152958 Makefiles: updated all makefiles adding clean functionality 2015-04-03 11:57:54 +03:00
Rejeesh Kutty 5b18d12c23 makefile: added 2015-04-01 16:27:39 -04:00
Rejeesh Kutty ee0912eb6a ad9361: make 2t2r external for mw 2015-01-05 10:54:23 -05:00
Adrian Costina e086f5eb9f axi_ad9361: Updated core with the new up_adc_common register set 2014-10-27 19:26:40 +02:00
Rejeesh Kutty de33722470 up/constr: independent read/write and local constraints 2014-10-02 14:35:59 -04:00
Lars-Peter Clausen 3162540b03 axi_ad9361: Remove the Altera toplevel wrapper
By setting the AXI controler interface type from axi4 to axi4lite we can use
the normal toplevel file with only a simple modification to add the awprot
and arprot signals.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:29:13 +02:00
Lars-Peter Clausen 41cc92ef49 Remove BASEADDR/HIGHADDR parameters
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
Lars-Peter Clausen a4b9b1254a axi_ad9361/axi_dmac: Fix altrea AXI wrapper rid/wid handling
We must make sure that the response ID is the same as the request ID when we
accepted the request. Otherwise we might respond with the wrong ID and the
system will lockup.

Also set rlast to 1 instead of 0.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-09 15:05:06 +02:00
Lars-Peter Clausen 50faf0c53a Remove executable flags from non-exectuable files 2014-09-09 15:05:06 +02:00
Rejeesh Kutty 59759a8ab3 c5soc: working hdl version 2014-07-24 20:51:41 -04:00
Rejeesh Kutty 6346017763 c5soc: changed to alt_lvds - 250M is too high for cyclone v 2014-07-24 20:51:40 -04:00
Rejeesh Kutty c0e31aa6c2 daq2: latest hardware 2014-07-21 09:06:57 -04:00
Rejeesh Kutty 2955b9db78 fifo2s: flush if no request, c5soc: 14.0 2014-07-15 16:25:33 -04:00
Adrian Costina 39ac29bb01 AD9361: Altera, modified address width so that all registers are accessible
Modified qsys project with the new address span
2014-07-08 10:41:51 +03:00
Rejeesh Kutty a388ccab0a fmcomms2/c5soc: initial checkin 2014-07-02 14:56:00 -04:00
Rejeesh Kutty b6052773b7 added adc/dac gpio registers 2014-06-27 14:45:58 -04:00
Rejeesh Kutty 10a7804e14 ad9361: altera wrapper updates 2014-06-25 15:26:06 -04:00
Rejeesh Kutty 985ace533e ad9361: remove unused modules 2014-06-24 14:26:40 -04:00
Rejeesh Kutty e650253013 library: register map changes and for mathworks 2014-06-24 14:22:05 -04:00
Adrian Costina bef6a9c32c axi_ad9361: Split dma data into individual channels for both ADC and DAC 2014-06-07 17:15:31 +03:00
Rejeesh Kutty 5b5bca400f ad9361: added adc loopback 2014-05-27 14:47:59 -04:00
Rejeesh Kutty 842cd98b61 ad9361: adc loopback option 2014-05-27 12:15:02 -04:00
Rejeesh Kutty 3aed3ba71c axi_ad9361: fmcomms5 changes 2014-05-19 12:41:12 -04:00
Rejeesh Kutty a007add714 iqcorrection: missing input signals fix 2014-05-09 11:17:50 -04:00
Rejeesh Kutty 1d50489870 ad9361: ml605 updates 2014-05-05 11:03:57 -04:00
ATofan 570ec26798 FMCOMMS2: Added sync option 2014-04-11 18:14:48 +03:00
ATofan 99ef34936f Merge branch 'master' of https://github.com/analogdevicesinc/hdl 2014-04-11 18:14:08 +03:00
U-ANALOG\ACostina c73390b6c9 axi_ad9361: Intermediary check in for altera porting
This is work in progress. It will not work as it is
2014-04-11 17:40:34 +03:00
ATofan 5aac9d7288 FMCOMMS2 added sync option
Added signals to allow synchronisation of multiple AD9361.
2014-04-10 10:46:42 +03:00
Rejeesh Kutty 25f416e46f dds output is reset if disabled 2014-03-31 10:01:49 -04:00
Rejeesh Kutty ad491e92ab changed pcore version and made it local (top shouldn't override) 2014-03-14 12:02:16 -04:00
Rejeesh Kutty 580808e146 axi_ad9361: added 2014-03-11 20:01:55 -04:00