Commit Graph

23 Commits (main)

Author SHA1 Message Date
Iulia Moldovan c9a7d4d927 Add copyright and license to .tcl, .ttcl files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 15:22:26 +03:00
Iacob_Liviu 482f0489a3 scripts: Merge adi_env.tcl into a single file
Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
LIacob106 076e81a17c library: Add link to wiki for IPs 2021-10-25 10:44:53 +03:00
Istvan Csomortani 363494ab9c library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
AndreiGrozav 23841478c6 Remove library/scripts/common_bd.tcl
Remove the script from the file list of the IPs that previously used it.
axi_clkgen: Add independent adi_auto_assign_device_spec proc
2019-04-09 16:07:14 +03:00
AndreiGrozav 66823682b6 Add FPGA info parameters flow
Common basic steps:
- Include/create infrastructure:

   * Intel:
       - require quartus::device package
       - set_module_property VALIDATION_CALLBACK info_param_validate

   * Xilinx
       - add bd.tcl, containing init{} procedure. The init procedure will be
         called when the IP will be instantiated into the block design.
       - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl
       - create GUI files

- add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params)
- add/propagate the info parameters through the IP verilog files

axi_clkgen
util_adxcvr
ad_ip_jesd204_tpl_adc
ad_ip_jesd204_tpl_dac
axi_ad5766
axi_ad6676
axi_ad9122
axi_ad9144
axi_ad9152
axi_ad9162
axi_ad9250
axi_ad9265
axi_ad9680
axi_ad9361
axi_ad9371
axi_adrv9009
axi_ad9739a
axi_ad9434
axi_ad9467
axi_ad9684
axi_ad9963
axi_ad9625
axi_ad9671
axi_hdmi_tx
axi_fmcadc5_sync
2019-03-30 11:26:11 +02:00
Istvan Csomortani e092149cbc adi_ip: Use 'associate_bus_interface' command to setup the clock and reset for s_axi 2018-08-06 10:14:48 +03:00
Lars-Peter Clausen 5b58fb67f0 library: Remove empty constraint files
Most of the cores are fully covered by the generic constraint files. When
the constraints where moved from the core specific to the generic
constraint files some empty core constraints files where left around. These
don't do anything, so remove them.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
AndreiGrozav 74ad0d1e46 library: Update
Older Vivado versions where incorrectly inferring interfaces
-axi_ad9361
-axi_ad9963
-axi_adc_decimate
-axi_adc_trigger
-axi_clkgen
-axi_dac_interpolate
-axi_hdmi_tx
-axi_i2s_adi
-axi_logic_analyzer
-spi_engine
2017-11-15 17:08:45 +02:00
Lars-Peter Clausen af913863d4 axi_clkgen: Infer CLKIN period
Instead of having to manually specify the input clock period infer the
values from the block design. This means that less configuration parameters
need to be changed if the clock input frequency changes.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 20:36:15 +02:00
Lars-Peter Clausen fdedc9568c axi_clkgen: Add interface definitions for clock inputs/outputs
Add interface definition for the input and output clocks. This will allow
the tools to recognize them as clocks and enable things like clock
frequency propagation.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 19:55:57 +02:00
Lars-Peter Clausen 15ce8cc356 axi_clkgen: Add enable parameters for secondary clock inputs/outputs
The secondary clock inputs and outputs of the axi_clkgen are rarely used.
Add enable parameters that need to be explicitly set before they are
available. This allows to hide the secondary clock pins when they are not
used in the block design.

There are currently no projects which use the secondary clock inputs or
outputs so there is no need to set these new parameters anywhere.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-20 19:55:57 +02:00
Istvan Csomortani c1bdfca4c3 library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
Istvan Csomortani df36902713 lib_refactoring: Fix path of the IO macros 2016-08-08 15:07:19 +03:00
Adrian Costina e7fd964874 axi_clkgen: Added a second input clock option 2015-11-06 17:55:29 +02:00
Istvan Csomortani 7b858bc5ad Revert commit 6b99ce
Revert 6b99ce2482
2015-08-26 13:48:28 +03:00
Istvan Csomortani da315eb6c0 library: 2015.2 updates
IPI bus interface names have changed in this new release.
2015-08-25 09:13:24 +03:00
Adrian Costina 6b99ce2482 library: Added common constraints for all cores. Commented code that needs to be updated to 2015.2 2015-08-20 18:17:38 +03:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
Rejeesh Kutty c6ebab7393 library- drp moved to up clock 2015-06-01 13:39:26 -04:00
Adrian Costina cc7d9f9d54 axi_clkgen: Added CDC and reset constraints 2015-04-23 10:44:37 +03:00
Rejeesh Kutty 63bd2b870a pointers to directories 2014-02-28 16:58:30 -05:00
Rejeesh Kutty f7c9368abc initial checkin 2014-02-28 14:26:22 -05:00