SPI Engine: create inverted CS mode
Add a CS Invert Mask instruction for selecting the polarity of
the Chip Select pins.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Revert AXI bus signals back to upper case on SPI Engine Offload IP,
changed on e2ca5a991a.
Fixup signals from sd*_data_* to sd*_* for spi_engine_ctrl interface.
Non-breaking mistake, but added warnings to the IP.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
* SPI Engine: Add registers for Offload memory and FIFO sizes
Adds registers at dword 0x04 and 0x05, respectively allowing software
to get the sizes of the Offload Module memories (command and sdo) or
the sizes of the FIFOs on the AXI regmap.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Use tcl script instead of static xmls for the interface.
Easier to maintain and are not gitignored.
Rename spi_master to spi_engine because every interface should be
prefixed by the IP name; in this case, spi_engine.
Also, remove interface/*.sv files on make clean and git ignore them.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
* SPI Engine: fix early sdi data clear
In case an SPI read was immediately followed by a cs assert, the sdi
register was being cleared one cycle too soon, so that the data being
passed on was always 'b0.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Previous level-based trigger could cause issues in some low
sampling rate setups. This commit changes it to edge-based.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Set validation ranges for DATA_WIDTH and NUM_OF_CS for the expected
min/max values in the verilog source code.
Also, fix swapped description for CPHA in the documentation.
Signed-off-by: Carlos Oliveira <caosjr8@gmail.com>
Fixed wrong behaviour on chip select instruction:
- previously, a sleep time happened before the chip select change
- the intended behaviour was for another sleep time, of equal amount, to happen after the chip select change as well
- additionally, the counter logic implementation was creating an additional factor of 2 on the sleep time
All of the above points were fixed. The changes introduced also fix another issue where the sleep instruction was likewise happening with a duration larger than intended by a factor of 2
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
The SPI Engine cores were named directly inside the script and this
would mean that for multiple SPI Engine instances IPs with the same
name would appear. These updates will introduce the hierarchy name
into the name given to the cores and will therefore allow for
multiple instances of SPI Engine to be added to the same Xilinx
project.
Projects which use spi_engine.tcl will be updated to account for
these changes.
* Added header license for the files that didn't have
* Modified parentheses
* Removed extra spaces at the end of lines
* Fixed parameters list to be each parameter on its line
* Deleted lines after endmodule and consecutive empty lines
* Fixed indentation
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
The 4 parameters are added to facilitate transmiting project
related information to the software. They act as read-only
memory which is written in Vivado when the project builds.
Set 31 to SDI FIFO's almost full threshold
In case of multiple SDI (MISO) lanes, the samples arrives in a parallel
fashion. For example in case of 4 MISO line, at the first latching clock
edge 4 bits of a sample will be saved, one bit into each shift register.
The data reorder module reconstruct the incoming samples from the AXI
stream of the offload module.
There are boards (e.g. AD4630-24) which take the SCLK and echo back to
the FPGA through a level shifter - doing this removes the effect of
round-trip timing delays from the level shifter. This is commonly done
whenever isolators are used since they are very slow.
By setting the ECHO_SCLK parameter to 1, the IP will use the incoming
echoed SCLK clock to latch the SDI line(s). The sdi_data_valid is still
synchronous to the SPI clock, and it's generated after the last valid
SDI latch.
The designer's responsibility is to time the SDI shift registers in order to
respect the design requirements.
This reverts commit 0402ce85e4
and reverts commit 164aa97ec3.
The trigger pulse generation must be handled outside of the
SPI Engine framework.
It is recommanded to be done in system level using a PWM
generator or an external signal.
Define both AXI4 Memory Mapped and microprocessor interface for the
reigster map, then activate/deactive one of it in fucntion of the memory
interface type parameter.
Define the missing status_sync interface, which should be connected to
the offload.
Context switching with a parameter is not a good idea. The simulator
may evaluate both branch of the IF statement, even though the inactive
branch may not be valid.
Use if..generate to make the code more robust for both synthesizers and
simulators.
Fix the *_ip.tcl scripts for axi_spi_engine and spi_engine_offload
module.
In case of a bool parameters the value_format and value properties must
be set for both user and hdl paramters. If not, in the generated verilog
code the tool will use "true" or "false" strings, instead of 0 or 1.
LBFFilho
Jorge Marques
Iulia Moldovan
caosjr
Sergiu Arpadi
laurent-19
Iacob_Liviu
Nick Pillitteri
Istvan Csomortani
Laszlo Nagy
Adrian Costina
stefan.raus