Commit Graph

8 Commits (main)

Author SHA1 Message Date
Jorge Marques f2a00c8528
spi_engine: Revert Offload AXI signals, ctrl fixup (#1288)
Revert AXI bus signals back to upper case on SPI Engine Offload IP,
changed on e2ca5a991a.
Fixup signals from sd*_data_* to sd*_* for spi_engine_ctrl interface.
Non-breaking mistake, but added warnings to the IP.

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2024-03-14 11:45:33 -03:00
Jorge Marques e2ca5a991a
spi_engine: Create interface_ip.tcl (#1251)
Use tcl script instead of static xmls for the interface.
Easier to maintain and are not gitignored.
Rename spi_master to spi_engine because every interface should be
prefixed by the IP name; in this case, spi_engine.
Also, remove interface/*.sv files on make clean and git ignore them.

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2024-02-28 10:31:46 -03:00
Istvan Csomortani 4d54c7e2d6 spi_engine_execution: Merge the SDI lines into one vector
This modification will help to support multiple SPI engine
execution setups (e.g. different NUM_OF_SDI) for the same project.
2020-05-19 09:28:02 +03:00
Istvan Csomortani 7b3d52436a spi_engine: Forward the offload's sync_id to the register map
Forward the offload's sync_id to the register map, by defining an
additional AXI stream interface between the offload and axi_spi_engine.
The last sync_id of the offload module can read out from the
register 0x00C4. It also can generate and interrupt if the irq mask is
configured accordingly.
2020-05-19 09:27:28 +03:00
Istvan Csomortani 269ae40f66 spi_engine: Add support for 8 SDI lines 2018-04-11 15:09:54 +03:00
Istvan Csomortani ed20d00f77 spi_engine: Add support for max 4 SDI lines 2017-08-04 14:49:17 +03:00
Istvan Csomortani 825d46259b interface: Update spi_engine_offload_ctrl definition
Because of the new AD5766 offload module, SDO lines are
defined as 'optional'.
2017-04-27 11:19:22 +03:00
Lars-Peter Clausen e6b58e8a20 Add SPI Engine framework
SPI Engine is a highly flexible and powerful SPI controller framework. It
consist out of multiple sub-modules which communicate over well defined
interfaces. This allows a high degree of flexibility and re-usability while
at the same time staying highly customizable and easily extensible.

Currently included are four components:
	* SPI Engine execution module: The excution module is responsible for
	  handling the low-level physical interface SPI logic.
	* SPI Engine AXI interface module: The AXI interface module allows
	  memory mapped acccess to a SPI bus control stream and can be used to
	  implement a software driver that controls the SPI bus.
	* SPI Engine offload module: The offload module allows to store a
	  predefined SPI Engine command and data stream which will be send out
	  when a external trigger signal is asserted.
	* SPI Engine interconnect module: The interconnect module allows to
	  combine multiple control streams into a single stream giving multiple
	  control modules access to a execution module.

For more information see: http://wiki.analog.com/resources/fpga/peripherals/spi_engine

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00