* Value 24 was wrongfully set for parameter LENGTH_WIDTH, because
it is not among the valid values, which are 28, 29, ..., 34. Set '28'
to be the default value
* Vivado Tcl somehow didn't accept the old expression set for
calculating the HBM_SEGMENTS_PER_MASTER parameter, so it was changed
accordingly to work. Dropped "expr", ".0" and "int ()" parsing and now
it works
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
* Added header license for the files that didn't have
* Modified parentheses
* Removed extra spaces at the end of lines
* Fixed parameters list to be each parameter on its line
* Deleted lines after endmodule and consecutive empty lines
* Fixed indentation
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
This IP serves as storage interfacing element for external memories like
HBM or DDR4 which have AXI3 or AXI4 data interfaces.
The core leverages the axi_dmac as building blocks by merging an array of
simplex DMA channels into duplex AXI channels. The core will split the
incoming data from the source AXIS interface to multiple AXI channels,
and in the read phase will merge the multiple AXI channels into a single
AXIS destination interface.
The number of duplex channels is set by syntheses parameter and must be
set with the ratio of AXIS and AXI3/4 interface.
Underflow or Overflow conditions are reported back to the data offload
through the control/status interface.
In case multiple AXI channels are used the source and destination AXIS
interfaces widths must match.
Iulia Moldovan
Ionut Podgoreanu
Iacob_Liviu
Laszlo Nagy