Commit Graph

61 Commits (main)

Author SHA1 Message Date
Iulia Moldovan 68461110aa Replace link in license header from master to main
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2024-01-16 16:48:45 +02:00
Iulia Moldovan c9a7d4d927 Add copyright and license to .tcl, .ttcl files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 15:22:26 +03:00
Iulia Moldovan 1cac2d82e1 Add copyright and license to .xdc files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 11:03:02 +03:00
Iulia Moldovan 28c06d505f Add/edit copyright and license for .v, .sv files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-11 15:17:41 +03:00
Iulia Moldovan db94628cc6 library & projects: Update Makefiles
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-01-27 11:54:05 +02:00
Bogdan Luncan 72313df81f Updated the makefiles to build the projects in subdirectories based on the build parameters.
Running 'make' will build the default project directly in the project folder (like it did before)
Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory.
Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory.
Running 'make clean' will clean the default project only.
Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build.
Running 'make clean-all' will delete all the built configurations and libraries.

Note that the 'JESD' and 'LANE' words from the parameter names are stripped.

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
2022-11-14 09:38:42 +02:00
Iacob_Liviu 482f0489a3 scripts: Merge adi_env.tcl into a single file
Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
Iulia Moldovan 961ebe0cc2 projects: Update .v files according to guideline
Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
Laszlo Nagy 97b92565b2 Makefile: Replace util_fifo2axi_bridge with util_hbm 2022-04-28 14:31:32 +03:00
Laszlo Nagy 0e55583a63 daq2: Do not set AXI address width for DO
Address size and memory ranges are automatically computed by the
external storage interfacing IP (util_hbm) based on the storage size and
base address so this parameter is redundant.
2022-04-28 14:31:32 +03:00
Dan Hotoleanu 530aca9754 daq2: Parameterize JESD204 configuration values
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-20 12:54:03 +02:00
LIacob106 58c1d2e3b2 projects: fixed xcvr clocks that generated critical warning 2021-11-09 12:40:14 +02:00
LIacob106 d4126739b4 projects: remove hardcoded div_clk from xcvr 2021-10-27 12:11:22 +03:00
Mihaita Nagy ff090b60ef daq2/zcu102: Fix the ad9144 data offload to use internal BRAM 2021-10-15 15:03:22 +03:00
Laszlo Nagy 51b643b978 Makefile: Fix misc makefiles from projects and library 2021-10-05 14:24:48 +03:00
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
Sergiu Arpadi 6f2f2b8626 makefile: Regenerate make files 2021-01-20 01:02:56 +02:00
sergiu arpadi acbbd4636a sysid: Upgrade framework, header/ip are now at 2/1.1.a
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
Adrian Costina 9093a8c428 library: Move ad_iobuf to the common library, as it's not Xilinx specific
Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
Istvan Csomortani 37254358dd makefile: Regenerate make files 2020-10-20 12:51:10 +03:00
Sergiu Arpadi d8ab27b2af sysid: Remove cstring init string 2020-09-30 19:12:24 +03:00
Istvan Csomortani aa5fdf903e Makefile: Update makefiles 2019-08-26 16:58:01 +03:00
Arpadi 0680e44330 system_id: deployed ip 2019-08-06 16:53:11 +03:00
Istvan Csomortani a589753d92 project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 43725429ac adi_project: Rename the process adi_project_xilinx to adi_project 2019-06-29 06:53:51 +03:00
AndreiGrozav d894c30c2d Remove deprecated/unused parameters
adrv9009
adrv9371x
arradio
daq2
daq3
fmcomms2
fmcomms5
2019-03-30 11:26:11 +02:00
Laszlo Nagy 9b048f1a0e daq2: update adcfifo/dacfifo 2019-01-23 14:45:45 +02:00
Lars-Peter Clausen b9958cac00 daq2: Use new pack/unpack infrastructure
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Laszlo Nagy 4ce153e6e1 all/system_top.v: loopback gpio lines
Create loopback on unused GPIO lines since Linux may rely on it.
2018-10-04 14:19:37 +03:00
Istvan Csomortani 2293374307 adc|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs
The affected projects are:
  - FMCADC2/VC707 - 16Mb
  - FMCADC5/VC707 - 16Mb
  - DAQ2/ZC706  - ADC@1GB and DAC@8Mb
  - DAQ2/KC705  - ADC@4Mb and DAC@4Mb
  - DAQ2/VC707  - ADC@8Mb and DAC@8Mb
  - DAQ2/KCU105 - ADC@4Mb and DAC@4Mb
  - DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb
  - DAQ3/ZC706  - ADC@1GB and DAC@8Mb
  - DAQ3/KCU105 - ADC@4Mb and DAC@4Mb
  - DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb
  - ADRV9371x/KCU105 - DAC@8Mb
  - ADRV9371x/ZCU102 - DAC@16Mb
2018-08-21 11:44:05 +03:00
Laszlo Nagy 31318cf311 all/system_top.v: drive unused gpio inputs with zero
The loopback on the unused gpio inputs consumes routing resources
while does not gives any value for the software.

Connect these lines to zero instead.
2018-08-10 17:00:11 +03:00
Laszlo Nagy fa7c85a9eb all: Drive undriven input signals, complete interface
- connect unused GPIO inputs to loopback
- connect unconnected inputs to zero
- complete interface for system_wrapper instantiated in all system_top

fixes incomplet portlist WARNING [Synth 8-350]
fixes undriven inputs WARNING [Synth 8-3295]

The change excludes the generated system.v and Xilinx files.
2018-08-10 17:00:11 +03:00
AndreiGrozav ebae8bf8c1 Remove interrupts from system_top for all xilinx projects
- remove interrupts from system_top
- for all suported carriers:
	- remove all interrupt bd pins
	- connect to GND all initial unconnected interrupt pins
- update ad_cpu_interrupt procedure to disconnect a interrupt from GND
before connectiong it to another pin.
2018-08-10 10:10:58 +03:00
Lars-Peter Clausen 377247a434 Regenerate project Makefiles using the new shared Makefile includes
This reduces the amount of boilerplate code that is present in these
Makefiles by a lot.

It also makes it possible to update the Makefile rules in future without
having to re-generate all the Makefiles.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Istvan Csomortani 425e803364 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
AndreiGrozav dd8d6f90ee zcu102:all_projects: Delete required version tcl variable
All the ZCU102 projects will use the default tool version.
This setup was a temporary exception for hdl_2017_r1 release.
2018-04-11 15:09:54 +03:00
Istvan Csomortani a740b6012f Make: Use $(MAKE) for recursive make commands
This commit should resolve the issue #64.

Recursive make commands should always use the variable MAKE, not the explicit
command name ‘make’.
2018-03-07 07:40:19 +00:00
AndreiGrozav ec324652aa daq2_zcu102: Fix typo 2017-11-20 18:02:22 +02:00
AndreiGrozav a23c640180 Require Vivado 2017.2.1 for all zcu102 projects 2017-11-20 15:36:51 +00:00
AndreiGrozav 76cec098d1 daq2, daq3: zcu102: Update constraints
Differential pins ignored by the tool
2017-11-15 10:47:01 +02:00
Lars-Peter Clausen 8fa50a0cb4 daq2: Set correct transceiver type for UltraScale projects
Make sure that the axi_adxcvr instances are configured with the same
transceiver type as the util_adxcvr.

This is necessary for software to be able to detect the transceiver type
and support dynamic reconfiguration.

It is also necessary for correct eye scan support in the axi_adxcvr block.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-11-14 14:31:03 +01:00
AndreiGrozav 514e54287c zcu102 constraints description/cosmetic updates 2017-11-08 10:38:39 +02:00
Michael Hennerich 5b9e4cb692 daq2/zcu102: Pin Swap for ZCU102 Rev1.0
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2017-10-30 11:09:20 +00:00
Lars-Peter Clausen 0360e8587e Connect JESD204 interrupts
Connect the ADI JESD204 link layer peripheral interrupt signals in all
projects.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-05 14:37:50 +02:00
Adrian Costina b7ca17f02b scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
Istvan Csomortani 50cdb6db67 Merge branch 'jesd204' into dev 2017-05-31 20:44:32 +03:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Lars-Peter Clausen 0ec92d3153 daq2: Convert to ADI JESD204
Convert the DAQ2 project to the ADI JESD204 link layer cores. The change is
very straight forward, but a matching change on the software side is
required.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00