1cac2d82e1
Add copyright and license to .xdc files
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 11:03:02 +03:00
a4a9d0a19d
fmcomms11/zc706: Relax core clock timing to 250MHz/125MHz
2019-06-10 11:23:41 +03:00
119fd0915a
fmcomms11: Make the lane remapping after the link layer
2019-06-10 11:23:41 +03:00
eba1975144
fmcomms11: Initial commit
2019-05-16 13:26:58 +03:00
43496cf80a
fmcomms11: Move project to a feature branch
2018-04-13 18:22:15 +03:00
502989c25f
jesd_rst_gen:constraints: Remove invalid false path definitions
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The constraint where added to remove timing problems on the reset path.
The constraint paths do not match anymore. The resets are used in a synchronous
way so we don't need the timing exceptions anyway.
Projects affected by this change:
- daq3
- adrv9739
- ad6676evb
- fmcadc5
- daq2/kcu105
- fmcadc2
- adrv9371x
- fmcomms11/zc706
- fmcjesdadc1
2018-04-11 15:09:54 +03:00
bf3ba4426c
fmcomms11: Update the SPI IO definitions
2018-01-29 18:48:31 +02:00
55b4603e60
fmcomms11: Update the clock tree
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- one single reference clock for both rx and tx channels
- delete the SYSREF inputs
- update the IO location of the usr_clk
2018-01-29 18:44:15 +02:00
ff562e7165
fmcomms11: Delete trailing whitespaces
2018-01-29 17:46:54 +02:00
b85a282748
fmcomms11- lane swap
2016-11-16 10:26:47 -05:00
7fd9280cbf
fmcomms11- xcvr updates
2016-09-26 15:19:05 -04:00
d6243f3d01
update in fmcomms11 tcl and clock constrains
2016-07-18 09:04:13 -04:00
1746701d45
fmcomms11- updates
2016-06-10 14:20:43 -04:00
8f00760c13
fmcomms11- initial commit
2016-06-10 14:20:43 -04:00
Iulia Moldovan
Istvan Csomortani
AndreiGrozav
Rejeesh Kutty
Shrutika Redkar