Running 'make' will build the default project directly in the project folder (like it did before)
Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory.
Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory.
Running 'make clean' will clean the default project only.
Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build.
Running 'make clean-all' will delete all the built configurations and libraries.
Note that the 'JESD' and 'LANE' words from the parameter names are stripped.
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
In ad_xcvrcon procedure from adi_board, phy_en_char_align must be connected only when 8B10B encoding is used,
otherwise this signal does not exists in the JESD ip and will cause an error.
Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
Expose JESD parameters to make.
Add FMCOMMS8 parameter.
Changed the name of the observation path to match the rest of the repo.
Replace old dac_data_width formula with a more generic one.
* Update xdc to use diff_term true instead of diff_term 1
* Generated xdc using adi_fmc_constr_generator.tcl
* Make CSN to be inactive
* Cosmetic changes also
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
Using the script:
- make sure that the eval board in use has a common fmc connection file.
if you created a new one, it should be saved as &project_name_fmc.txt inside
&project_name/common
- open a tcl terminal, either inside or outside the project
- make sure your current directory is &hdl_repo/projects/&project_name/&carrier
- source the script found at &hdl_repo/project/scripts/fmc_constr_generator.tcl
- call gen_fmc_constr $parameter_1 $parameter_2:
- in case of only one fmc port on the carrier call without any parameters
- if there are two fmc ports on the carrier and you want to use only one,
the first parameter should contain an indication (fmc_lpc/hpc, fmc0/1, etc.)
- if there are two fmc ports on the carrier and you want to use both, then
both parameters should contain an indication
- the constraints file will be generated in the current directory
Signed-off-by: AndrDragomir <andrei.dragomir@analog.com>
For some newer versions of git where by default color.ui=always.
The colored string captured can result in some special characters
(ASCI escape codes for coloring the terminal output) before and after the string.
e.g:
$ git branch > test.txt
$ vim test.txt
"
* ^[[32mmaster^[[m
dev_new_device^[[m"
The above escape codes will mess up a terminals color scheme when this
information is read from sysid and displayed on a terminal.
Use --no-color flag to fix this issue.
New version of Quartus Standard for de10nano and sockit was changed
to 21.1.
Signed-off-by: Liviu Adace <liviu.adace@analog.com>
Signed-off-by: Liviu Adace <liviu.adace@analog.com>
New version of Quartus Pro for A10SOC, A10GX and S10SOC was changed
to 21.4. Is known that some projects will not build anymore due to
timming violations.
* library/common: Ad adc_status_header, adc_crc_err and adc_crc_enable.
* library/axi_ad777x: Initial commit for Xilinx and Intel
* projects/ad777x_ardz: Initial commit for ZedBoard and DE10Nano
Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
- Added an utility buffer in order to generate the 50Mhz DRP clock.
- 'addn_ui_clockout4' will be used to generate the higher frequency 'sys_mb' clock for Microblaze.
Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
Increased the Microblaze performance for the VCU118 carrier:
- Increased the size of Instruction Cache and Data Cache to 64kB
Increased the Microblaze clock frequency:
- Using the DDR4 Controller to generate a new sys_mb_clk of 214 MHz to drive all the Microblaze interfaces at higher frequencies
Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
Created a virtual clock to constrain cnv_en.
Given that the cnv_en should be asserted only once per 8 clock
cycles and only the rise edge is of interest, we can constrain
the path as multicycle path.
Because the inferface signals which pass through the eval board's
Arduino connector are connected to level shifters the design
will not work at the maximum clk frequency of 48MHz. The maximum
tested frequency is 24MHz.
Address size and memory ranges are automatically computed by the
external storage interfacing IP (util_hbm) based on the storage size and
base address so this parameter is redundant.
The internal bypass FIFO has poor timing performance,
when using HBM data can be passed always through the external memory
without storage length constraints, so no need for the internal bypass FIFO.
Make the storage type over writable so it can be set specifically
to carriers.
Address width of external memory AXI master is calculated in the
interfacing core (util_hbm) so that parameters is removed.
The HBM interfacing core requires a 450MHz clock, make it part of the
base design.
The clock can't be obtained from the DDR controller so a clock wizard is
used instead.
Deprecate unused parameters.
Change to MEM_SIZE_LOG2, to support only power of 2 storage sizes for
now. However in the future we might want to add support for non pow2
sizes so register map is not changed.
Change transfer length to -1 value to spare logic.
Change FIFO interface to AXIS to have backpressure, this allows the
implementation of data movement logic in the storage unit and let the
FSM handle high level control an synchronization and control the storage
unit through a control interface.
Refactor FSM to have preparation states where slow storages can be
configured and started ahead of the data handling.
Make bypasss FIFO optional since in some cases causes timing failures
due the missing output register of the memory. This can be targeted in
a later commit.
Hook up underflow/overflow to regmap useful in case of external memory
where rate drops due misconfiguration can be detected.
Cleanup for verilator.
Scripting:
Add HBM and DDR external memory support using util_hbm IP
Replace asym_block_ram with util_do_ram IP
Remove contraints related to quartus version so that
cn0506_mii and cn0506_rgmii on arria10 to be built
with default quartus version.
Signed-off-by: stefan.raus <stefan.raus@analog.com>
There are no external termination resistors on the VCU118 and VCU128 for
the SGMII clock lines.
The board files of the VCU118 enables them, but this was not reflected in the
constraint files.
For VCU128 the clocking is similar, even if diff terms are not set in the
board files we should have a consistent approach with the VCU118.
There are no external termination resistors on the VCU118 for the SGMII
clock lines. The board files enables them, but this was not reflected in the
constraint files.
In some cases (GTX2) the transceiver may gate the out_clk when it is in
reset or misconfigured. This will stop the clock generators from getting
a clock prior removing the reset of the XCVR. The XCVR has a requirement
of running user clock while removing the reset. The correct sequence must be :
Enable device clocks (user clock)
Remove the reset from the XCVR
In some cases (GTX2) the transceiver may gate the out_clk when it is in
reset. This will stop the clock generators from getting a clock prior
removing the reset of the XCVR. The XCVR has a requirement of running
user clock while removing the reset. The correct sequence must be :
Enable device clocks (user clock)
Remove the reset from the XCVR
Reset CPACK from ADC TPL so during armed capture clear the cpack to avoid
capturing old samples.
Reset UNPACK with TPL to clear upack during armed transfers to avoid
sending old data.
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
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