3 Commits (0059c907eae443bf45e238f4897c4c863c2a74c5)

Author	SHA1	Message	Date
Istvan Csomortani	ac2e5a9dac	constraints: Update constraints ... Xilinx recommends that all synchronizer flip-flops have their ASYNC_REG property set to true in order to preserve the synchronizer cells through any logic optimization during synthesis and implementation.	2017-02-24 13:43:32 +02:00
Rejeesh Kutty	bb9cb86f34	adc/dac- fifo constraints	2016-08-11 10:00:41 -04:00
Istvan Csomortani	69d721526a	util_dacfifo: Add constraints file	2016-04-12 13:21:50 +03:00