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27 Commits (007a1ea3a4ecd0eb74763a9520873e28094e150b)

Author SHA1 Message Date
Rejeesh Kutty a74c61d6d5 vc707: gpio_bd changes 2015-03-23 10:00:46 -04:00
Adrian Costina 69326a72ef VC707: Updated base design 2015-03-20 18:20:44 +02:00
Istvan Csomortani d69d105b5d vc707_common: Fix address mapping 
The axi_ethernet/eth_buf/S_AXI_2TEMAC address space and axi_ethernet/eth_mac/s_axi/Reg address
segment does not exist in 2014.4.
 2015-01-29 12:22:06 +02:00
Istvan Csomortani e8ff30119d vc707_xdc: Delete unnecessary clock definition 2015-01-29 11:39:10 +02:00
Istvan Csomortani 6c8ea24f20 common: Update VC707 base design to 2014.4 2015-01-28 16:24:52 +02:00
Adrian Costina 71baa129a7 VC707: Fixed linear flash timings 2014-12-19 15:45:14 +02:00
Istvan Csomortani caa0268434 base_design: External IIC reset is connected to Vcc 
External IIC reset is connected to Vcc in case of AC701, KC705 and VC707
 2014-12-11 11:13:07 +02:00
Michael Hennerich 3cc890e604 projects/common: KCU105 VC707 update and sync axi_ethernet:6.1 features 
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
 2014-12-04 09:49:09 +01:00
Michael Hennerich 3bc9b25e96 projects/common: KCU105 VC707 KC705 sync microblaze core defaults 
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
 2014-12-04 09:47:02 +01:00
Adrian Costina 05ed98f884 common: Updated common constratins for ac701, kc705, vc707, zc702 2014-11-11 12:35:44 +02:00
Adrian Costina 4634a4f868 vc707: Added linear flash to the base design 2014-11-05 17:18:40 +02:00
Rejeesh Kutty 4788d09620 vc707: interrupt updates 2014-10-28 15:42:55 -04:00
Istvan Csomortani a870603db5 common_bd: Update the common block designs to the new IRQ path 
Avoid the use of xil_concat module by using the ad_interrupts.
 2014-10-27 19:44:25 +02:00
Istvan Csomortani dcdba475f7 vc707_common: Fix net name sys_100m_resetn 2014-10-22 15:41:36 +03:00
Lars-Peter Clausen 7d3be14ab5 common: Connect audio clkgen reset 
While we are at it also hide the unused locked pin.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-10-15 18:44:46 +03:00
Lars-Peter Clausen fd89458708 common: Set cpu interconnect strategy to minimize area 
There will rarely be concurrent access to the peripheral control bus
interconnect, so there is no need to optimize for performace. Setting the
interconnect strategy to minimize area can reduce the resource usage by
~90%.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-10-15 18:43:54 +03:00
Michael Hennerich a3dbd5ac00 projects/common/vc707/vc707_system_bd: AD9625_FMC update to 2014.2 
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
 2014-09-16 14:59:36 +02:00
Lars-Peter Clausen 41cc92ef49 Remove BASEADDR/HIGHADDR parameters 
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-09-11 12:26:37 +02:00
Michael Hennerich 647a26e19c projects/common/vc707/vc707_system_bd.tcl: Select Linux MMU settings 2014-09-10 17:40:36 +02:00
Rejeesh Kutty 877b81a373 ad9625/vc707: working version 2014-05-30 15:07:23 -04:00
Istvan Csomortani c5b3dd3643 vc707 base : tcl update 
- Added missing address space
    - Connect the sys_audio_clkgen/reset
 2014-05-08 12:30:25 +03:00
Istvan Csomortani fbafaa8507 MicroBlaze base system: Fix a few net names 
Every interconnect interface net name follows the convention:
	<interconnect name>_<interface name>
	No changes in logic or any connection!
 2014-04-01 10:40:35 +03:00
Adrian Costina a881557645 base_design: Fixed AC701 and VC707 contstraints 
AC701: Modified the IOSTANDARD for some of the pins to correspond to the
AC701 user guide.
VC707: Fixed naming for some system clocks
 2014-03-31 17:38:20 +03:00
Istvan Csomortani 0f10623be4 AC701/VC707: Define common variables 
Define variables sys_zynq, sys_mem_size, sys_addr_cntrl_space.
 2014-03-25 14:24:51 +02:00
Istvan Csomortani aa7b0bb4dd VC707 basesys: General fixes, actual status: working 
- Add an auxiliary cpu interconnect
	- Add an auxiliary interrupt concatenation module
	- Add new MIG file, current frequency of the DDR interface is 100
	  Mhz
	- Memory interconnect optimisation strategy is 'Maximize
	  Performance'
 2014-03-24 13:07:48 +02:00
Istvan Csomortani 75963ab376 Initial check in of VC707 base project 
- All source files for the VC707 base project
	- Update the common base system to the new naming convention
 2014-03-10 17:26:17 +02:00
Rejeesh Kutty ddac1a8834 added common board files 2014-02-28 21:17:01 -05:00