The constraints processing order changed to "late" instead of "early", in order for all the clocks in the system to be already created when the IP constraints are applied
While the reset for the memory mapped AXI master is synchronous to some
clock it is not necessarily synchronous to the clock used for that
interface. So always generate a local reset signal to avoid problems that
could result from this.
While we are at it also update the code to only generate a local reset if
the interface is asynchronous to the register map, otherwise use the
register map reset.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Ignore the timing path from the current DMA address to the register map,
this is just a debug signal at the moment.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
If the internal FIFO is larger than one block ram there will be multiple
BRAMs called ram_reg[0], ram_reg[1]. Modify the BRAM constraint rule so that
it matches these as well.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Set the ASYNC_REG property on the bit synchronizer CDC control regs. This
hint to Vivado that the registers are used for CDC purposes.
Also use -datapath_only for the set_max_delay constraints on the CDC data
path to remove the hold time requirement.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently the axi_hdmi_tx core constraints marks all its clocks asynchronous
to all other clocks in the system. This is a bit unfortunate as these
constraints are not restricted to the axi_hdmi_tx, but affect all cores in
the system, some of which might actually have timing constraints on CDC
paths.
The proper way to fix this is to add constraints for the axi_hdmi_tx core
CDC paths. For now only mark the interface clock asynchronous to the HDMI
clock, as this is easy to do and an improvement over the current situation,
as other cores are no longer affected.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The src_response_fifo has been removed from the design, but we still need to
assert the ready and empty control signals for things to work properly.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
We really only want to apply the CDC constraints if the clocks are actually
asynchronous. Unfortunately we can't use if ... inside a xdc script. But we
can use expr which has support for a ? b : c if-like expression. We can use
that to create helper variables that contains valid clock when the clock
domains are asynchronous or {} if they are not. Passing {} as
set_false_path/set_max_delay as either the source or destination will cause
it to abort and no constraints will be added.
Also add -quiet parameters to avoid generating warning if the constraints
could not be added.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
All the FPGA internal control signals are active high, using a active low
reset inserts a extra invert LUT. By using a active high reset we can avoid
that.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.
The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
Adrian Costina
Istvan Csomortani
Lars-Peter Clausen