b84325d43f
fmcomms2: take into consideration both adc_r1 and dac_r1 for clock division selection
2017-01-13 13:56:04 +02:00
4b2602437f
util_clkdiv: Added Ultrascale support and switch to BUFGMUX_CTRL for glitch free switching
2017-01-13 13:54:07 +02:00
f003b5b35a
fmcjesdadc1: Reduce SYSREF period
2017-01-12 16:10:45 +02:00
1f7d19688a
Update Makefile
2017-01-12 15:58:32 +02:00
b59549053c
scripts/adi_ip: Fix adi_ip_infer_interfaces process
...
This patch is a complementary fix of 8b8c37 patch. And fix
all the 'infer interface' issues.
The adi_ip_infer_interfaces process was renamed to
adi_ip_infer_streaming_interfaces. Now the process just do
what its name suggest.
Affected cores were axi_dmac, axi_spdif_rx, axi_spdif_tx, axi_i2s_adi
and axi_usb_fx3. All these cores scripts were updated.
2017-01-12 12:15:33 +02:00
e77428c50e
fmcomms2: Added FIFOs for DAC and ADC paths so that the path works at l_clk / 2 or l_clk /4
...
- removed ILA
2017-01-11 18:12:35 +02:00
9b29941c77
util_clkdiv: Add constraint file
2017-01-11 18:11:53 +02:00
37d54bb984
fmcjesdadc1/a5gt- max delay fit only
2017-01-04 16:04:19 -05:00
8b74e911b8
fmcjesdadc1/a5gt- qr to ddio max delay
2017-01-04 14:10:44 -05:00
e4e5b30ade
fmcadc5: Integrate ad_sysref_gen into the project
2017-01-03 13:52:39 +02:00
14ded4f123
fmcjeadadc1/a5soc- ad_sysref_gen updates
2016-12-22 15:59:45 -05:00
b089173b4c
fmcjesdadc1/a5soc- cpu clock is 50m for a5gt also
2016-12-22 14:14:21 -05:00
aa6c94c993
usdrx1/a5gt: ddr3 use ip constraints
2016-12-22 14:14:21 -05:00
18660c7ab4
fmcjesdadc1/a5gt: ddr3 use ip constraints
2016-12-22 14:14:21 -05:00
2bea337aa2
fmcjesdadc1/a5gt- use 50m-mem-cpu-clk
2016-12-22 14:14:21 -05:00
5d683943ab
fmcjesdadc1/a5gt- remove ad-sysref-gen-pack
2016-12-22 14:14:21 -05:00
f1168f9e29
fmcjesdadc1/a5gt- use xilinx setup 2-dma
2016-12-22 14:14:21 -05:00
1ceec2e2a9
projects/a5gt- use 50m afi clock for cpu- xcvr reconfig timing
2016-12-22 14:14:21 -05:00
eba30b0cde
projects/altera- qii_auto_pack option
2016-12-22 14:14:21 -05:00
c78c9cf633
util_fir_int: Updated coefficient file
2016-12-21 10:06:56 +02:00
4a783d523d
projects/altera* - default & common qsys commands
2016-12-20 16:27:44 -05:00
c0a2ef1ac4
library- altera power up warnings
2016-12-20 16:18:15 -05:00
3e57ff1fc5
z-mpsoc- map 0x4-0x8,0x7-0x9
2016-12-20 16:14:38 -05:00
ca8b479cee
Merge branch 'hdl_2016_r2' into dev
2016-12-20 12:41:57 +02:00
1156aeac16
ad_sysref_gen: Update SYSREF related constraints
2016-12-19 18:07:05 +02:00
ce47cf8d30
ad_sysref_gen: Fix sysref generation
...
Toggle sysref output just if the sysref_en is asserted.
2016-12-19 18:02:49 +02:00
a48c4a41bc
Merge branch 'hdl_2016_r2' into dev
2016-12-19 15:41:03 +00:00
180c96bcde
Update .gitignore
2016-12-19 15:37:05 +00:00
da7f4608a8
fmcjesdadc1/usdrx1: Clean up the mess
...
Delete accidentally commited generated files.
2016-12-19 15:35:20 +00:00
468214fd34
Merge branch 'hdl_2016_r2' into dev
2016-12-19 14:43:52 +00:00
f47863bbcf
usdrx1: Integrate ad_syref_gen into the project
2016-12-19 14:36:01 +00:00
8d799d0316
fmcjesdadc1: Intergrate ad_sysref_gen into project
2016-12-19 13:37:29 +00:00
0c42e04bc3
fmcadc2: Integrate ad_sysref_gen into the project
2016-12-19 12:16:05 +00:00
67390c2a95
ad6676evb: Update projects with ad_sysref_gen
2016-12-19 10:52:25 +00:00
a228c05bd3
common: Add a SYSREF generation module
...
The SYSREF generator is using a simple free running counter,
which runs on the JESD204 core clock. The period can be
configured using a parameter, it must respect the constraints
defined by the JESD204 standard.
The generator can be enabled through a GPIO line.
2016-12-17 11:12:10 +02:00
dc70807de2
Merge branch 'hdl_2016_r2' into dev
2016-12-16 16:21:09 +00:00
8879218502
a5gte: Fixed timing violations
2016-12-16 15:37:51 +02:00
596d0fa3fb
axi_ad9122: Add a constraint for a false path
2016-12-16 12:07:40 +00:00
a00d9870be
axi_ip_constr: Fix constraints
...
Modify a contraint for a false path, so it will be applied to
up_delay_cntr module too.
2016-12-16 12:01:38 +00:00
c0b0f9b7e9
ad6676evb: Connect SYS_REF to GPIO
2016-12-14 17:55:50 +02:00
557efed5d9
ad6676evb: Update clock constraints
2016-12-14 17:55:49 +02:00
3a2c889115
ad6676evb: Update GT configuration
2016-12-14 17:55:49 +02:00
905c7ccf99
Merge branch 'hdl_2016_r2' into dev
...
Merging commmits : c455d2d88461411515b6fd5165cad962614
2016-12-13 19:48:47 +02:00
d962614000
usdrx1/zc706: Disabele axi_spi constraint file
...
The interface ports of the AXI SPI IP are not connected
directly to a IOBUF, this results in a CRITICAL WARNING
2016-12-13 19:23:51 +02:00
d5165ca81f
motcon_fmc: Tie unused pins to GND
2016-12-13 19:20:13 +02:00
1515b6f1af
fmcomms7/zc706: Disabele axi_spi constraint file
...
The interface ports of the AXI SPI IP are not connected
directly to a IOBUF, this results in a CRITICAL WARNING
2016-12-13 19:18:18 +02:00
8846141467
fmcomms1/kc705: Disabele axi_spi constraint file
...
The interface ports of the AXI SPI IP are not connected
directly to a IOBUF, this results in a CRITICAL WARNING
2016-12-13 19:16:31 +02:00
c455d2d64f
fmcadc2/vc707: Disabele axi_spi constraint file
...
The interface ports of the AXI SPI IP are not connected
directly to a IOBUF, this results in a CRITICAL WARNING
2016-12-13 19:15:44 +02:00
9fb7db97da
a5gte: Fixed timing violations
2016-12-13 10:30:24 +02:00
99f72a9b3b
util_gtlb: this core is obsoleted
...
The util_gtlb core is obsoleted by xilinx/axi_xcvrlb
2016-12-12 14:23:47 +02:00
Adrian Costina
Istvan Csomortani
Rejeesh Kutty
AndreiGrozav