zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
646 Commits
1 Branch
0 Tags
23 MiB
Commit Graph

275 Commits (01b3495a81cf08c53e4e88bc99119879263217c7)

Author SHA1 Message Date
Rejeesh Kutty a4724f8396 es: added kcu105 gth 2014-11-17 09:55:12 -05:00
Rejeesh Kutty b1c91fac92 es: added kcu105 gth 2014-11-17 09:55:10 -05:00
Rejeesh Kutty fd305f2eff es: added kcu105 gth 2014-11-17 09:55:09 -05:00
Adrian Costina 6dd1226696 axi_ad9643: Fixed constraint file 2014-11-17 12:12:09 +02:00
Adrian Costina 8831d9dbd7 axi_ad9122: fixed constraint file 2014-11-17 12:11:20 +02:00
Adrian Costina 2744d0cb37 util_wfifo: Update to implement flip flops 2014-11-17 12:10:21 +02:00
Rejeesh Kutty 41ffc66c26 fifo2s: removed m interface 2014-11-13 15:00:03 -05:00
Rejeesh Kutty 8761db438e axi_fifo2f: common interface with fifo2s 2014-11-12 15:15:32 -05:00
Rejeesh Kutty 925e966eb6 axi_fifo2s: fifo full replaced with ready 2014-11-12 14:43:47 -05:00
Rejeesh Kutty 5fc4f1b000 axi_fifo2s: buswidth fix 2014-11-12 14:43:46 -05:00
Rejeesh Kutty d204a7c2b7 axi_fifo2s: include bus width/clock transfer 2014-11-12 14:43:44 -05:00
Rejeesh Kutty e7cec7171e axi_fifo2s: include bus width/clock transfer 2014-11-12 14:43:43 -05:00
Rejeesh Kutty 4381f20a6a axi_fifo2s: include bus width/clock transfer 2014-11-12 14:43:42 -05:00
Rejeesh Kutty 9f2dbad539 axi_fifo2s: include bus width/clock transfer 2014-11-12 14:43:41 -05:00
Rejeesh Kutty e683b5868e axi_fifo2s: include bus width/clock transfer 2014-11-12 14:43:40 -05:00
Rejeesh Kutty 81b4cd532d axi_fifo2s: include bus width/clock transfer 2014-11-12 14:43:38 -05:00
Rejeesh Kutty 888ab888d2 axi_fifo2s: include bus width/clock transfer 2014-11-12 14:43:37 -05:00
Istvan Csomortani f8e7796592 axi_jesd_gt: Fix lane number parameters 2014-11-12 17:43:32 +02:00
Istvan Csomortani bf62665c56 prcfg_qpsk: Add Simulink model 
Matlab version used: R2014a, HDL Coder 3.3
 2014-11-12 15:44:38 +02:00
Rejeesh Kutty 64ec633438 gt: asymmetric no of lanes 2014-11-11 08:54:24 -05:00
Rejeesh Kutty cb15567a56 ad6676: added 2014-11-10 13:36:07 -05:00
Istvan Csomortani c6df568a00 Revert "ad_interrupts: Initial check in." 
This reverts commit b254380338.
 2014-11-06 12:16:52 +02:00
Rejeesh Kutty b11d80ed98 ad_rst: changed to dual stage 2014-11-05 16:48:02 -05:00
Rejeesh Kutty 74ec396b27 ad_rst: ultrascale -dual stage 2014-11-05 16:47:41 -05:00
Rejeesh Kutty d69ccebbde ad9234: full 16bit samples 2014-11-05 11:59:08 -05:00
Rejeesh Kutty 403fe1b373 wfifo: read only if ready is asserted 2014-10-31 13:05:17 -04:00
Adrian Costina 38652b1c3e axi_ad9643: Added constraint file 2014-10-31 17:57:47 +02:00
Adrian Costina 3e9ce71d21 axi_ad9122: Added constraint file 2014-10-31 17:56:56 +02:00
Istvan Csomortani d596d71285 prcfg_qpsk: Swap the I/Q pair nets between the filter and the demodulator. 
This fix the wrong symbol mapping issue.
 2014-10-31 12:14:52 +02:00
Istvan Csomortani eb520b1f75 prcfg_qpsk: Major update 
Add a symbol wrapper to the logic. Wraps the 32 bit data to 2 bit symbols.
 2014-10-31 12:10:59 +02:00
Istvan Csomortani ea194755e1 prcfg: Upgrade the QPSK logic 
Regenerate the qpsk logic, with the new HDL coder, and modify the design to support the new files.
 2014-10-31 11:59:29 +02:00
Rejeesh Kutty 9818bcb601 axi_fifo2f: internal memory low overhead 2014-10-30 11:12:10 -04:00
Rejeesh Kutty 17cb1d9585 common/mem: asymmetric version 2014-10-30 11:12:09 -04:00
Rejeesh Kutty 6470ea91ad axi_fifo2f: fake version 2014-10-30 11:12:08 -04:00
Lars-Peter Clausen f9628262aa axi_dmac: Add xfer_req signal to the streamin AXI source interface 
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-10-29 18:15:54 +01:00
Adrian Costina fbce64411e axi_ad9671: added synchronization interface to altera core 2014-10-29 18:20:26 +02:00
acozma 36c7034bd6 ad7175: Fix dma issues 2014-10-28 16:00:06 +02:00
acozma 9c8fe5f09c ad7175: Removed unused files 2014-10-28 14:30:41 +02:00
acozma 9e1d1c1b49 ad7175: Updated the AD7175 IP and project 2014-10-28 14:28:38 +02:00
Istvan Csomortani b254380338 ad_interrupts: Initial check in. 
Initial check in of the interrupt concatenation block.
 2014-10-27 19:34:34 +02:00
Adrian Costina e086f5eb9f axi_ad9361: Updated core with the new up_adc_common register set 2014-10-27 19:26:40 +02:00
Rejeesh Kutty 7e52cf9568 up_axi: timeout generating multiple/repeated acks 2014-10-23 13:51:33 -04:00
Istvan Csomortani 3dbfa8cda6 ad9434_fmc: Fix PN monitor and device interrupt 2014-10-23 11:29:14 +03:00
acozma b9ca616150 Merge branch 'dev' of https://github.com/analogdevicesinc/hdl into dev 2014-10-23 06:11:52 +03:00
acozma da8454ae4c axi_ad7175: Added the AD7175 IP 2014-10-23 06:11:41 +03:00
Rejeesh Kutty 6f723ef9e5 axi_jesd_gt: lane mux on char qualifiers 2014-10-22 15:29:25 -04:00
Adrian Costina fe92b8b210 axi_ad9671: Updated synchronization mechanism to have a software defined starting code 2014-10-22 13:10:28 +03:00
Adrian Costina 121a416916 axi_dmac: Fixed constraints for axi_dmac core 2014-10-22 13:07:55 +03:00
Adrian Costina 1d26639d73 common: Added synchronization mechanism to the up_adc_common module 2014-10-22 10:05:55 +03:00
Istvan Csomortani 4b19646ed9 ad9434_fmc: Fix samples order. 
Four consecutive samples were reversed.
 2014-10-21 16:34:28 +03:00