Commit Graph

67 Commits (01de117b5f823e56003e2c2f63058bbe9e446d88)

Author SHA1 Message Date
Adrian Costina 01de117b5f motor_control: Changed controller to PID controller. Some estetic changes 2014-04-28 17:57:51 +03:00
Rejeesh Kutty fa998a406b dma: parameter fix 2014-04-24 15:50:16 -04:00
Rejeesh Kutty 314ec3d343 altera-9250/dma: make id width generic 2014-04-24 14:54:19 -04:00
Rejeesh Kutty dfc2bba335 ad9671: updates to allow default adc setup routines 2014-04-23 16:39:28 -04:00
Adrian Costina 213e852e11 motor_control: Initial commit 2014-04-18 18:57:18 +03:00
Rejeesh Kutty 503096de18 gt: change userready on drp clock 2014-04-17 16:09:55 -04:00
ATofan 570ec26798 FMCOMMS2: Added sync option 2014-04-11 18:14:48 +03:00
ATofan 99ef34936f Merge branch 'master' of https://github.com/analogdevicesinc/hdl 2014-04-11 18:14:08 +03:00
U-ANALOG\ACostina c73390b6c9 axi_ad9361: Intermediary check in for altera porting
This is work in progress. It will not work as it is
2014-04-11 17:40:34 +03:00
Rejeesh Kutty af07f8874f wfifo/rfifo: asynchronous interface 2014-04-10 14:01:40 -04:00
Rejeesh Kutty 96541f0a7f usdrx1: zc706 updated for usdrx1 2014-04-10 11:05:13 -04:00
Lars-Peter Clausen dc7b3e085c axi_dmac: Fix issues with non 64-bit AXI masters
Make sure that the address generator behaves correctly when the buswidth is not
64-bit. Also since the source and destination can have different widths add
separate parameters for source and destination address alignment.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 14:54:22 +02:00
Lars-Peter Clausen 36ef882da0 axi_dmac: data_mover: Improve timing
We do not know which 'last' condition to use before hand, but we can pre-compute
the result for both conditions and then use them. This removes the comparison
from the already pretty long combinatorial path.

Also simplify a few expressions.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 14:06:44 +02:00
Lars-Peter Clausen 090d3aee04 axi_dmac: Change C_DMA_LENGTH_WIDTH default to 24
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
Lars-Peter Clausen cb630e36a9 axi_dmac: src_fifo_inf: Simplify data path
Improves timing a bit

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
Lars-Peter Clausen f9ca4fb8be axi_fifo: Slightly improve timing
It is OK to overwrite invalid data with other invalid data.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
Lars-Peter Clausen 4c9647f289 axi_dmac: axi_register_slice: Provide default values for registers
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
Lars-Peter Clausen fa5ba6c09d axi_dmac: Make cyclic mode runtime configurable
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
Lars-Peter Clausen 7ca43f4920 axi_dmac: address_generator: Make 'len' registered
Slightly improves the timing.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
Lars-Peter Clausen 66e6c1cc21 axi_dmac: axi_register_slice: Remove reset "latch" from datapath
Move the datapath updates out of the else branch of the reset condition.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
Lars-Peter Clausen 799d2384d8 up_xfer_cntrl: Remove extra semicolon
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
ATofan 9d19145713 Merge branch 'master' of https://github.com/analogdevicesinc/hdl 2014-04-10 10:50:53 +03:00
ATofan 5aac9d7288 FMCOMMS2 added sync option
Added signals to allow synchronisation of multiple AD9361.
2014-04-10 10:46:42 +03:00
Istvan Csomortani e73952a694 ad9467 : initial checkin 2014-04-09 17:34:40 +03:00
Rejeesh Kutty 8bebc5e3d4 ad9671: initial checkin 2014-04-07 13:01:10 -04:00
Rejeesh Kutty f8f2684b7e up_gt: eyescan delay bug fix 2014-04-02 16:45:41 -04:00
Rejeesh Kutty e85153b5dd altera hal version 2014-04-01 21:12:11 -04:00
Rejeesh Kutty 80e5051894 axi_jesd_gt: initial checkin 2014-04-01 15:14:28 -04:00
Rejeesh Kutty 2472d61daf ad_gt_es: status asserted early for latency 2014-04-01 15:06:51 -04:00
Rejeesh Kutty 0d678b89ed altera a5gt fmcjesdadc1 setup 2014-04-01 11:46:37 -04:00
Rejeesh Kutty 724bd70a06 altera additions and replacements 2014-04-01 11:18:10 -04:00
Rejeesh Kutty 25f416e46f dds output is reset if disabled 2014-03-31 10:01:49 -04:00
Rejeesh Kutty d3d26e1220 lower the address space requirements 2014-03-26 11:03:45 -04:00
Lars-Peter Clausen 9b4539b7c2 axi_dmac: Add option to configure the FIFO size
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-26 12:51:35 +01:00
Lars-Peter Clausen ca7a70650d axi_dmac: Delay up_ack by one clock cycle
The read data also becomes available only with a delay of one clock cycle,
sending the ack too early will result in bogus register reads.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-25 14:35:52 +01:00
Lars-Peter Clausen b3657b77cb util_sync_reset: Fix polarity of the sync_resetn signal
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-25 13:03:12 +01:00
Lars-Peter Clausen a230e6505a axi_dmac: Add option to configure AXI standard 2014-03-25 12:47:27 +01:00
Lars-Peter Clausen d0e26899a4 Add util_sync_reset helper module
This helper module can be used to make sure that a reset signal is de-asserted
synchronously to a clock signal. This is e.g. required by the AXI spec.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-24 22:43:01 +01:00
Rejeesh Kutty ef960a29c7 altera files 2014-03-24 13:27:27 -04:00
Adrian Costina 551319a670 Modified data mover to improve timing 2014-03-20 18:22:18 +02:00
Lars-Peter Clausen e373b85954 axi_dmac: Fix Vivado warnings
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-18 20:59:13 +01:00
Lars-Peter Clausen 29d590c951 axi_dmac: response_generator: Do not generate responses during ID sync
During an ID sync the request_id might increment, we should not generate a
response in this case. Since the ID sync only happens when the core is disabled
check that the core is enabled before generating a response.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-18 19:12:13 +01:00
Lars-Peter Clausen df1c4f0786 axi_dmac: data_mover: Improve timing
The pending_burst signal and the expression id != request_id are almost
identical. pending_burst goes high with a delay of one clock cycle, but the
important thing is that it goes low on the same clock cycle as the expression.
By using pending_burst here instead of 'id != request_id' we can reduce the
fanout of the 'id' register and improve the timing of the core.
2014-03-18 19:06:26 +01:00
Lars-Peter Clausen 522a222d3a axi_dmac: Fix default value for DMA type
Vivado doesn't handle the case where we use symbolic constants for the default
value properly, so update this to use plain integers.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-17 13:20:49 +01:00
Rejeesh Kutty ad491e92ab changed pcore version and made it local (top shouldn't override) 2014-03-14 12:02:16 -04:00
Lars-Peter Clausen f02ba999ae axi_dmac: Add support for DMA bus widths other than 64 bit
There were a few place in the core where it assumed a 64-bit wide bus. Make this
configurable using parameters. The patch also adds support for having different
DMA bus widths on the source and destination side.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-13 13:20:10 +01:00
Rejeesh Kutty fd14607da5 mult instances: consistent naming style 2014-03-12 15:42:47 -04:00
Rejeesh Kutty 64a89ff66b Merge branch 'master' of github.com:analogdevicesinc/hdl 2014-03-12 15:36:00 -04:00
Rejeesh Kutty 7fc5b8ecd9 common: use dsp slice for multiply modules 2014-03-12 15:35:21 -04:00
Istvan Csomortani ba484999b3 Fix default value of $ad_hdl_dir and $ad_phdl_dir 2014-03-12 18:18:47 +02:00