Rejeesh Kutty
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0291bb3bf7
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util_rfifo: port name fixes & doc.
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2015-01-06 16:15:51 -05:00 |
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Rejeesh Kutty
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36b041ccc0
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util_wfifo: port name fixes & doc.
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2015-01-06 16:15:42 -05:00 |
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Rejeesh Kutty
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ee0912eb6a
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ad9361: make 2t2r external for mw
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2015-01-05 10:54:23 -05:00 |
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Rejeesh Kutty
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1d6ea64d04
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up_gt: move status to up clock
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2014-12-16 08:48:13 -05:00 |
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Rejeesh Kutty
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16f64a75d6
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fifo2s: false path typo on source signals
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2014-12-15 13:00:13 -05:00 |
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Rejeesh Kutty
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04c10abc2f
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gth/gtx: share same cpll/qpll cpu settings
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2014-12-11 11:18:48 -05:00 |
Istvan Csomortani
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19732d89fb
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plddr3: Fix the adc_dwr pulse width
The adc_dwr signal pulse width was to long, need to be just one adc_clk cycle.
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2014-12-09 13:51:00 +02:00 |
Adrian Costina
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6f8c259961
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axi_hdmi_tx: Fixed typo in altera related core
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2014-12-09 09:56:14 +02:00 |
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Adrian Costina
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a70d27c094
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axi_mc_speed: updated core to latest axi interface implementation
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2014-12-05 11:53:11 +02:00 |
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Adrian Costina
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26f58914e2
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axi_mc_current_monitor: updated core to latest axi interface implementation
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2014-12-05 11:53:06 +02:00 |
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Adrian Costina
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7e8e1e4fd0
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axi_mc_controller: updated core to latest axi interface implementation
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2014-12-05 11:52:59 +02:00 |
Lars-Peter Clausen
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8cc9adfc49
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up_axi: Fix up_raddr/up_waddr port width
Make sure that the port declaration width matches with the reg declaration
later on.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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2014-12-01 13:22:28 +01:00 |
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Rejeesh Kutty
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afddc45ba4
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library/ccat: initial commit
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2014-11-25 12:59:51 -05:00 |
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Rejeesh Kutty
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196e8b119c
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library/bsplit: initial commit
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2014-11-25 12:59:50 -05:00 |
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Rejeesh Kutty
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403f8c0631
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util_cpack: ipi doesn't like local params
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2014-11-21 15:32:13 -05:00 |
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Rejeesh Kutty
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3b500bafcc
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util_cpack: add port controls on ipi
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2014-11-21 15:32:12 -05:00 |
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Rejeesh Kutty
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5ca2944b70
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library/util_cpack: initial checkin
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2014-11-21 15:32:10 -05:00 |
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Istvan Csomortani
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42874bfe81
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prcfg_library: Major update
Get rid of the QPSK symbol wrapper for now. The DMA data path is using the 2 LSB bits.
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2014-11-18 10:05:52 +02:00 |
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Rejeesh Kutty
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a4724f8396
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es: added kcu105 gth
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2014-11-17 09:55:12 -05:00 |
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Rejeesh Kutty
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b1c91fac92
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es: added kcu105 gth
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2014-11-17 09:55:10 -05:00 |
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Rejeesh Kutty
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fd305f2eff
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es: added kcu105 gth
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2014-11-17 09:55:09 -05:00 |
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Adrian Costina
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6dd1226696
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axi_ad9643: Fixed constraint file
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2014-11-17 12:12:09 +02:00 |
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Adrian Costina
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8831d9dbd7
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axi_ad9122: fixed constraint file
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2014-11-17 12:11:20 +02:00 |
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Adrian Costina
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2744d0cb37
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util_wfifo: Update to implement flip flops
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2014-11-17 12:10:21 +02:00 |
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Rejeesh Kutty
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41ffc66c26
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fifo2s: removed m interface
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2014-11-13 15:00:03 -05:00 |
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Rejeesh Kutty
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8761db438e
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axi_fifo2f: common interface with fifo2s
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2014-11-12 15:15:32 -05:00 |
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Rejeesh Kutty
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925e966eb6
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axi_fifo2s: fifo full replaced with ready
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2014-11-12 14:43:47 -05:00 |
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Rejeesh Kutty
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5fc4f1b000
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axi_fifo2s: buswidth fix
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2014-11-12 14:43:46 -05:00 |
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Rejeesh Kutty
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d204a7c2b7
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axi_fifo2s: include bus width/clock transfer
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2014-11-12 14:43:44 -05:00 |
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Rejeesh Kutty
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e7cec7171e
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axi_fifo2s: include bus width/clock transfer
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2014-11-12 14:43:43 -05:00 |
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Rejeesh Kutty
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4381f20a6a
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axi_fifo2s: include bus width/clock transfer
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2014-11-12 14:43:42 -05:00 |
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Rejeesh Kutty
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9f2dbad539
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axi_fifo2s: include bus width/clock transfer
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2014-11-12 14:43:41 -05:00 |
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Rejeesh Kutty
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e683b5868e
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axi_fifo2s: include bus width/clock transfer
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2014-11-12 14:43:40 -05:00 |
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Rejeesh Kutty
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81b4cd532d
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axi_fifo2s: include bus width/clock transfer
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2014-11-12 14:43:38 -05:00 |
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Rejeesh Kutty
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888ab888d2
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axi_fifo2s: include bus width/clock transfer
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2014-11-12 14:43:37 -05:00 |
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Istvan Csomortani
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f8e7796592
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axi_jesd_gt: Fix lane number parameters
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2014-11-12 17:43:32 +02:00 |
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Istvan Csomortani
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bf62665c56
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prcfg_qpsk: Add Simulink model
Matlab version used: R2014a, HDL Coder 3.3
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2014-11-12 15:44:38 +02:00 |
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Rejeesh Kutty
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64ec633438
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gt: asymmetric no of lanes
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2014-11-11 08:54:24 -05:00 |
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Rejeesh Kutty
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cb15567a56
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ad6676: added
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2014-11-10 13:36:07 -05:00 |
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Istvan Csomortani
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c6df568a00
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Revert "ad_interrupts: Initial check in."
This reverts commit b254380338.
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2014-11-06 12:16:52 +02:00 |
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Rejeesh Kutty
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b11d80ed98
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ad_rst: changed to dual stage
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2014-11-05 16:48:02 -05:00 |
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Rejeesh Kutty
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74ec396b27
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ad_rst: ultrascale -dual stage
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2014-11-05 16:47:41 -05:00 |
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Rejeesh Kutty
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d69ccebbde
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ad9234: full 16bit samples
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2014-11-05 11:59:08 -05:00 |
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Rejeesh Kutty
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403fe1b373
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wfifo: read only if ready is asserted
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2014-10-31 13:05:17 -04:00 |
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Adrian Costina
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38652b1c3e
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axi_ad9643: Added constraint file
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2014-10-31 17:57:47 +02:00 |
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Adrian Costina
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3e9ce71d21
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axi_ad9122: Added constraint file
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2014-10-31 17:56:56 +02:00 |
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Istvan Csomortani
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d596d71285
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prcfg_qpsk: Swap the I/Q pair nets between the filter and the demodulator.
This fix the wrong symbol mapping issue.
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2014-10-31 12:14:52 +02:00 |
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Istvan Csomortani
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eb520b1f75
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prcfg_qpsk: Major update
Add a symbol wrapper to the logic. Wraps the 32 bit data to 2 bit symbols.
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2014-10-31 12:10:59 +02:00 |
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Istvan Csomortani
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ea194755e1
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prcfg: Upgrade the QPSK logic
Regenerate the qpsk logic, with the new HDL coder, and modify the design to support the new files.
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2014-10-31 11:59:29 +02:00 |
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Rejeesh Kutty
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9818bcb601
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axi_fifo2f: internal memory low overhead
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2014-10-30 11:12:10 -04:00 |